Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967601
C. Caloz, T. Itoh
A parametric characterization of the recently discovered anisotropic UC-PBG-GP is proposed. Simulated and measured transmission parameters are shown for several anisotropic PBGs with different numbers of unit cells. The results reveal two fundamental properties of the structure: First, its working range can be tuned by varying the number of cells in the propagation direction (PD), that is the overall length of the step-impedance slots; Second, in the attenuation direction (AD), the number unit cells can be reduced to two or three without degradation of the performances, which leads to a very compact size of the order of /spl lambda//2/spl times//spl lambda//7. In all the cases, the existence of a working range with good transmission in the PD and broad/deep gap with sharp cutoff in the AD is demonstrated.
{"title":"Characterization of the novel anisotropic uniplanar compact photonic band-gap ground plane (UC-PBG-GP)","authors":"C. Caloz, T. Itoh","doi":"10.1109/EPEP.2001.967601","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967601","url":null,"abstract":"A parametric characterization of the recently discovered anisotropic UC-PBG-GP is proposed. Simulated and measured transmission parameters are shown for several anisotropic PBGs with different numbers of unit cells. The results reveal two fundamental properties of the structure: First, its working range can be tuned by varying the number of cells in the propagation direction (PD), that is the overall length of the step-impedance slots; Second, in the attenuation direction (AD), the number unit cells can be reduced to two or three without degradation of the performances, which leads to a very compact size of the order of /spl lambda//2/spl times//spl lambda//7. In all the cases, the existence of a working range with good transmission in the PD and broad/deep gap with sharp cutoff in the AD is demonstrated.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"34 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121002545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967626
Li Li, B. Cook, M. Veatch
In this paper we introduce an improved RF dielectric measurement technique based on the Agilent 4291A Impedance Analyzer and 16453A Dielectric Material Test Fixture covering frequencies ranging from 1 MHz to 1 GHz. The measurement structure is a simple parallel plate capacitor with the material under test serving as the dielectric. Obtaining consistent data requires careful sample preparation and accurate alignment between the 16453A electrodes. We describe our procedures for creating flat, polished, metallized samples starting with encapsulant samples in their liquid form. Data for a variety of encapsulants are shown. The technique is readily extendable to solid materials, and we include data for selected samples of LTCC substrates as well as a MAPBGA molding compound.
{"title":"Measurement of RF properties of glob top and under-encapsulant materials","authors":"Li Li, B. Cook, M. Veatch","doi":"10.1109/EPEP.2001.967626","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967626","url":null,"abstract":"In this paper we introduce an improved RF dielectric measurement technique based on the Agilent 4291A Impedance Analyzer and 16453A Dielectric Material Test Fixture covering frequencies ranging from 1 MHz to 1 GHz. The measurement structure is a simple parallel plate capacitor with the material under test serving as the dielectric. Obtaining consistent data requires careful sample preparation and accurate alignment between the 16453A electrodes. We describe our procedures for creating flat, polished, metallized samples starting with encapsulant samples in their liquid form. Data for a variety of encapsulants are shown. The technique is readily extendable to solid materials, and we include data for selected samples of LTCC substrates as well as a MAPBGA molding compound.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967630
Dong-ho Han, Yuan-liang Li
A new TR method being implemented on CPW lines is described. To validate the method, a known material, alumina (99.6%), was tested over a wide frequency range (45 MHz to 10 GHz). The results show significant improvement on the characterization of loss tangent. More importantly, the method does not introduce any divergent solutions; therefore there is no need of extra numerical treatments in finding stable solutions.
{"title":"Complex dielectric constant measurement techniques for high-speed signaling","authors":"Dong-ho Han, Yuan-liang Li","doi":"10.1109/EPEP.2001.967630","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967630","url":null,"abstract":"A new TR method being implemented on CPW lines is described. To validate the method, a known material, alumina (99.6%), was tested over a wide frequency range (45 MHz to 10 GHz). The results show significant improvement on the characterization of loss tangent. More importantly, the method does not introduce any divergent solutions; therefore there is no need of extra numerical treatments in finding stable solutions.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126644326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967619
M.F. Davis, A. Sutono, A. Obatoyinbo, Sandip Chakraborty, K. Lim, S. Pinel, J. Laskar, S. Lee, R. Tummala
Presents the design, and measurement of RF-microwave multilayer interconnects and integrated passives implemented in a fully-organic system on package(SOP) technology. A CPW-microstrip interconnect scheme demonstrates a measured insertion loss of 1.7 dB at 12 GHz and a return loss better than 20 dB to 12 GHz. The novel hollow ground plane inductor configuration exhibits Q and effective inductance(Leff) enhancement by a factor of 2.5 and 2, respectively with SRF to 14 GHz. In addition, compact filters have also been designed for Optical Sub-Carrier Multiplexing(OSCM) link applications. These developments suggest the feasibility of building highly integrated organic-based radio front-end SOP.
{"title":"Integrated RF function architectures in fully-organic SOP technology","authors":"M.F. Davis, A. Sutono, A. Obatoyinbo, Sandip Chakraborty, K. Lim, S. Pinel, J. Laskar, S. Lee, R. Tummala","doi":"10.1109/EPEP.2001.967619","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967619","url":null,"abstract":"Presents the design, and measurement of RF-microwave multilayer interconnects and integrated passives implemented in a fully-organic system on package(SOP) technology. A CPW-microstrip interconnect scheme demonstrates a measured insertion loss of 1.7 dB at 12 GHz and a return loss better than 20 dB to 12 GHz. The novel hollow ground plane inductor configuration exhibits Q and effective inductance(Leff) enhancement by a factor of 2.5 and 2, respectively with SRF to 14 GHz. In addition, compact filters have also been designed for Optical Sub-Carrier Multiplexing(OSCM) link applications. These developments suggest the feasibility of building highly integrated organic-based radio front-end SOP.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967653
Yong Wang, V. Jandhyala, C. Shi
This paper presents a triangular surface mesh-based formulation of the Partial Element Equivalent Circuit (PEEC) approach. Rao-Wilton-Glisson (RWG) basis functions defined on triangular tessellations are used to model arbitrarily-shaped conducting structures via SPICE compatible netlists. This approach is potentially useful for modeling on-chip electromagnetic interactions.
{"title":"Coupled electromagnetic-circuit simulation of arbitrarily-shaped conducting structures","authors":"Yong Wang, V. Jandhyala, C. Shi","doi":"10.1109/EPEP.2001.967653","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967653","url":null,"abstract":"This paper presents a triangular surface mesh-based formulation of the Partial Element Equivalent Circuit (PEEC) approach. Rao-Wilton-Glisson (RWG) basis functions defined on triangular tessellations are used to model arbitrarily-shaped conducting structures via SPICE compatible netlists. This approach is potentially useful for modeling on-chip electromagnetic interactions.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125986655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967668
P. Walling, A. F. Tai, H. Hamel, R. Weekly, A. Haridass
This paper describes a high performance multi-layer ceramic (MLC) four chip glass-ceramic multi-chip module (MCM) that achieves very high bandwidth and low latency performance by incorporating unique design approaches and features. These include leveraging an I/O ring pattern arrangement using the fine line capability of IBM's High Performance Glass Ceramic (HPGC) and the capability to use 30+ wiring layers with isolating reference planes. The attendant signal integrity is assured by providing a tailored reference structure to control impedance and cross-talk coupling while maintaining the chip C4 I/O area density without requiring thin-films or degrading the power integrity.
{"title":"High bandwidth low latency chip to chip interconnects using high performance MLC glass ceramic POWER4/sup R/ MCM","authors":"P. Walling, A. F. Tai, H. Hamel, R. Weekly, A. Haridass","doi":"10.1109/EPEP.2001.967668","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967668","url":null,"abstract":"This paper describes a high performance multi-layer ceramic (MLC) four chip glass-ceramic multi-chip module (MCM) that achieves very high bandwidth and low latency performance by incorporating unique design approaches and features. These include leveraging an I/O ring pattern arrangement using the fine line capability of IBM's High Performance Glass Ceramic (HPGC) and the capability to use 30+ wiring layers with isolating reference planes. The attendant signal integrity is assured by providing a tailored reference structure to control impedance and cross-talk coupling while maintaining the chip C4 I/O area density without requiring thin-films or degrading the power integrity.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117033204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967627
H. Liang, J. Laskar, M. Hyslop
In this paper, a broad band Through-Line-Line (TLL) de-embedding technique is presented for accurate measurement and characterization of millimeter-wave devices. It is especially useful when the adapter or the launch is over one-quarter wavelength for which the traditional adapter-removal calibration is not applicable. The algorithm and the implementation of the TLL components are explained in detail. The applicability of the TLL technique has been demonstrated from DC to 50 GHz by an application to the de-embedding of a millimeter-wave BGA package measurement.
{"title":"A broad band Through-Line-Line de-embedding technique for BGA package measurements","authors":"H. Liang, J. Laskar, M. Hyslop","doi":"10.1109/EPEP.2001.967627","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967627","url":null,"abstract":"In this paper, a broad band Through-Line-Line (TLL) de-embedding technique is presented for accurate measurement and characterization of millimeter-wave devices. It is especially useful when the adapter or the launch is over one-quarter wavelength for which the traditional adapter-removal calibration is not applicable. The algorithm and the implementation of the TLL components are explained in detail. The applicability of the TLL technique has been demonstrated from DC to 50 GHz by an application to the de-embedding of a millimeter-wave BGA package measurement.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134012743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967656
K. Coperich, Jason Money, Andreas C. Cangellark, A. Ruehli
The development of a physically consistent multi-conductor transmission line model for high-speed interconnects in lossy, dispersive dielectrics is presented. Based on this model, a methodology is proposed for the construction of SPICE-compatible equivalent circuits that take into account dielectric loss and dispersion.
{"title":"Physically consistent transmission line models for high-speed interconnects in lossy dielectrics","authors":"K. Coperich, Jason Money, Andreas C. Cangellark, A. Ruehli","doi":"10.1109/EPEP.2001.967656","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967656","url":null,"abstract":"The development of a physically consistent multi-conductor transmission line model for high-speed interconnects in lossy, dispersive dielectrics is presented. Based on this model, a methodology is proposed for the construction of SPICE-compatible equivalent circuits that take into account dielectric loss and dispersion.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967628
Jiming Song, F. Ling, G. Flynn, W. Blood, E. Demircan
In general, three parameters are needed to model symmetrical adapters, but not enough equations can be found to solve them. The measurement of through adapters gives two conditions only, but neither open nor short adapter gives any useful condition. The results from lines with length L and length 2L can be used to derive the result for through adapters. This paper proposes one approach with a 2-impedance model, which has one shunt impedance and one series impedance. This model can be used with more complicated structures than the single impedance model.
{"title":"A de-embedding technique for interconnects","authors":"Jiming Song, F. Ling, G. Flynn, W. Blood, E. Demircan","doi":"10.1109/EPEP.2001.967628","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967628","url":null,"abstract":"In general, three parameters are needed to model symmetrical adapters, but not enough equations can be found to solve them. The measurement of through adapters gives two conditions only, but neither open nor short adapter gives any useful condition. The results from lines with length L and length 2L can be used to derive the result for through adapters. This paper proposes one approach with a 2-impedance model, which has one shunt impedance and one series impedance. This model can be used with more complicated structures than the single impedance model.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116678070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967666
A. Sarangi, G. Ji, T. Arabi, G. Taylor
This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.
{"title":"Design and performance evaluation of Pentium/sup R/ III microprocessor packaging","authors":"A. Sarangi, G. Ji, T. Arabi, G. Taylor","doi":"10.1109/EPEP.2001.967666","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967666","url":null,"abstract":"This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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