Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967636
Chung-Chi Huang, L. Tsang, D. Miller, A. Tripathi
Modeling of multiple via coupling is an important problem in the design of high-speed interconnect systems. It is known that the inter-via coupling has non-negligible effects on the signal integrity of high-speed circuits. In this paper, we investigate first order multi-via coupling based on a two-coupled-vias model. Analytical results are compared with experimental data up to 5GHz. Transient waveforms were obtained for reflection and transmission for trapezoidal and Gaussian input.
{"title":"Modeling of multi-vias coupling for high speed interconnects","authors":"Chung-Chi Huang, L. Tsang, D. Miller, A. Tripathi","doi":"10.1109/EPEP.2001.967636","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967636","url":null,"abstract":"Modeling of multiple via coupling is an important problem in the design of high-speed interconnect systems. It is known that the inter-via coupling has non-negligible effects on the signal integrity of high-speed circuits. In this paper, we investigate first order multi-via coupling based on a two-coupled-vias model. Analytical results are compared with experimental data up to 5GHz. Transient waveforms were obtained for reflection and transmission for trapezoidal and Gaussian input.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129496794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967619
M.F. Davis, A. Sutono, A. Obatoyinbo, Sandip Chakraborty, K. Lim, S. Pinel, J. Laskar, S. Lee, R. Tummala
Presents the design, and measurement of RF-microwave multilayer interconnects and integrated passives implemented in a fully-organic system on package(SOP) technology. A CPW-microstrip interconnect scheme demonstrates a measured insertion loss of 1.7 dB at 12 GHz and a return loss better than 20 dB to 12 GHz. The novel hollow ground plane inductor configuration exhibits Q and effective inductance(Leff) enhancement by a factor of 2.5 and 2, respectively with SRF to 14 GHz. In addition, compact filters have also been designed for Optical Sub-Carrier Multiplexing(OSCM) link applications. These developments suggest the feasibility of building highly integrated organic-based radio front-end SOP.
{"title":"Integrated RF function architectures in fully-organic SOP technology","authors":"M.F. Davis, A. Sutono, A. Obatoyinbo, Sandip Chakraborty, K. Lim, S. Pinel, J. Laskar, S. Lee, R. Tummala","doi":"10.1109/EPEP.2001.967619","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967619","url":null,"abstract":"Presents the design, and measurement of RF-microwave multilayer interconnects and integrated passives implemented in a fully-organic system on package(SOP) technology. A CPW-microstrip interconnect scheme demonstrates a measured insertion loss of 1.7 dB at 12 GHz and a return loss better than 20 dB to 12 GHz. The novel hollow ground plane inductor configuration exhibits Q and effective inductance(Leff) enhancement by a factor of 2.5 and 2, respectively with SRF to 14 GHz. In addition, compact filters have also been designed for Optical Sub-Carrier Multiplexing(OSCM) link applications. These developments suggest the feasibility of building highly integrated organic-based radio front-end SOP.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967622
S. Dalmia, Seock-Hee Lee, V. Sundaram, S. Min, M. Swaminathan, R. Tummala
The development of integrated passive components suitable for integration with printed wiring boards is relatively recent. This integration is required since in most mixed signal designs, off-passive components take up more real estate on the boards than the analog and digital signal processing units. Besides utilizing real estate on board, embedded passives on organic laminates significantly reduce cost and if optimized have less parasitics compared to discrete passive components. This paper discusses the design of high Q coplanar waveguide (CPW) planar inductors on laminates. The reason for choosing a CPW type layout is the ease in adding shunt elements and series elements compared to stripline and microstrip configurations. A max Q factor of 85 at 5.2 GHz was obtained for a 1.85 nH CPW type inductor. Several other inductors with similar performances were studied. The paper also presents a method to model the CPW type inductors. This approach allows designers to include metal-to-dielectric interface roughness, non-uniform signal line profiles and frequency dependent parameters such as the dielectric constant of materials.
{"title":"CPW high Q inductors on organic substrates","authors":"S. Dalmia, Seock-Hee Lee, V. Sundaram, S. Min, M. Swaminathan, R. Tummala","doi":"10.1109/EPEP.2001.967622","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967622","url":null,"abstract":"The development of integrated passive components suitable for integration with printed wiring boards is relatively recent. This integration is required since in most mixed signal designs, off-passive components take up more real estate on the boards than the analog and digital signal processing units. Besides utilizing real estate on board, embedded passives on organic laminates significantly reduce cost and if optimized have less parasitics compared to discrete passive components. This paper discusses the design of high Q coplanar waveguide (CPW) planar inductors on laminates. The reason for choosing a CPW type layout is the ease in adding shunt elements and series elements compared to stripline and microstrip configurations. A max Q factor of 85 at 5.2 GHz was obtained for a 1.85 nH CPW type inductor. Several other inductors with similar performances were studied. The paper also presents a method to model the CPW type inductors. This approach allows designers to include metal-to-dielectric interface roughness, non-uniform signal line profiles and frequency dependent parameters such as the dielectric constant of materials.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121897831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967653
Yong Wang, V. Jandhyala, C. Shi
This paper presents a triangular surface mesh-based formulation of the Partial Element Equivalent Circuit (PEEC) approach. Rao-Wilton-Glisson (RWG) basis functions defined on triangular tessellations are used to model arbitrarily-shaped conducting structures via SPICE compatible netlists. This approach is potentially useful for modeling on-chip electromagnetic interactions.
{"title":"Coupled electromagnetic-circuit simulation of arbitrarily-shaped conducting structures","authors":"Yong Wang, V. Jandhyala, C. Shi","doi":"10.1109/EPEP.2001.967653","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967653","url":null,"abstract":"This paper presents a triangular surface mesh-based formulation of the Partial Element Equivalent Circuit (PEEC) approach. Rao-Wilton-Glisson (RWG) basis functions defined on triangular tessellations are used to model arbitrarily-shaped conducting structures via SPICE compatible netlists. This approach is potentially useful for modeling on-chip electromagnetic interactions.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125986655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967630
Dong-ho Han, Yuan-liang Li
A new TR method being implemented on CPW lines is described. To validate the method, a known material, alumina (99.6%), was tested over a wide frequency range (45 MHz to 10 GHz). The results show significant improvement on the characterization of loss tangent. More importantly, the method does not introduce any divergent solutions; therefore there is no need of extra numerical treatments in finding stable solutions.
{"title":"Complex dielectric constant measurement techniques for high-speed signaling","authors":"Dong-ho Han, Yuan-liang Li","doi":"10.1109/EPEP.2001.967630","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967630","url":null,"abstract":"A new TR method being implemented on CPW lines is described. To validate the method, a known material, alumina (99.6%), was tested over a wide frequency range (45 MHz to 10 GHz). The results show significant improvement on the characterization of loss tangent. More importantly, the method does not introduce any divergent solutions; therefore there is no need of extra numerical treatments in finding stable solutions.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126644326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967626
Li Li, B. Cook, M. Veatch
In this paper we introduce an improved RF dielectric measurement technique based on the Agilent 4291A Impedance Analyzer and 16453A Dielectric Material Test Fixture covering frequencies ranging from 1 MHz to 1 GHz. The measurement structure is a simple parallel plate capacitor with the material under test serving as the dielectric. Obtaining consistent data requires careful sample preparation and accurate alignment between the 16453A electrodes. We describe our procedures for creating flat, polished, metallized samples starting with encapsulant samples in their liquid form. Data for a variety of encapsulants are shown. The technique is readily extendable to solid materials, and we include data for selected samples of LTCC substrates as well as a MAPBGA molding compound.
{"title":"Measurement of RF properties of glob top and under-encapsulant materials","authors":"Li Li, B. Cook, M. Veatch","doi":"10.1109/EPEP.2001.967626","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967626","url":null,"abstract":"In this paper we introduce an improved RF dielectric measurement technique based on the Agilent 4291A Impedance Analyzer and 16453A Dielectric Material Test Fixture covering frequencies ranging from 1 MHz to 1 GHz. The measurement structure is a simple parallel plate capacitor with the material under test serving as the dielectric. Obtaining consistent data requires careful sample preparation and accurate alignment between the 16453A electrodes. We describe our procedures for creating flat, polished, metallized samples starting with encapsulant samples in their liquid form. Data for a variety of encapsulants are shown. The technique is readily extendable to solid materials, and we include data for selected samples of LTCC substrates as well as a MAPBGA molding compound.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126573312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967627
H. Liang, J. Laskar, M. Hyslop
In this paper, a broad band Through-Line-Line (TLL) de-embedding technique is presented for accurate measurement and characterization of millimeter-wave devices. It is especially useful when the adapter or the launch is over one-quarter wavelength for which the traditional adapter-removal calibration is not applicable. The algorithm and the implementation of the TLL components are explained in detail. The applicability of the TLL technique has been demonstrated from DC to 50 GHz by an application to the de-embedding of a millimeter-wave BGA package measurement.
{"title":"A broad band Through-Line-Line de-embedding technique for BGA package measurements","authors":"H. Liang, J. Laskar, M. Hyslop","doi":"10.1109/EPEP.2001.967627","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967627","url":null,"abstract":"In this paper, a broad band Through-Line-Line (TLL) de-embedding technique is presented for accurate measurement and characterization of millimeter-wave devices. It is especially useful when the adapter or the launch is over one-quarter wavelength for which the traditional adapter-removal calibration is not applicable. The algorithm and the implementation of the TLL components are explained in detail. The applicability of the TLL technique has been demonstrated from DC to 50 GHz by an application to the de-embedding of a millimeter-wave BGA package measurement.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134012743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967656
K. Coperich, Jason Money, Andreas C. Cangellark, A. Ruehli
The development of a physically consistent multi-conductor transmission line model for high-speed interconnects in lossy, dispersive dielectrics is presented. Based on this model, a methodology is proposed for the construction of SPICE-compatible equivalent circuits that take into account dielectric loss and dispersion.
{"title":"Physically consistent transmission line models for high-speed interconnects in lossy dielectrics","authors":"K. Coperich, Jason Money, Andreas C. Cangellark, A. Ruehli","doi":"10.1109/EPEP.2001.967656","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967656","url":null,"abstract":"The development of a physically consistent multi-conductor transmission line model for high-speed interconnects in lossy, dispersive dielectrics is presented. Based on this model, a methodology is proposed for the construction of SPICE-compatible equivalent circuits that take into account dielectric loss and dispersion.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967628
Jiming Song, F. Ling, G. Flynn, W. Blood, E. Demircan
In general, three parameters are needed to model symmetrical adapters, but not enough equations can be found to solve them. The measurement of through adapters gives two conditions only, but neither open nor short adapter gives any useful condition. The results from lines with length L and length 2L can be used to derive the result for through adapters. This paper proposes one approach with a 2-impedance model, which has one shunt impedance and one series impedance. This model can be used with more complicated structures than the single impedance model.
{"title":"A de-embedding technique for interconnects","authors":"Jiming Song, F. Ling, G. Flynn, W. Blood, E. Demircan","doi":"10.1109/EPEP.2001.967628","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967628","url":null,"abstract":"In general, three parameters are needed to model symmetrical adapters, but not enough equations can be found to solve them. The measurement of through adapters gives two conditions only, but neither open nor short adapter gives any useful condition. The results from lines with length L and length 2L can be used to derive the result for through adapters. This paper proposes one approach with a 2-impedance model, which has one shunt impedance and one series impedance. This model can be used with more complicated structures than the single impedance model.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116678070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-29DOI: 10.1109/EPEP.2001.967666
A. Sarangi, G. Ji, T. Arabi, G. Taylor
This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.
{"title":"Design and performance evaluation of Pentium/sup R/ III microprocessor packaging","authors":"A. Sarangi, G. Ji, T. Arabi, G. Taylor","doi":"10.1109/EPEP.2001.967666","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967666","url":null,"abstract":"This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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