Micromachines最新文献

Radio photonic technologies have emerged as a promising solution for addressing microwave frequency synthesis challenges in current and future communication and sensing systems. One particularly effective approach is the optoelectronic oscillator (OEO), a simple and cost-effective electro-optical system. The OEO can generate microwave signals with low phase noise and high oscillation frequencies, often outperforming traditional electrical methods. However, a notable disadvantage of the OEO compared to conventional signal generation methods is its significant frequency tuning step. This paper presents a novel approach for continuously controlling the output frequency of an optoelectronic oscillator (OEO) based on integrated photonics. This is achieved by tuning an integrated optical delay line within a feedback loop. The analytical model developed in this study calculates the OEO's output frequency while accounting for nonlinear errors, enabling the consideration of various control schemes. Specifically, this study examines delay lines based on the Mach-Zehnder interferometer and microring resonators, which can be controlled by either the thermo-optic or electro-optic effect. To evaluate the model, we conducted numerical simulations using Ansys Lumerical software. The OEO that utilized an MRR-based electro-optical delay line demonstrated a tuning sensitivity of 174.5 MHz/V. The calculated frequency tuning sensitivity was as low as 6.98 kHz when utilizing the precision digital-to-analog converter with a minimum output voltage step of 40 μV. The proposed approach to controlling the frequency of the OEO can be implemented using discrete optical components; however, this approach restricts the minimum frequency tuning sensitivity. It provides an additional degree of freedom for frequency tuning within the OEO's operating range, which is ultimately limited by the amplitude-frequency characteristic of the notch filter. Thus, the proposed approach opens up new opportunities for increasing the accuracy and flexibility in generating microwave signals, which can be significant for various communications and radio engineering applications.

Based on additive manufacturing via photopolymerization, this study combines polymer-dispersed liquid crystal (PDLC) technology with 3D printing technology to produce tunable micro-optical components with switchable diffraction or focusing characteristics. The diffraction grating and Fresnel zone plate are the research targets. Their structures are designed and simulated to achieve expected optical functions. A liquid crystal display (LCD) 3D printer is used to produce structures on transparent conductive substrates. The printed structures are filled with PDLCs and covered with transparent conductive substrates to achieve tunable functions. The proposed configurations are implemented and verified. The experimental results show that the diffraction efficiency of the 0th order increases from 15% to 50% for the diffraction grating and the focusing spot intensity decreases from 74% to 12% after the application of an electric field. These results demonstrate the feasibility of the proposed tunable optical component configurations.

This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (V_T) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in V_T (ΔV_T) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔV_T is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔV_T during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔV_T with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device's thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems.

Direct energy deposition is an additive technology that can quickly manufacture irregularly shaped quartz-glass devices. Based on this technology and coaxial laser/wire feeding, open-loop tests were conducted under different process parameters. A closed-loop temperature control system was designed and built for the molten pool temperature in quartz-glass additive manufacturing. It was based on a PID (proportional-integral-derivative) control algorithm for adjusting laser power. Changes in the macroscopic morphology, microstructure, and other qualities of the final additive result before and after the temperature control of the quartz glass were examined. Relative to constant laser powers of 120 W and 140 W, the temperature control of the multi-pass single-layer lateral additives produced dense surface microstructures of the additively produced quartz glass, and the molding quality was better.

Silicon-glass anode bonding is the key technology in the process of wafer-level packaging for MEMS sensors. During the anodic bonding process, the device may experience adhesion failure due to the influence of electric field forces. A common solution is to add a metal shielding layer between the glass substrate and the device. In order to solve the problem of device failure caused by the electrostatic attraction phenomenon, this paper designed a double-ended solidly supported cantilever beam parallel plate capacitor structure, focusing on the study of the critical size of the window opening in the metal layer for the electric field shielding effect. The metal shield consists of 400 Å of Cr and 3400 Å of Au. Based on theoretical calculations, simulation analysis, and experimental testing, it was determined that the critical size for an individual opening in the metal layer is 180 μm × 180 μm, with the movable part positioned 5 μm from the bottom, which does not lead to failure caused by stiction due to electrostatic pull-in of the detection structure. It was proven that the metal shielding layer is effective in avoiding suction problems in secondary anode bonding.

Gate dielectrics are essential components in nanoscale field-effect transistors (FETs), but they often face significant instabilities when exposed to harsh environments, such as radioactive conditions, leading to unreliable device performance. In this paper, we evaluate the performance of ultrascaled transition metal dichalcogenide (TMD) FETs equipped with vacuum gate dielectric (VGD) as a means to circumvent oxide-related instabilities. The nanodevice is computationally assessed using a quantum simulation approach based on the self-consistent solutions of the Poisson equation and the quantum transport equation under the ballistic transport regime. The performance evaluation includes analysis of the transfer characteristics, subthreshold swing, on-state and off-state currents, current ratio, and scaling limits. Simulation results demonstrate that the investigated VGD TMD FET, featuring a gate-all-around (GAA) configuration, a TMD-based channel, and a thin vacuum gate dielectric, collectively compensates for the low dielectric constant of the VGD, enabling exceptional electrostatic control. This combination ensures superior switching performance in the ultrascaled regime, achieving a high current ratio and steep subthreshold characteristics. These findings position the GAA-VGD TMD FET as a promising candidate for advanced radiation-hardened nanoelectronics.

In this study, we aim to enhance the internal quantum efficiency (IQE) of AlGaN-based ultraviolet (UV) light-emitting diodes (LEDs) by using the short-period AlGaN/GaN superlattice as a tunnel junction (TJ) to construct polarized structures. We analyze in detail the effect of this polarized TJ on the carrier injection efficiency and investigate the increase in hole and electron density caused by the formation of 2D hole gas (2DHG) and 2D electron gas (2DEG) in the superlattice structure. In addition, a dielectric layer is introduced to evaluate the effect of stress changes on the tunneling probability and current spread in TJ. At a current of 140 mA, this method demonstrates effective current expansion. Our results not only improve the performance of UV LEDs but also provide an important theoretical and experimental basis for future research on UV LEDs based on superlattice TJ. In addition, our study also highlights the key role of group III nitride materials in achieving efficient UV luminescence, and the polarization characteristics and band structure of these materials are critical for optimizing carrier injection and recombination processes.

Aiming at the problem that ultrasonic detection is greatly affected by temperature drift, this paper investigates a novel temperature compensation algorithm. Ultrasonic impedance-based liquid-level measurement is a crucial non-contact, non-destructive technique. However, temperature drift can severely affect the accuracy of experimental measurements based on this technology. Theoretical analysis and experimental research on temperature drift phenomena are conducted in this study, accompanied by the proposal of a new compensation algorithm. Leveraging an external fixed-point liquid-level detection system experimental platform, the impact of temperature drift on ultrasonic echo energy and actual liquid-level height is examined. Experimental results demonstrate that temperature drift affects the speed and attenuation of ultrasonic waves, leading to decreased accuracy in measuring liquid levels. The proposed temperature compensation method yields an average relative error of 3.427%. The error range spans from 0.03 cm to 0.336 cm. The average relative error reduces by 21.535% compared with before compensation, showcasing its applicability across multiple temperature conditions and its significance in enhancing the accuracy of ultrasonic-based measurements.

An electromagnetic vibration energy harvester with a 2:1:2 internal resonance (IR) is proposed, allowing for the simultaneous activation of two IRs within the system in order to enhance its performance in terms of bandwidth and harvested power. The device consists of three magnetically coupled oscillators separated by an adjustable gap to tune the system eigenfrequencies and achieve a 2:1:2 IR. Numerical investigations are conducted to predict the behavior of the proposed device, and a multi-objective optimization procedure is employed to enhance the harvester's performance by introducing mass perturbations. The experimental validation of the optimized design is performed while highlighting the benefits of internal resonance, and the obtained results are in good agreement with the theoretical findings. The results indicate that incorporating two internal resonances into the harvester enhances its performance compared to the harvesters reported in the literature. The harvester achieves an SFoMBW of 7600 kg/m³, reflecting a high average power density over a broad bandwidth.

Reconfigurable processor-based acceleration of deep convolutional neural network (DCNN) algorithms has emerged as a widely adopted technique, with particular attention on sparse neural network acceleration as an active research area. However, many computing devices that claim high computational power still struggle to execute neural network algorithms with optimal efficiency, low latency, and minimal power consumption. Consequently, there remains significant potential for further exploration into improving the efficiency, latency, and power consumption of neural network accelerators across diverse computational scenarios. This paper investigates three key techniques for hardware acceleration of sparse neural networks. The main contributions are as follows: (1) Most neural network inference tasks are typically executed on general-purpose computing devices, which often fail to deliver high energy efficiency and are not well-suited for accelerating sparse convolutional models. In this work, we propose a specialized computational circuit for the convolutional operations of sparse neural networks. This circuit is designed to detect and eliminate the computational effort associated with zero values in the sparse convolutional kernels, thereby enhancing energy efficiency. (2) The data access patterns in convolutional neural networks introduce significant pressure on the high-latency off-chip memory access process. Due to issues such as data discontinuity, the data reading unit often fails to fully exploit the available bandwidth during off-chip read and write operations. In this paper, we analyze bandwidth utilization in the context of convolutional accelerator data handling and propose a strategy to improve off-chip access efficiency. Specifically, we leverage a compiler optimization plugin developed for Vitis HLS, which automatically identifies and optimizes on-chip bandwidth utilization. (3) In coefficient-based accelerators, the synchronous operation of individual computational units can significantly hinder efficiency. Previous approaches have achieved asynchronous convolution by designing separate memory units for each computational unit; however, this method consumes a substantial amount of on-chip memory resources. To address this issue, we propose a shared feature map cache design for asynchronous convolution in the accelerators presented in this paper. This design resolves address access conflicts when multiple computational units concurrently access a set of caches by utilizing a hash-based address indexing algorithm. Moreover, the shared cache architecture reduces data redundancy and conserves on-chip resources. Using the optimized accelerator, we successfully executed ResNet50 inference on an Intel Arria 10 1150GX FPGA, achieving a throughput of 497 GOPS, or an equivalent computational power of 1579 GOPS, with a power consumption of only 22 watts.