Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0362
Alvina Jean Tampos, Karl Villareal
Complementary Metal-Oxide Semiconductor (CMOS) Image Sensors are gaining popularity most especially in Automotive Safety and Advanced Driver-Assistance Systems (ADAS) applications. Customer application modules involve oftentimes a third party supplier. When failures involve interaction between an image sensor die and the customer's module, the Failure Analyst has to know the exact failure mechanism to pinpoint whether root cause is in the die fabrication (fab) or packaging assembly (third party supplier). Challenges can befall the analyst: failure modes can recover which renders the unit functional and laboratories most often do not have complete sophisticated analytical laboratory equipment for electrical testing, fault isolation and sample preparation. In this paper, a case study of a CMOS Image Sensor is presented wherein the failure mode recovered which was restored and how the structural limitations were overcome for fault isolation on both front- and back-side. A modified process flow was performed to visualize the defect through backside Focused Ion Beam (FIB) cross-section.
{"title":"Practical Methodologies in Restoring Initial Failure Mode and Backside Focused Ion Beam Cross-Section for Defect Visualization","authors":"Alvina Jean Tampos, Karl Villareal","doi":"10.31399/asm.cp.istfa2021p0362","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0362","url":null,"abstract":"\u0000 Complementary Metal-Oxide Semiconductor (CMOS) Image Sensors are gaining popularity most especially in Automotive Safety and Advanced Driver-Assistance Systems (ADAS) applications. Customer application modules involve oftentimes a third party supplier. When failures involve interaction between an image sensor die and the customer's module, the Failure Analyst has to know the exact failure mechanism to pinpoint whether root cause is in the die fabrication (fab) or packaging assembly (third party supplier). Challenges can befall the analyst: failure modes can recover which renders the unit functional and laboratories most often do not have complete sophisticated analytical laboratory equipment for electrical testing, fault isolation and sample preparation. In this paper, a case study of a CMOS Image Sensor is presented wherein the failure mode recovered which was restored and how the structural limitations were overcome for fault isolation on both front- and back-side. A modified process flow was performed to visualize the defect through backside Focused Ion Beam (FIB) cross-section.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129066495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0211
Han Han, T. Hantschel, P. Lagrain, C. Porret, R. Loo, M. Baryshnikova, B. Kunert, Libor Strakoš, T. Vystavěl
The physical limits of CMOS scaling, as predicted by Moore's Law, should have already been reached several years ago. However, the scaling of transistors is still ongoing due to continuous improvements in material quality enabling the fabrication of complex device structures with nm-size dimensions. More than ever, the structural properties and the eventual presence of crystalline defects in the various semiconductor materials (SiGe, III/V) play a critical role. Electron channeling contrast imaging (ECCI) is a powerful defect analysis technique developed in recent years. The technique allows for fast and non-destructive characterizations with the potential for extremely low detection limits. The analysis of lowly defective materials requires measurements over large areas to obtain statistically relevant data. Automated ECCI mapping routines enable the quantification of crystalline defect densities as low as ~1e5 cm-2, e.g., Si0.75Ge0.25 strain relaxed buffers (SRB) epitaxially grown on a Si substrate. Methods to reduce the total measurement time without compromising its sensitivity will be discussed. The measurement routine has also been optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers. Throughout these examples, this study demonstrates the great potential of ECCI as a versatile and industry-relevant technique for defect analysis.
{"title":"Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers","authors":"Han Han, T. Hantschel, P. Lagrain, C. Porret, R. Loo, M. Baryshnikova, B. Kunert, Libor Strakoš, T. Vystavěl","doi":"10.31399/asm.cp.istfa2021p0211","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0211","url":null,"abstract":"\u0000 The physical limits of CMOS scaling, as predicted by Moore's Law, should have already been reached several years ago. However, the scaling of transistors is still ongoing due to continuous improvements in material quality enabling the fabrication of complex device structures with nm-size dimensions. More than ever, the structural properties and the eventual presence of crystalline defects in the various semiconductor materials (SiGe, III/V) play a critical role. Electron channeling contrast imaging (ECCI) is a powerful defect analysis technique developed in recent years. The technique allows for fast and non-destructive characterizations with the potential for extremely low detection limits. The analysis of lowly defective materials requires measurements over large areas to obtain statistically relevant data. Automated ECCI mapping routines enable the quantification of crystalline defect densities as low as ~1e5 cm-2, e.g., Si0.75Ge0.25 strain relaxed buffers (SRB) epitaxially grown on a Si substrate. Methods to reduce the total measurement time without compromising its sensitivity will be discussed. The measurement routine has also been optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers. Throughout these examples, this study demonstrates the great potential of ECCI as a versatile and industry-relevant technique for defect analysis.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114244215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0012
Mukhil Azhagan Mallaiyan Sathiaseelan, Olivia P. Paradis, Rajat Rai, Suryaprakash Vasudev Pandurangi, Manoj Yasaswi Vutukuru, S. Taheri, N. Asadizanjani
In this manuscript, we present our work on Logo classification in PCBs for Hardware assurance purposes. Identifying and classifying logos have important uses for text detection, component authentication and counterfeit detection. Since PCB assurance faces the lack of a representative dataset for classification and detection tasks, we collect different variants of logos from PCBs and present data augmentation techniques to create the necessary data to perform machine learning. In addition to exploring the challenges for image classification tasks in PCBs, we present experiments using Random Forest classifiers, Bag of Visual Words (BoVW) using SIFT and ORB Fully Connected Neural Networks (FCN) and Convolutional Neural Network (CNN) architectures. We present results and also a discussion on the edge cases where our algorithms fail including the potential for future work in PCB logo detection. The code for the algorithms along with the dataset that includes 18 classes of logos with 14000+ images is provided at this link: https://www.trusthub.org/#/data Index Terms—AutoBoM, Logo classification, Data augmentation, Bill of materials, PCB Assurance, Hardware Assurance, Counterfeit avoidance
{"title":"Logo Classification and Data Augmentation Techniques for PCB Assurance and Counterfeit Detection","authors":"Mukhil Azhagan Mallaiyan Sathiaseelan, Olivia P. Paradis, Rajat Rai, Suryaprakash Vasudev Pandurangi, Manoj Yasaswi Vutukuru, S. Taheri, N. Asadizanjani","doi":"10.31399/asm.cp.istfa2021p0012","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0012","url":null,"abstract":"\u0000 In this manuscript, we present our work on Logo classification in PCBs for Hardware assurance purposes. Identifying and classifying logos have important uses for text detection, component authentication and counterfeit detection. Since PCB assurance faces the lack of a representative dataset for classification and detection tasks, we collect different variants of logos from PCBs and present data augmentation techniques to create the necessary data to perform machine learning. In addition to exploring the challenges for image classification tasks in PCBs, we present experiments using Random Forest classifiers, Bag of Visual Words (BoVW) using SIFT and ORB Fully Connected Neural Networks (FCN) and Convolutional Neural Network (CNN) architectures. We present results and also a discussion on the edge cases where our algorithms fail including the potential for future work in PCB logo detection. The code for the algorithms along with the dataset that includes 18 classes of logos with 14000+ images is provided at this link: https://www.trusthub.org/#/data\u0000 Index Terms—AutoBoM, Logo classification, Data augmentation, Bill of materials, PCB Assurance, Hardware Assurance, Counterfeit avoidance","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0418
Jonathan Scholl, Nick Darby, Joshua Baur, Y. Patel, I. Boona, K. Wickey, Jeremiah Schley
The integrated circuit (IC) delayering workflow is heavily reliant on operator experience to determine the processing end point, which is the ideal point on an IC where processing should be terminated, to optimize region of interest imaging. The current method of end point detection during IC delayering utilizes qualitative correlation between dielectric film color and dielectric thickness observed via optical microscopy to guide decision making. The goal of this work is to quantify this relationship using computer vision. In the field of computer vision, convolutional neural networks (CNNs) have been successfully applied to capture spatial relationships within images. Given this success, a CNN was trained for thickness estimates of dielectric films using optical images captured during processing for eventual automated end point detection. The trained model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm.
{"title":"Dielectric Film Thickness Measurement Via a Convolutional Neural Network for Integrated Circuit Delayering End Point Detection","authors":"Jonathan Scholl, Nick Darby, Joshua Baur, Y. Patel, I. Boona, K. Wickey, Jeremiah Schley","doi":"10.31399/asm.cp.istfa2021p0418","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0418","url":null,"abstract":"\u0000 The integrated circuit (IC) delayering workflow is heavily reliant on operator experience to determine the processing end point, which is the ideal point on an IC where processing should be terminated, to optimize region of interest imaging. The current method of end point detection during IC delayering utilizes qualitative correlation between dielectric film color and dielectric thickness observed via optical microscopy to guide decision making. The goal of this work is to quantify this relationship using computer vision. In the field of computer vision, convolutional neural networks (CNNs) have been successfully applied to capture spatial relationships within images. Given this success, a CNN was trained for thickness estimates of dielectric films using optical images captured during processing for eventual automated end point detection. The trained model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0430
T. Colpaert, S. Verleye
Frontside die inspection by Scanning Electron Microscopy (SEM) is critical to investigate failures that appear dispersed over the GaN die surface and that will be very difficult to localize by the typical Focus Ion Beam (FIB) or Transmission Electron Microscopy (TEM) analysis. Frontside sample preparation is; however, extremely challenging if the device was already subjected to sample preparation for backside Photo Emission Microscopy (PEM). In this paper, a novel sample preparation method is presented where all front side layers are removed and only the 5μm GaN die is left for inspection.
{"title":"A Novel Sample Preparation Method for Frontside Inspection of GaN Devices after Backside Analysis","authors":"T. Colpaert, S. Verleye","doi":"10.31399/asm.cp.istfa2021p0430","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0430","url":null,"abstract":"\u0000 Frontside die inspection by Scanning Electron Microscopy (SEM) is critical to investigate failures that appear dispersed over the GaN die surface and that will be very difficult to localize by the typical Focus Ion Beam (FIB) or Transmission Electron Microscopy (TEM) analysis. Frontside sample preparation is; however, extremely challenging if the device was already subjected to sample preparation for backside Photo Emission Microscopy (PEM). In this paper, a novel sample preparation method is presented where all front side layers are removed and only the 5μm GaN die is left for inspection.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0274
Hana Choi, Seo Jin Kim, C. H. Kang, C. Tsao
In semiconductor industry, planer analysis is important in many applications such as Passive Voltage Contrast (PVC) and sample preparation for nanoprobing. In order to achieve successful results on the planer surface analysis, a proper delayering technique is critical. As the thickness of metal line, via of Back-End-of Line (BEOL) and contact layer are getting thinner in advanced nodes, we observed convention hand polishing is facing major challenge in endpointing at exactly targeted layer and specific Region of Interest (ROI). In addition, Cobalt process starting from 5nm node brings additional challenges. Cobalt tends to be oxidized easily which becomes not friendly for nanoprobing. The alternative solution to produce good planar surface is to use Plasma Focus Ion Beam (PFIB) technique with patented DX gas assisted. PFIB changes the convention FA workflow and has been proven that the new workflow improves the efficiency of planar failure analysis such as PVC and nanoprobing sample preparation.
{"title":"A New Delayering Application Workflow in Advanced 5nm Technology Device with Xenon Plasma Focus Ion Beam Microscopy","authors":"Hana Choi, Seo Jin Kim, C. H. Kang, C. Tsao","doi":"10.31399/asm.cp.istfa2021p0274","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0274","url":null,"abstract":"\u0000 In semiconductor industry, planer analysis is important in many applications such as Passive Voltage Contrast (PVC) and sample preparation for nanoprobing. In order to achieve successful results on the planer surface analysis, a proper delayering technique is critical. As the thickness of metal line, via of Back-End-of Line (BEOL) and contact layer are getting thinner in advanced nodes, we observed convention hand polishing is facing major challenge in endpointing at exactly targeted layer and specific Region of Interest (ROI). In addition, Cobalt process starting from 5nm node brings additional challenges. Cobalt tends to be oxidized easily which becomes not friendly for nanoprobing. The alternative solution to produce good planar surface is to use Plasma Focus Ion Beam (PFIB) technique with patented DX gas assisted. PFIB changes the convention FA workflow and has been proven that the new workflow improves the efficiency of planar failure analysis such as PVC and nanoprobing sample preparation.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126073650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0320
Pan-Ki Kim, Hyungtae Kim, Youngdae Kim
As technology scales down, the density of Static Random Access Memory (SRAM) devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node. In addition, resistive defects and parametric defects are increasing which are hard to detect by the conventional test. Thus, the need of effective tests with high fault coverage and low cost increases. In this work, we study the reuse of assist technique (read and write assist) and timing margin control technique, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of hard-to-detect marginal defects. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits and timing control circuits can be leveraged to increase the defect coverage can be increases up to 28% at nominal operation voltage by simulation. Some successful case studies are also discussed to demonstrate the efficiency of the proposed electrical stress test methodology.
{"title":"Advanced Soft Defect Screen Methodology for Nano-Scale SRAM Yield Improvement","authors":"Pan-Ki Kim, Hyungtae Kim, Youngdae Kim","doi":"10.31399/asm.cp.istfa2021p0320","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0320","url":null,"abstract":"\u0000 As technology scales down, the density of Static Random Access Memory (SRAM) devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node. In addition, resistive defects and parametric defects are increasing which are hard to detect by the conventional test. Thus, the need of effective tests with high fault coverage and low cost increases. In this work, we study the reuse of assist technique (read and write assist) and timing margin control technique, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of hard-to-detect marginal defects. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits and timing control circuits can be leveraged to increase the defect coverage can be increases up to 28% at nominal operation voltage by simulation. Some successful case studies are also discussed to demonstrate the efficiency of the proposed electrical stress test methodology.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126650858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PCB Assurance currently relies on manual physical inspection, which is time consuming, expensive and prone to error. In this study, we propose a novel automated segmentation algorithm to detect and isolate PCB components from the boards called EC-Seg. Segmentation and component localization is a vital preprocessing step in component identification, component authentication, as well as in detecting logos and text markings in components. EC-Seg is an efficient method to automate Quality assurance tool-chains and also to aid Bill of Material Extraction in PCBs. Finally, EC-Seg can be used as a Region proposal algorithm for object detection networks to detect and classify microelectronic components, and also to perform sensor fusion with X-Rays to aid in artifact removal in PCB X-Ray tomography. Index Terms—PCB Hardware Assurance, Component Segmentation, Component detection, AutoBoM, Physical Inspection, Visual inspection, Counterfeit detection
{"title":"EC-SEG: Electronic Component Segmentation for PCB Assurance and Counterfeit Avoidance","authors":"Mukhil Azhagan Mallaiyan Sathiaseelan, Sudarshan Agrawal, Manoj Yasaswi Vutukuru, N. Asadizanjani","doi":"10.31399/asm.cp.istfa2021p0065","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0065","url":null,"abstract":"\u0000 PCB Assurance currently relies on manual physical inspection, which is time consuming, expensive and prone to error. In this study, we propose a novel automated segmentation algorithm to detect and isolate PCB components from the boards called EC-Seg. Segmentation and component localization is a vital preprocessing step in component identification, component authentication, as well as in detecting logos and text markings in components. EC-Seg is an efficient method to automate Quality assurance tool-chains and also to aid Bill of Material Extraction in PCBs. Finally, EC-Seg can be used as a Region proposal algorithm for object detection networks to detect and classify microelectronic components, and also to perform sensor fusion with X-Rays to aid in artifact removal in PCB X-Ray tomography.\u0000 Index Terms—PCB Hardware Assurance, Component Segmentation, Component detection, AutoBoM, Physical Inspection, Visual inspection, Counterfeit detection","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133873015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0001
Frederik Platter, Anna Safont-Andreu, C. Burmer, Konstantin Schekotihin
In their daily work, engineers in the Failure Analysis (FA) laboratory generate numerous documents reporting all their tasks, findings, and conclusions regarding every device they are handled. This data stores valuable knowledge for the laboratory that other experts can consult, however, the nature of it, as individual reports reporting concrete devices and their corresponding processes, makes it inefficient to consult for the human experts. In this context, the following paper proposes a Artificial Intelligence solution for the gathering of this FA knowledge stored in the numerous documents generated in the laboratory. Therefore, we have generated a dataset of FA reports along with their corresponding electrical signatures and physical failures in order to train different supervised classifiers. The results show that the models are able of capturing the patterns underlying the different jobs and predict the causes, showing slightly better results for the physical hypotheses.
{"title":"Report Classification for Semiconductor Failure Analysis","authors":"Frederik Platter, Anna Safont-Andreu, C. Burmer, Konstantin Schekotihin","doi":"10.31399/asm.cp.istfa2021p0001","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0001","url":null,"abstract":"\u0000 In their daily work, engineers in the Failure Analysis (FA) laboratory generate numerous documents reporting all their tasks, findings, and conclusions regarding every device they are handled. This data stores valuable knowledge for the laboratory that other experts can consult, however, the nature of it, as individual reports reporting concrete devices and their corresponding processes, makes it inefficient to consult for the human experts. In this context, the following paper proposes a Artificial Intelligence solution for the gathering of this FA knowledge stored in the numerous documents generated in the laboratory. Therefore, we have generated a dataset of FA reports along with their corresponding electrical signatures and physical failures in order to train different supervised classifiers. The results show that the models are able of capturing the patterns underlying the different jobs and predict the causes, showing slightly better results for the physical hypotheses.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114207471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0366
Karl Villareal, Rommel Estores, Peter Baert
The paper discusses an imaging sensor exhibiting a fast-to-rise sanity check failure from a scan chain test. The DUT was prepared for backside analysis in a portable daughter-card [1] that enabled the analyst to easily shift between testing platforms such as a standard imaging tester bench and compact scan diagnosis system [2], while being inspected under the Electro-Optical Probing (EOP) machine. To find a failing flip-flop in several-thousands long chain, broken scan chain analysis was performed to narrow down the search to a few chain links was implemented. EOP methods of fault isolation were employed to verify the location of the broken scan cell in those selected flip-flops. Finally, parallel lapping was done to confirm the location of the failing flip-flop under a SEM.
{"title":"Electro-Optical Probing for Capturing Fast-to-Rise Scan Chain Failures","authors":"Karl Villareal, Rommel Estores, Peter Baert","doi":"10.31399/asm.cp.istfa2021p0366","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0366","url":null,"abstract":"\u0000 The paper discusses an imaging sensor exhibiting a fast-to-rise sanity check failure from a scan chain test. The DUT was prepared for backside analysis in a portable daughter-card [1] that enabled the analyst to easily shift between testing platforms such as a standard imaging tester bench and compact scan diagnosis system [2], while being inspected under the Electro-Optical Probing (EOP) machine. To find a failing flip-flop in several-thousands long chain, broken scan chain analysis was performed to narrow down the search to a few chain links was implemented. EOP methods of fault isolation were employed to verify the location of the broken scan cell in those selected flip-flops. Finally, parallel lapping was done to confirm the location of the failing flip-flop under a SEM.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122408406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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