Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063122
K. Sankaragomathi, Jabeom Koo, R. Ruby, B. Otis
Multiple emerging wireless applications (body-worn devices and IoT, for example) will demand previously impossible thin-film form factors and low system cost. One key enabling technology for this paradigm is a new class of radios that offer cost/size approaching RFID while still maintaining peer-to-peer connectivity like more complex radios. These radios need to be cheap and thin, which means they should be fabricated using wafer-scale semiconductor processing. The existing paradigm (quartz crystals used as a frequency reference in radios) is a huge bottleneck in reducing cost and size of these devices. MEMS frequency references have replaced quartz crystals in some applications [1-3]. For example, [1] reports a MEMS reference with 0.5ppm stability but the power consumption (~100mW) and supply voltage (1.8V) are not suitable for low-voltage/low-power radios. [2] reports a 32kHz, 3ppm reference for mobile time-keeping applications, but is unsuitable for radio frequency synthesis due to its low output frequency. In this paper, we report a thin-Film Bulk-Acoustic-Resonator (FBAR) frequency reference suitable for low-voltage/low-power radio applications. The reported FBAR reference achieves a stability of +/- 3ppm from 0 to 90C. We achieve this by using an electronic temperature compensation scheme to improve the intrinsic +/-50ppm stability of an FBAR oscillator down to +/- 3ppm (Fig. 25.9.1). The core of the temperature compensation scheme is a temperature sensor that achieves a 1.75mK resolution at a 100mS sampling time.
{"title":"25.9 A ±3ppm 1.1mW FBAR frequency reference with 750MHz output and 750mV supply","authors":"K. Sankaragomathi, Jabeom Koo, R. Ruby, B. Otis","doi":"10.1109/ISSCC.2015.7063122","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063122","url":null,"abstract":"Multiple emerging wireless applications (body-worn devices and IoT, for example) will demand previously impossible thin-film form factors and low system cost. One key enabling technology for this paradigm is a new class of radios that offer cost/size approaching RFID while still maintaining peer-to-peer connectivity like more complex radios. These radios need to be cheap and thin, which means they should be fabricated using wafer-scale semiconductor processing. The existing paradigm (quartz crystals used as a frequency reference in radios) is a huge bottleneck in reducing cost and size of these devices. MEMS frequency references have replaced quartz crystals in some applications [1-3]. For example, [1] reports a MEMS reference with 0.5ppm stability but the power consumption (~100mW) and supply voltage (1.8V) are not suitable for low-voltage/low-power radios. [2] reports a 32kHz, 3ppm reference for mobile time-keeping applications, but is unsuitable for radio frequency synthesis due to its low output frequency. In this paper, we report a thin-Film Bulk-Acoustic-Resonator (FBAR) frequency reference suitable for low-voltage/low-power radio applications. The reported FBAR reference achieves a stability of +/- 3ppm from 0 to 90C. We achieve this by using an electronic temperature compensation scheme to improve the intrinsic +/-50ppm stability of an FBAR oscillator down to +/- 3ppm (Fig. 25.9.1). The core of the temperature compensation scheme is a temperature sensor that achieves a 1.75mK resolution at a 100mS sampling time.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132283977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062967
James Myers, Anand Savanth, D. Howard, Rohan Gaddh, Pranay Prabhat, D. Flynn
The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction.
{"title":"8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications","authors":"James Myers, Anand Savanth, D. Howard, Rohan Gaddh, Pranay Prabhat, D. Flynn","doi":"10.1109/ISSCC.2015.7062967","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062967","url":null,"abstract":"The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128236170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062952
Jaehyuk Choi, Jungsoon Shin, Dongwu Kang, Du-sik Park
Most mobile devices embed a CMOS image sensor (CIS) for capturing images. In addition, a variety of sensors such as proximity, ambient light, and fingerprint sensors are integrated for device control. The integration of multiple sensors in a device requires significant power consumption, area, and cost. In contrast to multiple sensors, an always-on CIS enables advanced smart sensing, including gesture sensing, face recognition, eye tracking, and so on. Smart sensing using a CIS offers a variety of user interfaces and experiences such as touch-less control, authentication, gaming, and object recognition for the Internet of Things (IOT). A major drawback of a CIS in mobile devices is that it consumes power greater than 50mW [1], and this is not feasible for always-on sensing that is required to function with the limited energy available from the device's battery. Moreover, power reduction in a CIS causes image degradation owing to reduced SNR, which is not acceptable for capturing high-quality images. Many low-power CISs have been reported [2-3]. However, they are inadequate for use as high-resolution sensors because of the requirement of additional in-pixel circuits for device operation at low supply voltages.
{"title":"6.3 A 45.5μW 15fps always-on CMOS image sensor for mobile and wearable devices","authors":"Jaehyuk Choi, Jungsoon Shin, Dongwu Kang, Du-sik Park","doi":"10.1109/ISSCC.2015.7062952","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062952","url":null,"abstract":"Most mobile devices embed a CMOS image sensor (CIS) for capturing images. In addition, a variety of sensors such as proximity, ambient light, and fingerprint sensors are integrated for device control. The integration of multiple sensors in a device requires significant power consumption, area, and cost. In contrast to multiple sensors, an always-on CIS enables advanced smart sensing, including gesture sensing, face recognition, eye tracking, and so on. Smart sensing using a CIS offers a variety of user interfaces and experiences such as touch-less control, authentication, gaming, and object recognition for the Internet of Things (IOT). A major drawback of a CIS in mobile devices is that it consumes power greater than 50mW [1], and this is not feasible for always-on sensing that is required to function with the limited energy available from the device's battery. Moreover, power reduction in a CIS causes image degradation owing to reduced SNR, which is not acceptable for capturing high-quality images. Many low-power CISs have been reported [2-3]. However, they are inadequate for use as high-resolution sensors because of the requirement of additional in-pixel circuits for device operation at low supply voltages.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063029
Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, S. A. Mirhaj, Yen-Cheng Kuan, H. Chen, C. Jou, M. Tsai, F. Hsueh, Mau-Chung Frank Chang
The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.
{"title":"14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB","authors":"Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, S. A. Mirhaj, Yen-Cheng Kuan, H. Chen, C. Jou, M. Tsai, F. Hsueh, Mau-Chung Frank Chang","doi":"10.1109/ISSCC.2015.7063029","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063029","url":null,"abstract":"The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLL's high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116163381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062913
Zhicheng Lin, Pui-in Mak, R. Martins
RF-tunable blocker-tolerant receivers (RXs) enhance the flexibility of multiband multistandard radios at low cost (Fig. 2.4.1). The mixer-first RX [1] delays the signal amplification to baseband (BB) by frequency-translating the BB lowpass response to RF as bandpass. This raises the out-of-band (OB) IIP3 (27dBm) at the expense of NF (5.5dB) and power (60mW) due to no RF gain. The noisecancellation RX [2] breaks such a tradeoff by paralleling a voltage-sensing RX with the mixer-first RX. This achieves a better pair of NF (1.9dB) and OB-IIP3 (13.5dBm), but sacrifices more die size (1.2mm2) and power (<;78mW) to accommodate the doubled RF and BB circuits. In [3], N-path RF filtering and noise cancellation are concurrently attained in one current-reuse RX. That approach saves die area (0.55mm2) and power (16.2mW) at a high OB-IIP3 (17.4dBm), but requires a high VDD (2.5V) to widen the voltage headroom. Also, seeing that its NF (4.6dB) is handicapped by the input-impedance matching requirement (S11<;-10dB), there is no flexibility to get better NF. Finally, as both [2] and [3] involve two mixing steps, the LO power is penalized.
{"title":"2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF","authors":"Zhicheng Lin, Pui-in Mak, R. Martins","doi":"10.1109/ISSCC.2015.7062913","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062913","url":null,"abstract":"RF-tunable blocker-tolerant receivers (RXs) enhance the flexibility of multiband multistandard radios at low cost (Fig. 2.4.1). The mixer-first RX [1] delays the signal amplification to baseband (BB) by frequency-translating the BB lowpass response to RF as bandpass. This raises the out-of-band (OB) IIP3 (27dBm) at the expense of NF (5.5dB) and power (60mW) due to no RF gain. The noisecancellation RX [2] breaks such a tradeoff by paralleling a voltage-sensing RX with the mixer-first RX. This achieves a better pair of NF (1.9dB) and OB-IIP3 (13.5dBm), but sacrifices more die size (1.2mm2) and power (<;78mW) to accommodate the doubled RF and BB circuits. In [3], N-path RF filtering and noise cancellation are concurrently attained in one current-reuse RX. That approach saves die area (0.55mm2) and power (16.2mW) at a high OB-IIP3 (17.4dBm), but requires a high VDD (2.5V) to widen the voltage headroom. Also, seeing that its NF (4.6dB) is handicapped by the input-impedance matching requirement (S11<;-10dB), there is no flexibility to get better NF. Finally, as both [2] and [3] involve two mixing steps, the LO power is penalized.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121714793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062945
Jongmi Lee, Youngwoo Ji, Seungnam Choi, Y. Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, J. Sim
Bandgap references (BGRs) are widely used to generate a temperature-insensitive reference voltage determined by the silicon bandgap. the BGR generally utilizes PN diodes to generate both of proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption, BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow eVD/(n·VT) to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.
{"title":"5.7 A 29nW bandgap reference circuit","authors":"Jongmi Lee, Youngwoo Ji, Seungnam Choi, Y. Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, J. Sim","doi":"10.1109/ISSCC.2015.7062945","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062945","url":null,"abstract":"Bandgap references (BGRs) are widely used to generate a temperature-insensitive reference voltage determined by the silicon bandgap. the BGR generally utilizes PN diodes to generate both of proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption, BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow eVD/(n·VT) to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121868241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062852
F. Meng, Kaixue Ma, K. Yeo
Single-pole double-throw (SPDT) switches are a key building block for enabling transceiver time-division duplexing (TDD) when operated as a T/R switch or for eliminating imager fluctuations when operated as a Dicke switch. To provide acceptable compromises of IMF, Pout and sensitivity in transceivers or imagers, the switches are required to feature an insertion loss of ~3dB and an isolation of ~20dB. Recently, mm-Wave/sub-mm-Wave transceiver and imager integrated circuits have gradually migrated to silicon platforms for low-cost consumer markets [1,2]. However, the associated SPDT switches operating beyond 110GHz are developed using advanced SOI or SiGe HBT technologies [3,4] and rarely implemented in CMOS due to the lossy substrate and poor transistor characteristics [2,5].
{"title":"2.3 A 130-to-180GHz 0.0035mm2 SPDT switch with 3.3dB loss and 23.7dB isolation in 65nm bulk CMOS","authors":"F. Meng, Kaixue Ma, K. Yeo","doi":"10.1109/ISSCC.2015.7062852","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062852","url":null,"abstract":"Single-pole double-throw (SPDT) switches are a key building block for enabling transceiver time-division duplexing (TDD) when operated as a T/R switch or for eliminating imager fluctuations when operated as a Dicke switch. To provide acceptable compromises of IMF, Pout and sensitivity in transceivers or imagers, the switches are required to feature an insertion loss of ~3dB and an isolation of ~20dB. Recently, mm-Wave/sub-mm-Wave transceiver and imager integrated circuits have gradually migrated to silicon platforms for low-cost consumer markets [1,2]. However, the associated SPDT switches operating beyond 110GHz are developed using advanced SOI or SiGe HBT technologies [3,4] and rarely implemented in CMOS due to the lossy substrate and poor transistor characteristics [2,5].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122086547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062957
Changbyung Park, Sungsoo Park, Kiduk Kim, Sang-Hui Park, Juwan Park, Yunhee Huh, Byunghoon Kang, G. Cho
Capacitive touch systems for finger touch have become widely used in mobile devices such as smartphones, tablets, and so on. Beyond ordinary touch functions, some devices adopt an extra electromagnetic resonance (EMR) system [1] to support pens for advanced user experiences; these devices have been successfully commercialized for high-end devices [2]. Such devices offer a realistic and accurate pen-based drawing experience for consumers using a battreryless, light, and pressure-sensitive pen; this is possible because the EMR system excites a passive pen via magnetic coupling and senses the pen's returning signal that contains coordinate and fine pen-pressure information. As shown in Fig. 6.8.1 (top), an EMR system, however, requires an additional costly sensor board made with a flexible printed circuit board beneath a display panel to find coordinates of the EMR pen via a magnetic field and a dedicated controller, and it also consumes excessive power. If a capacitive touch system could cover the function of the EMR system, it would be a cost-effective and compact solution in terms of re-utilizing an existing system without the additional sensor board and EMR controller. In this paper, a capacitive touch system sensing a passive pen with pen pressure as well as a finger is introduced as an alternative to an EMR system.
{"title":"6.8 A pen-pressure-sensitive capacitive touch system using electrically coupled resonance pen","authors":"Changbyung Park, Sungsoo Park, Kiduk Kim, Sang-Hui Park, Juwan Park, Yunhee Huh, Byunghoon Kang, G. Cho","doi":"10.1109/ISSCC.2015.7062957","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062957","url":null,"abstract":"Capacitive touch systems for finger touch have become widely used in mobile devices such as smartphones, tablets, and so on. Beyond ordinary touch functions, some devices adopt an extra electromagnetic resonance (EMR) system [1] to support pens for advanced user experiences; these devices have been successfully commercialized for high-end devices [2]. Such devices offer a realistic and accurate pen-based drawing experience for consumers using a battreryless, light, and pressure-sensitive pen; this is possible because the EMR system excites a passive pen via magnetic coupling and senses the pen's returning signal that contains coordinate and fine pen-pressure information. As shown in Fig. 6.8.1 (top), an EMR system, however, requires an additional costly sensor board made with a flexible printed circuit board beneath a display panel to find coordinates of the EMR pen via a magnetic field and a dedicated controller, and it also consumes excessive power. If a capacitive touch system could cover the function of the EMR system, it would be a cost-effective and compact solution in terms of re-utilizing an existing system without the additional sensor board and EMR controller. In this paper, a capacitive touch system sensing a passive pen with pen pressure as well as a finger is introduced as an alternative to an EMR system.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063147
Ken Chang, F. O’Mahony, E. Alon, Hyeon-Min Bae, N. D. Dalt, E. Fluhr
The demand for ultra-high speed transceivers continues to rise exponentially due to the insatiable demand for high-throughput interconnect. Standards between 25 and 32Gb/s are rapidly approaching maturity, and available products and IPs at these rates are iterating to push down power while extending channel-loss recovery limits. Predictably, specifications are now in early stages for extending per-lane bandwith to between 40 and 64Gb/s. Meeting these 25Gb/s+ targets, especially for long-reach applications, is stressing the capabilities of both the underlying circuitry and the communication channels, and has caused significant rethinking of the overall system and circuit architectures for these links. In particular, the debate about multi-level (PAM4) versus binary (PAM2) signaling and which path offers the best energy-efficiency/data-rate scalability has returned to the foreground. Similarly, the emergence of high-speed ADCs with sufficient resolution for link applications has driven renewed interest in DSP-based approaches, while other efforts have pushed more analog/mixed-signal link components to over 60Gb/s/lane. To further ensure low BER operations, sophisticated coding such as FEC is brought into the discussion. Even in the domain of optical communications, significant challenges related to the bandwidth capabilities of the optical devices as well as the back end processing are currently being addressed. In fact, some of the highest speed optical links are limited by the short electrical interconnect between the driver circuitry and the optical module itself. This forum presents state-of-the-art I/O techniques enabling such high line rates across both optical and electrical interfaces as well as a number of emerging standards such as 802.3bj, various flavors of CEI, and HMC (hybrid memory cube).
{"title":"F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data","authors":"Ken Chang, F. O’Mahony, E. Alon, Hyeon-Min Bae, N. D. Dalt, E. Fluhr","doi":"10.1109/ISSCC.2015.7063147","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063147","url":null,"abstract":"The demand for ultra-high speed transceivers continues to rise exponentially due to the insatiable demand for high-throughput interconnect. Standards between 25 and 32Gb/s are rapidly approaching maturity, and available products and IPs at these rates are iterating to push down power while extending channel-loss recovery limits. Predictably, specifications are now in early stages for extending per-lane bandwith to between 40 and 64Gb/s. Meeting these 25Gb/s+ targets, especially for long-reach applications, is stressing the capabilities of both the underlying circuitry and the communication channels, and has caused significant rethinking of the overall system and circuit architectures for these links. In particular, the debate about multi-level (PAM4) versus binary (PAM2) signaling and which path offers the best energy-efficiency/data-rate scalability has returned to the foreground. Similarly, the emergence of high-speed ADCs with sufficient resolution for link applications has driven renewed interest in DSP-based approaches, while other efforts have pushed more analog/mixed-signal link components to over 60Gb/s/lane. To further ensure low BER operations, sophisticated coding such as FEC is brought into the discussion. Even in the domain of optical communications, significant challenges related to the bandwidth capabilities of the optical devices as well as the back end processing are currently being addressed. In fact, some of the highest speed optical links are limited by the short electrical interconnect between the driver circuitry and the optical module itself. This forum presents state-of-the-art I/O techniques enabling such high line rates across both optical and electrical interfaces as well as a number of emerging standards such as 802.3bj, various flavors of CEI, and HMC (hybrid memory cube).","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123525843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063086
P. Harpe, Hao Gao, R. V. Dommele, E. Cantatore, A. Roermund
Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.
{"title":"21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC","authors":"P. Harpe, Hao Gao, R. V. Dommele, E. Cantatore, A. Roermund","doi":"10.1109/ISSCC.2015.7063086","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063086","url":null,"abstract":"Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：