Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063046
Recently, the demand for miniaturized and fast transient response power delivery systems has been growing in high-voltage industrial electronics applications. Gallium Nitride (GaN) FETs showing a superior figure of merit (Rds, ON X Qg) in comparison with silicon FETs [1] can enable both high-frequency and high-efficiency operation in these applications, thus making power converters smaller, faster and more efficient. However, the lack of GaN-compatible high-speed gate drivers is a major impediment to fully take advantage of GaN FET-based power converters. Conventional high-voltage gate drivers usually exhibit propagation delay, tdelay, of up to several 10s of ns in the level shifter (LS), which becomes a critical problem as the switching frequency, fsw, reaches the 10MHz regime. Moreover, the switching slew rate (SR) of driving GaN FETs needs particular care in order to maintain efficient and reliable operation. Driving power GaN FETs with a fast SR results in large switching voltage spikes, risking breakdown of low-Vgs GaN devices, while slow SR leads to long switching rise time, tR, which degrades efficiency and limits fsw. In [2], large tdelay and long tR in the GaN FET driver limit its fsw to 1MHz. A design reported in [3] improves tR to 1.2ns, thereby enabling fsw up to 10MHz. However, the unregulated switching dead time, tDT, then becomes a major limitation to further reduction of tde!ay. This results in limited fsw and narrower range of VIN-VO conversion ratio. Interleaved multiphase topologies can be the most effective way to increase system fsw. However, each extra phase requires a capacitor for bootstrapped (BST) gate driving which incurs additional cost and complexity of the PCB design. Moreover, the requirements of fsw synchronization and balanced current sharing for high fsw operation in multiphase implementation are challenging.
近年来，在高压工业电子应用中，对小型化和快速瞬态响应电力传输系统的需求不断增长。与硅fet相比，氮化镓(GaN) fet具有优越的性能(Rds, ON X Qg)，可以在这些应用中实现高频和高效率的工作，从而使功率变换器更小，更快，更高效。然而，缺乏与氮化镓兼容的高速栅极驱动器是充分利用氮化镓场效应晶体管功率变换器的主要障碍。传统的高压栅极驱动器在电平移位器(LS)中通常表现出高达10s / ns的传播延迟，当开关频率达到10MHz时，这成为一个关键问题。此外，驱动GaN场效应管的开关压转率(SR)需要特别注意，以保持高效可靠的运行。具有快速SR的驱动功率GaN fet会导致大的开关电压尖峰，有可能导致低vgs GaN器件击穿，而缓慢SR会导致长开关上升时间tR，从而降低效率并限制fsw。在b[2]中，GaN FET驱动器的大延迟和长tR限制了其fsw为1MHz。b[3]中报道的一种设计将tR提高到1.2ns，从而使fsw达到10MHz。然而，无规开关死区时间(tDT)成为进一步降低tDT的主要限制因素。这导致有限的fsw和较窄的VIN-VO转换比的范围。交错多相拓扑结构是提高系统fsw的最有效方法。然而，每个额外的相位都需要一个用于自举(BST)栅极驱动的电容器，这会带来额外的成本和PCB设计的复杂性。此外，在多相实现中，对fsw同步和均衡电流分担的要求是具有挑战性的。
{"title":"16.7 A 20V 8.4W 20MHz four-phase GaN DC-DC converter with fully on-chip dual-SR bootstrapped GaN FET driver achieving 4ns constant propagation delay and 1ns switching rise time","authors":"","doi":"10.1109/ISSCC.2015.7063046","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063046","url":null,"abstract":"Recently, the demand for miniaturized and fast transient response power delivery systems has been growing in high-voltage industrial electronics applications. Gallium Nitride (GaN) FETs showing a superior figure of merit (R<sub>ds, ON</sub> X Q<sub>g</sub>) in comparison with silicon FETs [1] can enable both high-frequency and high-efficiency operation in these applications, thus making power converters smaller, faster and more efficient. However, the lack of GaN-compatible high-speed gate drivers is a major impediment to fully take advantage of GaN FET-based power converters. Conventional high-voltage gate drivers usually exhibit propagation delay, t<sub>delay</sub>, of up to several 10s of ns in the level shifter (LS), which becomes a critical problem as the switching frequency, f<sub>sw</sub>, reaches the 10MHz regime. Moreover, the switching slew rate (SR) of driving GaN FETs needs particular care in order to maintain efficient and reliable operation. Driving power GaN FETs with a fast SR results in large switching voltage spikes, risking breakdown of low-V<sub>gs</sub> GaN devices, while slow SR leads to long switching rise time, t<sub>R</sub>, which degrades efficiency and limits f<sub>sw</sub>. In [2], large t<sub>delay</sub> and long t<sub>R</sub> in the GaN FET driver limit its f<sub>sw</sub> to 1MHz. A design reported in [3] improves t<sub>R</sub> to 1.2ns, thereby enabling f<sub>sw</sub> up to 10MHz. However, the unregulated switching dead time, t<sub>DT</sub>, then becomes a major limitation to further reduction of t<sub>de!ay</sub>. This results in limited f<sub>sw</sub> and narrower range of V<sub>IN</sub>-V<sub>O</sub> conversion ratio. Interleaved multiphase topologies can be the most effective way to increase system f<sub>sw</sub>. However, each extra phase requires a capacitor for bootstrapped (BST) gate driving which incurs additional cost and complexity of the PCB design. Moreover, the requirements of f<sub>sw</sub> synchronization and balanced current sharing for high f<sub>sw</sub> operation in multiphase implementation are challenging.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063024
Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, Seonghwan Cho
Since the advent of digital PLLs (DPLLs), various techniques have been proposed for a low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantization noise (q-noise) can be achieved without complex q-noise cancellation schemes, since the delta-sigma modulator (DSM) has a high oversampling ratio and its q-noise is pushed to higher frequencies. Second, noise requirements of PLL building blocks become less stringent as the division value is reduced. For a digital PLL using a Nyquist-rate time-to-digital converter (TDC), if the reference is multiplied by N the time resolution of the TDC can be reduced by √N for the same noise level. Unfortunately, one drawback of the reference-multiplied PLL is the increase in power and complexity due to the reference-multiplying circuit. In this paper, we propose a reference-multiplied digital fractional-N PLL that has negligible overhead in the reference-multiplying circuit. To save power, a frequency-multiplied TDC (FMTDC) consisting of an open-loop multiplying DLL (MDLL) and a Vernier delay-line (VDL) TDC is proposed, which share their delay lines. High spurious tone coming from the open-loop MDLL is canceled by an adaptive filter located between TDC and loop filter.
{"title":"14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS","authors":"Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, Seonghwan Cho","doi":"10.1109/ISSCC.2015.7063024","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063024","url":null,"abstract":"Since the advent of digital PLLs (DPLLs), various techniques have been proposed for a low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantization noise (q-noise) can be achieved without complex q-noise cancellation schemes, since the delta-sigma modulator (DSM) has a high oversampling ratio and its q-noise is pushed to higher frequencies. Second, noise requirements of PLL building blocks become less stringent as the division value is reduced. For a digital PLL using a Nyquist-rate time-to-digital converter (TDC), if the reference is multiplied by N the time resolution of the TDC can be reduced by √N for the same noise level. Unfortunately, one drawback of the reference-multiplied PLL is the increase in power and complexity due to the reference-multiplying circuit. In this paper, we propose a reference-multiplied digital fractional-N PLL that has negligible overhead in the reference-multiplying circuit. To save power, a frequency-multiplied TDC (FMTDC) consisting of an open-loop multiplying DLL (MDLL) and a Vernier delay-line (VDL) TDC is proposed, which share their delay lines. High spurious tone coming from the open-loop MDLL is canceled by an adaptive filter located between TDC and loop filter.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128052551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062947
D. Griffith, J. Murdock, P. T. Røine, T. Murphy
A dual mode crystal oscillator has been implemented that can be used both as the reference clock for the radio PLL in a high performance mode the sleep timer in a low power mode. The oscillator can switch seamlessly between the high performance and low power modes without losing the time base so that synchronization can be maintained among wireless nodes. This the wireless node to be implemented with a single crystal, enabling a low and small form factor design.
{"title":"5.9 A 37μW dual-mode crystal oscillator for single-crystal radios","authors":"D. Griffith, J. Murdock, P. T. Røine, T. Murphy","doi":"10.1109/ISSCC.2015.7062947","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062947","url":null,"abstract":"A dual mode crystal oscillator has been implemented that can be used both as the reference clock for the radio PLL in a high performance mode the sleep timer in a low power mode. The oscillator can switch seamlessly between the high performance and low power modes without losing the time base so that synchronization can be maintained among wireless nodes. This the wireless node to be implemented with a single crystal, enabling a low and small form factor design.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129985461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062917
Song Hu, S. Kousai, Hua Wang
Spectrum-efficient modulations in modern wireless systems often result in large peak-to-average power ratios (PAPRs) for the transmitted signals. Therefore, PA efficiency at deep power back-off (PBO) levels (e.g., -12dB) becomes critical to extend the mobile's battery life. Classic techniques, i.e., outphasing, envelope tracking, and Doherty PAs, offer marginal efficiency improvement at deep PBO in practice. Dual-mode PAs require switches at the PA output for high-/low-power mode selection [1,2], posing reliability and linearity challenges. Although simple supply switching (Class-G) is effective at deep PBO, it only offers Class-B-like PBO efficiency in each supply mode [3,4]. Multi-level outphasing PA requires multiple supplies and frequent supply switching [5], resulting in substantial DC-DC converter overhead and exacerbated switching noise.
{"title":"2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement","authors":"Song Hu, S. Kousai, Hua Wang","doi":"10.1109/ISSCC.2015.7062917","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062917","url":null,"abstract":"Spectrum-efficient modulations in modern wireless systems often result in large peak-to-average power ratios (PAPRs) for the transmitted signals. Therefore, PA efficiency at deep power back-off (PBO) levels (e.g., -12dB) becomes critical to extend the mobile's battery life. Classic techniques, i.e., outphasing, envelope tracking, and Doherty PAs, offer marginal efficiency improvement at deep PBO in practice. Dual-mode PAs require switches at the PA output for high-/low-power mode selection [1,2], posing reliability and linearity challenges. Although simple supply switching (Class-G) is effective at deep PBO, it only offers Class-B-like PBO efficiency in each supply mode [3,4]. Multi-level outphasing PA requires multiple supplies and frequent supply switching [5], resulting in substantial DC-DC converter overhead and exacerbated switching noise.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126364160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063127
Barosaim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Hojin Park, S. Ryu
Recently reported high-speed ADCs have mostly taken advantage of time-interleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexity arising from the calibrations has often become a considerable burden. In order to reduce the number of channels in TI SAR ADCs, a flash-assisted TI (FATI) SAR structure [1] can be utilized to enhance the conversion speed of a sub-channel SAR ADC due to the multi-bit MSBs from a front-end flash ADC. In addition, because the codes from each SAR ADC embed the timing skew information of the corresponding channel, the structure can extract timing skew information in an efficient manner [2]. Despite these advantages of FATI SAR ADCs, as the required conversion rate increases, the power consumption of the front-end flash ADC becomes significant, which reduces the efficiency. In addition, if the target speed is higher than the frequency achievable by a single flash ADC, the FATI SAR ADC should be time-interleaved with multiple flash ADCs. The timing skew calibration scheme reported in [2] cannot be applied in this case. Considering these issues, this work introduces an advanced FATI SAR ADC with a folding-flash (F-flash) ADC that reduces the power burden placed upon a flash ADC. In addition, 2× time interleaving is applied in an effort to lower the conversion rate of the flash ADC (time-interleaved FATI SAR ADC). The offset and timing skew of each channel are calibrated in the background.
最近报道的高速adc大多利用时间交错(TI)架构和低功耗SAR adc作为子通道。然而，由于TI架构需要满足通道之间的匹配要求，校准引起的电路复杂性往往成为相当大的负担。为了减少TI SAR ADC中的通道数，可以利用闪存辅助TI (FATI) SAR结构[1]来提高子通道SAR ADC的转换速度，因为前端闪存ADC提供了多位msb。此外，由于来自每个SAR ADC的编码都嵌入了相应信道的时序倾斜信息，因此该结构可以有效地提取时序倾斜信息[2]。尽管FATI SAR ADC具有这些优点，但随着所需转换率的增加，前端闪存ADC的功耗变得显著，从而降低了效率。此外，如果目标速度高于单个闪存ADC可实现的频率，则FATI SAR ADC应与多个闪存ADC时间交错。在这种情况下，[2]中报道的时序偏差校准方案不能应用。考虑到这些问题，本工作引入了一种先进的FATI SAR ADC，该ADC带有折叠闪光(F-flash) ADC，可减少闪光ADC的功率负担。此外，为了降低闪存ADC(时间交错FATI SAR ADC)的转换率，还应用了2倍时间交错。每个通道的偏移和定时倾斜在背景中校准。
{"title":"26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS","authors":"Barosaim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Hojin Park, S. Ryu","doi":"10.1109/ISSCC.2015.7063127","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063127","url":null,"abstract":"Recently reported high-speed ADCs have mostly taken advantage of time-interleaved (TI) architectures with low-power SAR ADCs for their sub-channels. However, given that the TI architecture needs to satisfy matching requirements between channels, the circuit complexity arising from the calibrations has often become a considerable burden. In order to reduce the number of channels in TI SAR ADCs, a flash-assisted TI (FATI) SAR structure [1] can be utilized to enhance the conversion speed of a sub-channel SAR ADC due to the multi-bit MSBs from a front-end flash ADC. In addition, because the codes from each SAR ADC embed the timing skew information of the corresponding channel, the structure can extract timing skew information in an efficient manner [2]. Despite these advantages of FATI SAR ADCs, as the required conversion rate increases, the power consumption of the front-end flash ADC becomes significant, which reduces the efficiency. In addition, if the target speed is higher than the frequency achievable by a single flash ADC, the FATI SAR ADC should be time-interleaved with multiple flash ADCs. The timing skew calibration scheme reported in [2] cannot be applied in this case. Considering these issues, this work introduces an advanced FATI SAR ADC with a folding-flash (F-flash) ADC that reduces the power burden placed upon a flash ADC. In addition, 2× time interleaving is applied in an effort to lower the conversion rate of the flash ADC (time-interleaved FATI SAR ADC). The offset and timing skew of each channel are calibrated in the background.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126474751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062960
Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, S. Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, H. Park, Dong-Hun Kwak, Sangwon Park, Seok-Min Yoon, Wook-Ghee Hahn, J. Ryu, Sang-Won Shim, Kyung-Tae Kang, Sungsoo Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, O. Kwon, Ji-Sang Lee, Moosung Kim, Sanghoon Joo, J. Jang, Sang-Won Hwang, D. Byeon, Hyang-Ja Yang, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].
{"title":"7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate","authors":"Jae-Woo Im, Woopyo Jeong, Doo-Hyun Kim, S. Nam, Dong-Kyo Shim, Myung-Hoon Choi, Hyun-Jun Yoon, Dae-Han Kim, Youse Kim, H. Park, Dong-Hun Kwak, Sangwon Park, Seok-Min Yoon, Wook-Ghee Hahn, J. Ryu, Sang-Won Shim, Kyung-Tae Kang, Sungsoo Choi, Jeong-Don Ihm, Young-Sun Min, In-Mo Kim, Doosub Lee, Ji-Ho Cho, O. Kwon, Ji-Sang Lee, Moosung Kim, Sanghoon Joo, J. Jang, Sang-Won Hwang, D. Byeon, Hyang-Ja Yang, Ki-Tae Park, K. Kyung, Jeong-Hyuk Choi","doi":"10.1109/ISSCC.2015.7062960","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062960","url":null,"abstract":"Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127631226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7063044
N. Delorme, C. Blanc, A. Dezzani, M. Bely, Alexandre Ferret, Simon Laminette, J. Roudier, É. Colinet
Progress in silicon technology has promoted NEMS sensors as viable and highly sensitive candidates for gravimetric applications such as gas sensing, mass spectrometry and biochemical analysis [1]. The high sensitivity to mass is related to the small dimensions and intrinsic mass of the NEMS themselves, which results in resonant frequencies in the 10MHz-to-1GHz range and drive voltages reaching 1V to 10V. Such a combination of frequencies and voltages is a challenge for the driving electronics. Although several promising approaches using NEMS/CMOS co-integration have been recently published [2], many experiments in the field are currently using discrete electronic boards and specialized lab instruments. To respond to size, power and cost demands, an IC implementing the most critical parts of the full system is described hereafter.
{"title":"16.5 A NEMS-array control IC for sub-attogram gravimetric sensing applications in 28nm CMOS technology","authors":"N. Delorme, C. Blanc, A. Dezzani, M. Bely, Alexandre Ferret, Simon Laminette, J. Roudier, É. Colinet","doi":"10.1109/ISSCC.2015.7063044","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7063044","url":null,"abstract":"Progress in silicon technology has promoted NEMS sensors as viable and highly sensitive candidates for gravimetric applications such as gas sensing, mass spectrometry and biochemical analysis [1]. The high sensitivity to mass is related to the small dimensions and intrinsic mass of the NEMS themselves, which results in resonant frequencies in the 10MHz-to-1GHz range and drive voltages reaching 1V to 10V. Such a combination of frequencies and voltages is a challenge for the driving electronics. Although several promising approaches using NEMS/CMOS co-integration have been recently published [2], many experiments in the field are currently using discrete electronic boards and specialized lab instruments. To respond to size, power and cost demands, an IC implementing the most critical parts of the full system is described hereafter.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"15 3-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121006288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062956
L. Du, Yan Zhang, F. Hsiao, A. Tang, Yan Zhao, Yilei Li, Zuow-Zun Chen, Liting Huang, Mau-Chung Frank Chang
Contactless (3D) touch sensors, when integrated with displays, offer many advantages over that of conventional touch-panel screens by offering a more hygienic and a more immersive & interactive human/machine interface for 3D user experiences [1]. While significant progress has been made in developing 3D contactless touch sensors for larger television and monitor type displays [2-3], the technology has yet to be infused into space- and battery-constrained mobile devices (i.e., tablets and smartphones). For successful insertions into these systems, a paradigm shift in touch-sensor system design is essential to enable seamless sensing operations with smaller-size, more tightly spaced, strongly coupled, and highly resistive display electrodes. In addition, any successful 3D sensing solution for mobile devices must consume low power and small silicon area to be compatible with limited battery and space resources.
{"title":"6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices","authors":"L. Du, Yan Zhang, F. Hsiao, A. Tang, Yan Zhao, Yilei Li, Zuow-Zun Chen, Liting Huang, Mau-Chung Frank Chang","doi":"10.1109/ISSCC.2015.7062956","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062956","url":null,"abstract":"Contactless (3D) touch sensors, when integrated with displays, offer many advantages over that of conventional touch-panel screens by offering a more hygienic and a more immersive & interactive human/machine interface for 3D user experiences [1]. While significant progress has been made in developing 3D contactless touch sensors for larger television and monitor type displays [2-3], the technology has yet to be infused into space- and battery-constrained mobile devices (i.e., tablets and smartphones). For successful insertions into these systems, a paradigm shift in touch-sensor system design is essential to enable seamless sensing operations with smaller-size, more tightly spaced, strongly coupled, and highly resistive display electrodes. In addition, any successful 3D sensing solution for mobile devices must consume low power and small silicon area to be compatible with limited battery and space resources.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121447651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062946
G. Maderbacher, S. Marsili, M. Motz, Thomas Jackum, J. Thielmann, Henrik Hassander, Herbert Gruber, Florian Hus, C. Sandner
Accurate voltage references are key building blocks for almost all electronic systems. Specifically, fuel gauge applications benefit from very high precision references to allow for extremely precise measurement of battery voltage and current in order to provide an accurate measurement of the state of charge of the battery.
{"title":"5.8 A digitally assisted single-point-calibration CMOS bandgap voltage reference with a 3σ inaccuracy of ±0.08% for fuel-gauge applications","authors":"G. Maderbacher, S. Marsili, M. Motz, Thomas Jackum, J. Thielmann, Henrik Hassander, Herbert Gruber, Florian Hus, C. Sandner","doi":"10.1109/ISSCC.2015.7062946","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062946","url":null,"abstract":"Accurate voltage references are key building blocks for almost all electronic systems. Specifically, fuel gauge applications benefit from very high precision references to allow for extremely precise measurement of battery voltage and current in order to provide an accurate measurement of the state of charge of the battery.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-19DOI: 10.1109/ISSCC.2015.7062988
P. Francese, T. Toifl, M. Braendli, C. Menolfi, M. Kossel, T. Morf, L. Kull, T. Andersen, Hazar Yueksel, A. Cevrero, D. Luu
The authors report the implementation of a continuous-time linear equalizer (CTLE) featuring a new technique to control the high-frequency gain peaking and to interface to current-summing stages usually implemented as interleaved slices for the linear analog superposition of the coefficients of decision-feedback equalizers (DFE). The circuits are implemented in 14nm FinFET SOI CMOS technology and are included in a prototype receiver targeted to 16Gb/s serial I/O links for multi-core microprocessors off-chip communication. The architecture is shown in the paper. Power efficiency and compactness are among the primary goals of the study together with an equalization capability sufficient to recover at bit-error rate (BER) levels below 10-12 data transmitted across smooth channels with losses in excess of 25dB at 8GHz.
作者报告了一种连续时间线性均衡器(CTLE)的实现，该均衡器采用一种新技术来控制高频增益峰值，并与通常作为交错片实现的电流求和级接口，用于决策反馈均衡器(DFE)系数的线性模拟叠加。该电路采用14nm FinFET SOI CMOS技术实现，并包含在针对多核微处理器片外通信的16Gb/s串行I/O链路的原型接收器中。本文给出了该系统的总体结构。功率效率和紧凑性是该研究的主要目标之一，同时均衡能力足以恢复在8GHz时损耗超过25dB的平滑信道上传输的误码率(BER)低于10-12的数据。
{"title":"10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver","authors":"P. Francese, T. Toifl, M. Braendli, C. Menolfi, M. Kossel, T. Morf, L. Kull, T. Andersen, Hazar Yueksel, A. Cevrero, D. Luu","doi":"10.1109/ISSCC.2015.7062988","DOIUrl":"https://doi.org/10.1109/ISSCC.2015.7062988","url":null,"abstract":"The authors report the implementation of a continuous-time linear equalizer (CTLE) featuring a new technique to control the high-frequency gain peaking and to interface to current-summing stages usually implemented as interleaved slices for the linear analog superposition of the coefficients of decision-feedback equalizers (DFE). The circuits are implemented in 14nm FinFET SOI CMOS technology and are included in a prototype receiver targeted to 16Gb/s serial I/O links for multi-core microprocessors off-chip communication. The architecture is shown in the paper. Power efficiency and compactness are among the primary goals of the study together with an equalization capability sufficient to recover at bit-error rate (BER) levels below 10-12 data transmitted across smooth channels with losses in excess of 25dB at 8GHz.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123033590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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