Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585820
J. C. Foster
We will describe a CAD system used by AT$#x0026;T Bell Laboratories, AT$#x0026;T Information Systems, and AT$#x0026;T Technologies, Inc. for the design and documentation of electronic packages. It is a highly integrated system designed around a single common data base. Both the system and data base have evolved over a number of years. The system is made up of two major functional subsystems; EDS - the Engineering Design System, a systems for design intent capture, validation and prototype for all packaging levels; IDS - the Interconnection Design System, a physical layout and documentation system for circuit packs and backplanes. In this paper we will take a high level view of the system, looking at the goals for the system and the consequent functional and architectural strategies, the history of its development, its overall architecture and some of the future directions its development might go in. Companion papers will discuss in more detail the functional components of the system plus some specifics of its use.
我们将描述AT$#x0026;T Bell实验室、AT$#x0026;T Information Systems和AT$#x0026;T Technologies, Inc.用于电子封装设计和文档编制的CAD系统。它是一个围绕单一公共数据库设计的高度集成的系统。系统和数据库都经过了多年的发展。该系统由两大功能子系统组成;EDS—工程设计系统，用于所有包装级别的设计意图捕获、验证和原型的系统;IDS -互连设计系统，电路包和背板的物理布局和文档系统。在本文中，我们将从一个高层次的角度来看待这个系统，看看系统的目标和相应的功能和架构策略，它的发展历史，它的整体架构和一些未来的发展方向。配套的论文将更详细地讨论系统的功能组件及其使用的一些细节。
{"title":"A Unified CAD System for Electronic Design","authors":"J. C. Foster","doi":"10.1109/DAC.1984.1585820","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585820","url":null,"abstract":"We will describe a CAD system used by AT$#x0026;T Bell Laboratories, AT$#x0026;T Information Systems, and AT$#x0026;T Technologies, Inc. for the design and documentation of electronic packages. It is a highly integrated system designed around a single common data base. Both the system and data base have evolved over a number of years. The system is made up of two major functional subsystems; EDS - the Engineering Design System, a systems for design intent capture, validation and prototype for all packaging levels; IDS - the Interconnection Design System, a physical layout and documentation system for circuit packs and backplanes. In this paper we will take a high level view of the system, looking at the goals for the system and the consequent functional and architectural strategies, the history of its development, its overall architecture and some of the future directions its development might go in. Companion papers will discuss in more detail the functional components of the system plus some specifics of its use.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131381134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A unique cell compiler is described which uses a combination of high level or systems level parameters to define and build complex cells such as RAMs, ROMs and PLAs. The techniques include specialized macros residing in VIP (VLSI Implementation Program), a powerful procedural design language, and predefined component cells used to construct multiple variations of the same circuit.
{"title":"Methodology for Compiler Generated Silicon Structures","authors":"Antonio Martínez, S. Nance","doi":"10.5555/800033.800883","DOIUrl":"https://doi.org/10.5555/800033.800883","url":null,"abstract":"A unique cell compiler is described which uses a combination of high level or systems level parameters to define and build complex cells such as RAMs, ROMs and PLAs. The techniques include specialized macros residing in VIP (VLSI Implementation Program), a powerful procedural design language, and predefined component cells used to construct multiple variations of the same circuit.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131808894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585765
M. Kawai, J. Hayes
A prototype version of a new switch-level fault simulator for digital MOS IC's is described. The simulation program, which is called CSASIM, analyzes CSA (connector-switch-attenuator) circuit models using multiple logic values. A novel method of signal evaluation is employed, based on the superposition of bidirectional static and dynamic signals. CSASIM also allows efficient simulation of many different fault types, including stuck-at-constant, open-circuit, short-circuit, and delay faults. The internal structure and fault-simulation mechanisms of the simulator are discussed in this paper.
{"title":"An Experimental MOS Fault Simulation Program CSASIM","authors":"M. Kawai, J. Hayes","doi":"10.1109/DAC.1984.1585765","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585765","url":null,"abstract":"A prototype version of a new switch-level fault simulator for digital MOS IC's is described. The simulation program, which is called CSASIM, analyzes CSA (connector-switch-attenuator) circuit models using multiple logic values. A novel method of signal evaluation is employed, based on the superposition of bidirectional static and dynamic signals. CSASIM also allows efficient simulation of many different fault types, including stuck-at-constant, open-circuit, short-circuit, and delay faults. The internal structure and fault-simulation mechanisms of the simulator are discussed in this paper.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585890
Ola A. Marvik
A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.
{"title":"A Method for IC Layout Verification","authors":"Ola A. Marvik","doi":"10.1109/DAC.1984.1585890","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585890","url":null,"abstract":"A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126872987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585775
G. Odawara, Jun Sato, M. Tomita
This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System). SFDL has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable for computer processing. Besides, the LDSS allows designers to draw diagrams without the attention to complicated drawing rule and translate the SFDL diagrams into a text-styled hardware description language. Through experiments, the effectiveness of the SFDL for hierarchical logic design has been confirmed.
{"title":"A Symbolic Functional Description Language","authors":"G. Odawara, Jun Sato, M. Tomita","doi":"10.1109/DAC.1984.1585775","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585775","url":null,"abstract":"This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System). SFDL has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable for computer processing. Besides, the LDSS allows designers to draw diagrams without the attention to complicated drawing rule and translate the SFDL diagrams into a text-styled hardware description language. Through experiments, the effectiveness of the SFDL for hierarchical logic design has been confirmed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115490538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585770
T. Yoshimura
In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a spcified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical "left edge algorithm". The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorithm was implemented for examples in previously published papers. Experimental results show that the new algorithm produces optimum solutions in most cases.
{"title":"An Efficient Channel Router","authors":"T. Yoshimura","doi":"10.1109/DAC.1984.1585770","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585770","url":null,"abstract":"In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a spcified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical \"left edge algorithm\". The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorithm was implemented for examples in previously published papers. Experimental results show that the new algorithm produces optimum solutions in most cases.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585795
S. DasGupta, M. Graf, R. A. Rasmussen, R. Walther, T. Williams
This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.
{"title":"Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI","authors":"S. DasGupta, M. Graf, R. A. Rasmussen, R. Walther, T. Williams","doi":"10.1109/DAC.1984.1585795","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585795","url":null,"abstract":"This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128879432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585783
M. Hardwick
In recent years many researchers have tried to apply the traditional database systems to design applications. To date, most of these experiments have been largely unsuccessful. Insufficient computing power may be one reason for this failure. However, the problem may be more fundamental. We believe the data models of the traditional database systems are intrinsically unsuited for design applications. In this paper we give reasons for this opinion and describe an enhanced relational model which removes some of the weaknesses we have identified.
{"title":"Extending the Relational Database Data Model for Design Applications","authors":"M. Hardwick","doi":"10.1109/DAC.1984.1585783","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585783","url":null,"abstract":"In recent years many researchers have tried to apply the traditional database systems to design applications. To date, most of these experiments have been largely unsuccessful. Insufficient computing power may be one reason for this failure. However, the problem may be more fundamental. We believe the data models of the traditional database systems are intrinsically unsuited for design applications. In this paper we give reasons for this opinion and describe an enhanced relational model which removes some of the weaknesses we have identified.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585777
D. Gajski
The present VLSI design crisis was caused by advancements in VLSI technology which allow us to pack almost a million transistors on a single chip. The functional complexity of a chip has increased accordingly. First, this forced a chip designer, usually an experienced circuit designer, to become an expert in logic design, computer architecture, and application software. This requirement for accumulated expertise in one person and increased demand for new designs created a shortage of chip designers. Secondly, the design complexity prolonged the design cycle, which became almost as long as the lifetime of the product. To solve this design Crisis, an advancement in design methodology for VLSI technology is needed. Basically, there are three approaches. knowledse base of an expert system. The knowledge in the knowledge base can be divided basically into three categories: Concepts include basic terms of the problem domain (VLSI design in our case), which can be usually obtained from textbooks. Rules describe particular situations and desirable actions to be performed (design refinements in our case). This knowledge is based on experience, and is obtained from an expert. Strate$ies are procedures that aid in guiding the search through the knowledge base and help resolve conflicts when several equally plausible rules apply. The other two components of an expert system are a workin$ memory that stores current design description, and an inference en$ine that searches the knowledge base for applicable knowledge and makes design refinements on the basis of current design description.
{"title":"Silicon Compilers and Expert Systems for VLSI","authors":"D. Gajski","doi":"10.1109/DAC.1984.1585777","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585777","url":null,"abstract":"The present VLSI design crisis was caused by advancements in VLSI technology which allow us to pack almost a million transistors on a single chip. The functional complexity of a chip has increased accordingly. First, this forced a chip designer, usually an experienced circuit designer, to become an expert in logic design, computer architecture, and application software. This requirement for accumulated expertise in one person and increased demand for new designs created a shortage of chip designers. Secondly, the design complexity prolonged the design cycle, which became almost as long as the lifetime of the product. To solve this design Crisis, an advancement in design methodology for VLSI technology is needed. Basically, there are three approaches. knowledse base of an expert system. The knowledge in the knowledge base can be divided basically into three categories: Concepts include basic terms of the problem domain (VLSI design in our case), which can be usually obtained from textbooks. Rules describe particular situations and desirable actions to be performed (design refinements in our case). This knowledge is based on experience, and is obtained from an expert. Strate$ies are procedures that aid in guiding the search through the knowledge base and help resolve conflicts when several equally plausible rules apply. The other two components of an expert system are a workin$ memory that stores current design description, and an inference en$ine that searches the knowledge base for applicable knowledge and makes design refinements on the basis of current design description.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121695924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585816
M. Glazier, A. Ambler
The growing need for high-speed digital logic simulation is well-known and several special-purpose hardware architectures to provide this have, to date, been presented. This paper attempts to address the problems of high-speed simulation in a more systematic and detailed manner to achieve an enhanced performance from a simpler architecture. The proposed architecture is capable of providing all the facilities currently available in software logic simulators.
{"title":"ULTIMATE: A Hardware Logic Simulation Engine","authors":"M. Glazier, A. Ambler","doi":"10.1109/DAC.1984.1585816","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585816","url":null,"abstract":"The growing need for high-speed digital logic simulation is well-known and several special-purpose hardware architectures to provide this have, to date, been presented. This paper attempts to address the problems of high-speed simulation in a more systematic and detailed manner to achieve an enhanced performance from a simpler architecture. The proposed architecture is capable of providing all the facilities currently available in software logic simulators.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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