Pub Date : 2024-07-25DOI: 10.1038/s41928-024-01213-0
Yuanbo Guo, Zheyu Yan, Xiaoting Yu, Qingpeng Kong, Joy Xie, Kevin Luo, Dewen Zeng, Yawen Wu, Zhenge Jia, Yiyu Shi
Ensuring the fairness of neural networks is crucial when applying deep learning techniques to critical applications such as medical diagnosis and vital signal monitoring. However, maintaining fairness becomes increasingly challenging when deploying these models on platforms with limited hardware resources, as existing fairness-aware neural network designs typically overlook the impact of resource constraints. Here we analyse the impact of the underlying hardware on the task of pursuing fairness. We use neural network accelerators with compute-in-memory architecture as examples. We first investigate the relationship between hardware platform and fairness-aware neural network design. We then discuss how hardware advancements in emerging computing-in-memory devices—in terms of on-chip memory capacity and device variability management—affect neural network fairness. We also identify challenges in designing fairness-aware neural networks on such resource-constrained hardware and consider potential approaches to overcome them. An analysis of the relationship between hardware platforms and fairness-aware neural network design shows how hardware advancements can affect the fairness of neural networks and highlights the need for future designs to consider this factor.
{"title":"Hardware design and the fairness of a neural network","authors":"Yuanbo Guo, Zheyu Yan, Xiaoting Yu, Qingpeng Kong, Joy Xie, Kevin Luo, Dewen Zeng, Yawen Wu, Zhenge Jia, Yiyu Shi","doi":"10.1038/s41928-024-01213-0","DOIUrl":"10.1038/s41928-024-01213-0","url":null,"abstract":"Ensuring the fairness of neural networks is crucial when applying deep learning techniques to critical applications such as medical diagnosis and vital signal monitoring. However, maintaining fairness becomes increasingly challenging when deploying these models on platforms with limited hardware resources, as existing fairness-aware neural network designs typically overlook the impact of resource constraints. Here we analyse the impact of the underlying hardware on the task of pursuing fairness. We use neural network accelerators with compute-in-memory architecture as examples. We first investigate the relationship between hardware platform and fairness-aware neural network design. We then discuss how hardware advancements in emerging computing-in-memory devices—in terms of on-chip memory capacity and device variability management—affect neural network fairness. We also identify challenges in designing fairness-aware neural networks on such resource-constrained hardware and consider potential approaches to overcome them. An analysis of the relationship between hardware platforms and fairness-aware neural network design shows how hardware advancements can affect the fairness of neural networks and highlights the need for future designs to consider this factor.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":null,"pages":null},"PeriodicalIF":33.7,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141764235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-25DOI: 10.1038/s41928-024-01207-y
Shaohua Ling, Xi Tian, Qihang Zeng, Zhihang Qin, Selman A. Kurt, Yu Jun Tan, Jerry Y. H. Fuh, Zhuangjian Liu, Michael D. Dickey, John S. Ho, Benjamin C. K. Tee
The direct writing of complex three-dimensional (3D) metallic structures is of use in the development of advanced electronics. However, conventional direct ink writing primarily uses composite inks that have low electrical conductivity and require support materials to create 3D architectures. Here we show that Field’s metal—a eutectic alloy with a relatively low melting point—can be 3D printed using a process in which tension between the molten metal in a nozzle and the leading edge of the printed part allows 3D structures to be directly written. The use of tension avoids using external pressure for extrusion (which can cause beading of the printed structure), allowing uniform and smooth microwire structures to be printed on various substrates with speeds of up to 100 mm s−1. We use the approach to print various free-standing 3D structures—including vertical letters, a cubic framework and scalable helixes—without post-treatment, and the resulting Field’s metal structures can offer electrical conductivity of 2 × 104 S cm−1, self-healing capability and recyclability. We also use the technique to print a 3D circuit for wearable battery-free temperature sensing, hemispherical helical antennas for wireless vital sign monitoring and 3D metamaterials for electromagnetic-wave manipulation. Free-standing metallic structures with high conductivities and aspect ratios can be 3D printed from Field’s metal using a direct ink writing method that avoids using external pressure to drive ink through the nozzle.
直接书写复杂的三维（3D）金属结构在先进电子产品的开发中非常有用。然而，传统的直接写入油墨主要使用导电性较低的复合油墨，并且需要辅助材料来创建三维结构。在这里，我们展示了菲尔德的金属--一种熔点相对较低的共晶合金--可以通过喷嘴中的熔融金属与打印部件前缘之间的张力进行三维打印，从而直接写入三维结构。张力的使用避免了使用外部压力进行挤压（这可能会导致打印结构出现串珠），从而可以在各种基底上以高达 100 mm s-1 的速度打印出均匀光滑的微线结构。我们利用这种方法打印出各种独立的三维结构，包括垂直字母、立方体框架和可扩展的螺旋线，而无需进行后处理，所打印出的 Field 金属结构可提供 2 × 104 S cm-1 的导电性、自愈能力和可回收性。我们还利用这项技术打印了用于可穿戴无电池温度传感的三维电路、用于无线生命体征监测的半球形螺旋天线以及用于电磁波操纵的三维超材料。
{"title":"Tension-driven three-dimensional printing of free-standing Field’s metal structures","authors":"Shaohua Ling, Xi Tian, Qihang Zeng, Zhihang Qin, Selman A. Kurt, Yu Jun Tan, Jerry Y. H. Fuh, Zhuangjian Liu, Michael D. Dickey, John S. Ho, Benjamin C. K. Tee","doi":"10.1038/s41928-024-01207-y","DOIUrl":"10.1038/s41928-024-01207-y","url":null,"abstract":"The direct writing of complex three-dimensional (3D) metallic structures is of use in the development of advanced electronics. However, conventional direct ink writing primarily uses composite inks that have low electrical conductivity and require support materials to create 3D architectures. Here we show that Field’s metal—a eutectic alloy with a relatively low melting point—can be 3D printed using a process in which tension between the molten metal in a nozzle and the leading edge of the printed part allows 3D structures to be directly written. The use of tension avoids using external pressure for extrusion (which can cause beading of the printed structure), allowing uniform and smooth microwire structures to be printed on various substrates with speeds of up to 100 mm s−1. We use the approach to print various free-standing 3D structures—including vertical letters, a cubic framework and scalable helixes—without post-treatment, and the resulting Field’s metal structures can offer electrical conductivity of 2 × 104 S cm−1, self-healing capability and recyclability. We also use the technique to print a 3D circuit for wearable battery-free temperature sensing, hemispherical helical antennas for wireless vital sign monitoring and 3D metamaterials for electromagnetic-wave manipulation. Free-standing metallic structures with high conductivities and aspect ratios can be 3D printed from Field’s metal using a direct ink writing method that avoids using external pressure to drive ink through the nozzle.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":null,"pages":null},"PeriodicalIF":33.7,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141764236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-24DOI: 10.1038/s41928-024-01212-1
Raghav Sharma, Tung Ngo, Eleonora Raimondo, Anna Giordano, Junta Igarashi, Butsurin Jinnai, Shishun Zhao, Jiayu Lei, Yong-Xin Guo, Giovanni Finocchio, Shunsuke Fukami, Hideo Ohno, Hyunsoo Yang
Radiofrequency harvesting using ambient wireless energy could be used to reduce the carbon footprint of electronic devices. However, ambient radiofrequency energy is weak (less than −20 dBm), and the performance of state-of-the-art radiofrequency rectifiers is restricted by thermodynamic limits and high-frequency parasitic impedance. Nanoscale spin rectifiers based on magnetic tunnel junctions have recently demonstrated high sensitivity, but suffer from a low a.c.-to-d.c. conversion efficiency (less than 1%). Here we report a sensitive spin rectifier rectenna that can harvest ambient radiofrequency signals between −62 and −20 dBm. We also develop an on-chip co-planar-waveguide-based spin rectifier array with a large zero-bias sensitivity (around 34,500 mV mW−1) and high efficiency (7.81%). The performance of our spin rectifier array relies on self-parametric excitation, driven by voltage-controlled magnetic anisotropy. We show that these spin rectifiers can be used to wirelessly power a sensor at a radiofrequency power of −27 dBm. Sensitive spin rectifier devices can be used to create rectennas that harvest ambient radiofrequency signals between –62 and –20 dBm, and can be used to create on-chip co-planar-waveguide-based spin rectifier arrays with large zero-bias sensitivity and high efficiency.
{"title":"Nanoscale spin rectifiers for harvesting ambient radiofrequency energy","authors":"Raghav Sharma, Tung Ngo, Eleonora Raimondo, Anna Giordano, Junta Igarashi, Butsurin Jinnai, Shishun Zhao, Jiayu Lei, Yong-Xin Guo, Giovanni Finocchio, Shunsuke Fukami, Hideo Ohno, Hyunsoo Yang","doi":"10.1038/s41928-024-01212-1","DOIUrl":"10.1038/s41928-024-01212-1","url":null,"abstract":"Radiofrequency harvesting using ambient wireless energy could be used to reduce the carbon footprint of electronic devices. However, ambient radiofrequency energy is weak (less than −20 dBm), and the performance of state-of-the-art radiofrequency rectifiers is restricted by thermodynamic limits and high-frequency parasitic impedance. Nanoscale spin rectifiers based on magnetic tunnel junctions have recently demonstrated high sensitivity, but suffer from a low a.c.-to-d.c. conversion efficiency (less than 1%). Here we report a sensitive spin rectifier rectenna that can harvest ambient radiofrequency signals between −62 and −20 dBm. We also develop an on-chip co-planar-waveguide-based spin rectifier array with a large zero-bias sensitivity (around 34,500 mV mW−1) and high efficiency (7.81%). The performance of our spin rectifier array relies on self-parametric excitation, driven by voltage-controlled magnetic anisotropy. We show that these spin rectifiers can be used to wirelessly power a sensor at a radiofrequency power of −27 dBm. Sensitive spin rectifier devices can be used to create rectennas that harvest ambient radiofrequency signals between –62 and –20 dBm, and can be used to create on-chip co-planar-waveguide-based spin rectifier arrays with large zero-bias sensitivity and high efficiency.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":null,"pages":null},"PeriodicalIF":33.7,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141764080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The growth of data-intensive computing tasks requires processing units with higher performance and energy efficiency, but these requirements are increasingly difficult to achieve with conventional semiconductor technology. One potential solution is to combine developments in devices with innovations in system architecture. Here we report a tensor processing unit (TPU) that is based on 3,000 carbon nanotube field-effect transistors and can perform energy-efficient convolution operations and matrix multiplication. The TPU is constructed with a systolic array architecture that allows parallel 2 bit integer multiply–accumulate operations. A five-layer convolutional neural network based on the TPU can perform MNIST image recognition with an accuracy of up to 88% for a power consumption of 295 µW. We use an optimized nanotube fabrication process that offers a semiconductor purity of 99.9999% and ultraclean surfaces, leading to transistors with high on-current densities and uniformity. Using system-level simulations, we estimate that an 8 bit TPU made with nanotube transistors at a 180 nm technology node could reach a main frequency of 850 MHz and an energy efficiency of 1 tera-operations per second per watt. Carbon nanotube networks made with high purity and ultraclean interfaces can be used to make a tensor processing unit that contains 3,000 transistors in a systolic array architecture to improve energy efficiency in accelerating neural network tasks.
{"title":"A carbon-nanotube-based tensor processing unit","authors":"Jia Si, Panpan Zhang, Chenyi Zhao, Dongyi Lin, Lin Xu, Haitao Xu, Lijun Liu, Jianhua Jiang, Lian-Mao Peng, Zhiyong Zhang","doi":"10.1038/s41928-024-01211-2","DOIUrl":"10.1038/s41928-024-01211-2","url":null,"abstract":"The growth of data-intensive computing tasks requires processing units with higher performance and energy efficiency, but these requirements are increasingly difficult to achieve with conventional semiconductor technology. One potential solution is to combine developments in devices with innovations in system architecture. Here we report a tensor processing unit (TPU) that is based on 3,000 carbon nanotube field-effect transistors and can perform energy-efficient convolution operations and matrix multiplication. The TPU is constructed with a systolic array architecture that allows parallel 2 bit integer multiply–accumulate operations. A five-layer convolutional neural network based on the TPU can perform MNIST image recognition with an accuracy of up to 88% for a power consumption of 295 µW. We use an optimized nanotube fabrication process that offers a semiconductor purity of 99.9999% and ultraclean surfaces, leading to transistors with high on-current densities and uniformity. Using system-level simulations, we estimate that an 8 bit TPU made with nanotube transistors at a 180 nm technology node could reach a main frequency of 850 MHz and an energy efficiency of 1 tera-operations per second per watt. Carbon nanotube networks made with high purity and ultraclean interfaces can be used to make a tensor processing unit that contains 3,000 transistors in a systolic array architecture to improve energy efficiency in accelerating neural network tasks.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":null,"pages":null},"PeriodicalIF":33.7,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-22DOI: 10.1038/s41928-024-01221-0
Matthew Parker
{"title":"Oxide dielectrics that grow on 2D materials","authors":"Matthew Parker","doi":"10.1038/s41928-024-01221-0","DOIUrl":"10.1038/s41928-024-01221-0","url":null,"abstract":"","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":null,"pages":null},"PeriodicalIF":33.7,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141737034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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