Pub Date : 2026-01-20DOI: 10.1038/s41928-025-01553-5
Kuakua Lu, Yun Li, Qijing Wang, Linlu Wu, Xinglong Ren, Xu Chen, Luhao Liu, Yating Li, Xiaoming Xu, Qingkai Zhang, Di Wang, Liqi Zhou, Mingfei Xiao, Sai Jiang, Mengjiao Pei, Haoxin Gong, William Wood, Ian E. Jacobs, Junzhan Wang, Gang Chen, Peng Wang, Zhaosheng Li, Chunfeng Zhang, Xinran Wang, Xu Wu, Yeliang Wang, Wei Ji, Songlin Li, Jingsi Qiao, Yi Shi, Henning Sirringhaus
Metallic charge transport of field-induced carriers can be observed in single-crystal silicon over a wide temperature range. Such behaviour is rare in undoped organic semiconductors but is beneficial for engineering devices with advanced performance. Here we report metallic charge transport in conjugated molecular bilayers down to 8 K with an electrical conductivity of up to 245 S cm−1 and a Hall mobility larger than 100 cm2 V−1 s−1 at 20 K. We use molecular-crystal bilayers of the organic semiconductor 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene. We infer that this transport behaviour originates from the phenyl bridge coupling between the two molecular layers, which suppresses molecular vibrations and weakens Coulomb interactions. We develop a controlled method for introducing defects, using which we observe a disorder-driven metal–insulator transition in the molecular crystal.
在单晶硅中可以在很宽的温度范围内观察到场致载流子的金属电荷输运。这种行为在未掺杂的有机半导体中是罕见的，但对于具有先进性能的工程器件是有益的。在这里，我们报道了金属电荷在共轭分子双层中传输到8k，电导率高达245 S cm−1,20 K时霍尔迁移率大于100 cm2 V−1 S−1。我们使用了有机半导体2-癸基-7-苯基-[1]苯并噻吩[3,2-b][1]苯并噻吩的分子晶体双层。我们推断这种传输行为源于两个分子层之间的苯基桥耦合，它抑制了分子振动并减弱了库仑相互作用。我们开发了一种引入缺陷的控制方法，使用该方法我们观察了分子晶体中无序驱动的金属-绝缘体转变。
{"title":"Metallic charge transport in conjugated molecular bilayers","authors":"Kuakua Lu, Yun Li, Qijing Wang, Linlu Wu, Xinglong Ren, Xu Chen, Luhao Liu, Yating Li, Xiaoming Xu, Qingkai Zhang, Di Wang, Liqi Zhou, Mingfei Xiao, Sai Jiang, Mengjiao Pei, Haoxin Gong, William Wood, Ian E. Jacobs, Junzhan Wang, Gang Chen, Peng Wang, Zhaosheng Li, Chunfeng Zhang, Xinran Wang, Xu Wu, Yeliang Wang, Wei Ji, Songlin Li, Jingsi Qiao, Yi Shi, Henning Sirringhaus","doi":"10.1038/s41928-025-01553-5","DOIUrl":"https://doi.org/10.1038/s41928-025-01553-5","url":null,"abstract":"Metallic charge transport of field-induced carriers can be observed in single-crystal silicon over a wide temperature range. Such behaviour is rare in undoped organic semiconductors but is beneficial for engineering devices with advanced performance. Here we report metallic charge transport in conjugated molecular bilayers down to 8 K with an electrical conductivity of up to 245 S cm−1 and a Hall mobility larger than 100 cm2 V−1 s−1 at 20 K. We use molecular-crystal bilayers of the organic semiconductor 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene. We infer that this transport behaviour originates from the phenyl bridge coupling between the two molecular layers, which suppresses molecular vibrations and weakens Coulomb interactions. We develop a controlled method for introducing defects, using which we observe a disorder-driven metal–insulator transition in the molecular crystal.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"6 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146006035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-20DOI: 10.1038/s41928-025-01546-4
Juhyuk Park, Woojin Baek, Hyunsu Kim, Dongsoon Jung, Hokwon Kim, Baul Kim, Yong-Hoon Cho, Jaebong Lee, SungWook Lim, Shin Hyung Lee, Seungyeop Ahn, Seong Kwang Kim, Jaeyong Jeong, Joon Pyo Kim, Jinha Lim, Joonsup Shim, Dae-Myeong Geum, Sanghyeon Kim
Monolithic three-dimensional integration technology can eliminate the need for mechanical alignment between driving circuits and light-emitting diode (LED) pixels, leading to ultrahigh-resolution displays. However, this is challenging for red micro-LEDs, which are typically based on AlGaInP/GaInP, because of their low quantum efficiency and performance degradation when the pixel size is reduced. Here we report a high-pixel-density (1,700 pixels per inch) red active-matrix display consisting of micro-LEDs based on an epitaxial AlInP/GaInP double-quantum-well structure and silicon complementary metal–oxide–semiconductor integrated circuits. The epitaxial layer exhibits high internal quantum efficiency at low current densities (less than 10 A cm−2) due to a hole-dominant quantum well that reduces the non-radiative Shockley–Read–Hall recombination caused by electron lateral diffusion. We also use thickness fluctuation scattering in the quantum well to minimize the size-dependent quantum efficiency shift to higher current densities when reducing the size of the red micro-LEDs.
单片三维集成技术可以消除驱动电路和发光二极管（LED）像素之间的机械校准需求，从而实现超高分辨率显示。然而，这对于通常基于AlGaInP/GaInP的红色微型led来说是具有挑战性的，因为它们的量子效率低，并且当像素尺寸减小时性能会下降。本文报道了一种高像素密度（1700像素/英寸）的红色有源矩阵显示器，该显示器由基于外延AlInP/GaInP双量子阱结构和硅互补金属氧化物半导体集成电路的微型led组成。外延层在低电流密度（小于10 A cm−2）下表现出高的内部量子效率，这是由于空穴主导量子阱减少了由电子横向扩散引起的非辐射肖克利-里德-霍尔复合。当减小红色微型led的尺寸时，我们还使用量子阱中的厚度波动散射来最小化与尺寸相关的量子效率向更高电流密度的转移。
{"title":"A monolithic three-dimensional integrated red micro-LED display on silicon using AlInP/GaInP epilayers","authors":"Juhyuk Park, Woojin Baek, Hyunsu Kim, Dongsoon Jung, Hokwon Kim, Baul Kim, Yong-Hoon Cho, Jaebong Lee, SungWook Lim, Shin Hyung Lee, Seungyeop Ahn, Seong Kwang Kim, Jaeyong Jeong, Joon Pyo Kim, Jinha Lim, Joonsup Shim, Dae-Myeong Geum, Sanghyeon Kim","doi":"10.1038/s41928-025-01546-4","DOIUrl":"https://doi.org/10.1038/s41928-025-01546-4","url":null,"abstract":"Monolithic three-dimensional integration technology can eliminate the need for mechanical alignment between driving circuits and light-emitting diode (LED) pixels, leading to ultrahigh-resolution displays. However, this is challenging for red micro-LEDs, which are typically based on AlGaInP/GaInP, because of their low quantum efficiency and performance degradation when the pixel size is reduced. Here we report a high-pixel-density (1,700 pixels per inch) red active-matrix display consisting of micro-LEDs based on an epitaxial AlInP/GaInP double-quantum-well structure and silicon complementary metal–oxide–semiconductor integrated circuits. The epitaxial layer exhibits high internal quantum efficiency at low current densities (less than 10 A cm−2) due to a hole-dominant quantum well that reduces the non-radiative Shockley–Read–Hall recombination caused by electron lateral diffusion. We also use thickness fluctuation scattering in the quantum well to minimize the size-dependent quantum efficiency shift to higher current densities when reducing the size of the red micro-LEDs.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"393 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146006036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-19DOI: 10.1038/s41928-025-01555-3
Vignesh Ravichandran, Yi Huang, Bryce Flannery, Tergel Molom-Ochir, Tina Maurer, Shiva Asapu, Ali Abdel-Maksoud, Nia Heermance, Remy Yoo, Joshua Tackie, Wuyu Zhao, Yunzhi Ling, Alex Guo, J. Joshua Yang, Qiangfei Xia
Cellular neural networks, inspired in part by the biological retina, offer a potential route to massively parallel analogue computing. However, the hardware implementation of such systems remains challenging. Here we report memristor-based cellular neural networks for image and video processing applications. We develop a Python-based digital twin for network simulations and as a graphical user interface for controlling the fabricated hardware. Simulations using the digital twin illustrate the network’s capabilities in image processing and in solving partial differential equations. We build hardware through the tape-out of a transistor-based network and the fabrication of a circuit board with multilevel non-volatile memristors as the synapses. We show that the hardware can be used to run image processing tasks including edge and horizontal line detection.
{"title":"Memristive cellular neural networks for fast in-pixel computing","authors":"Vignesh Ravichandran, Yi Huang, Bryce Flannery, Tergel Molom-Ochir, Tina Maurer, Shiva Asapu, Ali Abdel-Maksoud, Nia Heermance, Remy Yoo, Joshua Tackie, Wuyu Zhao, Yunzhi Ling, Alex Guo, J. Joshua Yang, Qiangfei Xia","doi":"10.1038/s41928-025-01555-3","DOIUrl":"https://doi.org/10.1038/s41928-025-01555-3","url":null,"abstract":"Cellular neural networks, inspired in part by the biological retina, offer a potential route to massively parallel analogue computing. However, the hardware implementation of such systems remains challenging. Here we report memristor-based cellular neural networks for image and video processing applications. We develop a Python-based digital twin for network simulations and as a graphical user interface for controlling the fabricated hardware. Simulations using the digital twin illustrate the network’s capabilities in image processing and in solving partial differential equations. We build hardware through the tape-out of a transistor-based network and the fabrication of a circuit board with multilevel non-volatile memristors as the synapses. We show that the hardware can be used to run image processing tasks including edge and horizontal line detection.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"263 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146006037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-16DOI: 10.1038/s41928-025-01542-8
Dong-Yan Chen, Lei Dong, Qing-An Huang
Parity–time-symmetric systems with loss and gain can be described by non-Hermitian Hamiltonians. In such systems, the inclusion of a nonlinear saturable gain can eliminate the imaginary part of frequency eigenvalues and suppress noise. Consequently, a system biased at an exceptional point can be used to create enhanced sensors. However, exceptional-point frequency sensing typically has a relatively small scaling factor and a limited dynamic range. Here we report a nonlinear parity–time-symmetric system that detects the phase difference between the loss and gain resonators. We show both theoretically and experimentally that the phase difference has a cube-root singularity with a large scaling factor over a wide dynamic range. We create a wearable capacitive temperature sensor based on exceptional-point phase sensing and show that it can measure temperatures from 36 °C to 55.5 °C, which corresponds to a perturbation from 0% to 3.95%, with a maximum normalized sensitivity of 400, an estimated dynamic range of 53.52 dB and an estimated signal-to-noise ratio of 63.8 dB. Compared with an exceptional-point frequency sensing sensor, the sensitivity of our sensor is enhanced by an order of magnitude.
{"title":"A nonlinear parity–time-symmetric system for robust phase sensing","authors":"Dong-Yan Chen, Lei Dong, Qing-An Huang","doi":"10.1038/s41928-025-01542-8","DOIUrl":"https://doi.org/10.1038/s41928-025-01542-8","url":null,"abstract":"Parity–time-symmetric systems with loss and gain can be described by non-Hermitian Hamiltonians. In such systems, the inclusion of a nonlinear saturable gain can eliminate the imaginary part of frequency eigenvalues and suppress noise. Consequently, a system biased at an exceptional point can be used to create enhanced sensors. However, exceptional-point frequency sensing typically has a relatively small scaling factor and a limited dynamic range. Here we report a nonlinear parity–time-symmetric system that detects the phase difference between the loss and gain resonators. We show both theoretically and experimentally that the phase difference has a cube-root singularity with a large scaling factor over a wide dynamic range. We create a wearable capacitive temperature sensor based on exceptional-point phase sensing and show that it can measure temperatures from 36 °C to 55.5 °C, which corresponds to a perturbation from 0% to 3.95%, with a maximum normalized sensitivity of 400, an estimated dynamic range of 53.52 dB and an estimated signal-to-noise ratio of 63.8 dB. Compared with an exceptional-point frequency sensing sensor, the sensitivity of our sensor is enhanced by an order of magnitude.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"5 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145993484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-15DOI: 10.1038/s41928-025-01544-6
Pek Jun Tiw, Rui Yuan, Teng Zhang, Lianfeng Yu, Yuchao Yang
Neuromorphic systems are crucial for the development of intelligent human–machine interfaces. Memristive hardware can emulate the neuron dynamics of biological systems, but typically uses rate coding, whereas single-spike coding (in which information is expressed by the firing time of a sole spike per neuron and the relative firing times between neurons) is faster and more energy efficient. Here we report a robust memristive hardware system that uses single-spike coding. For input encoding and neural processing, we use uniform vanadium oxide memristors to create a single-spiking circuit with under 1% coding variability. For synaptic computations, we develop a conductance consolidation strategy and mapping scheme to limit conductance drift due to relaxation in a hafnium oxide/tantalum oxide memristor chip, achieving relaxed conductance states with standard deviations within 1.2 μS. We also develop an incremental step and width pulse programming strategy to prevent resource wastage. The combined end-to-end hardware single-spike-coded system exhibits an accuracy degradation under 1.5% relative to a software baseline. We show that this approach can be used for real-time vehicle control from surface electromyography. Simulations show that our system consumes around 38 times lower energy with around 6.4 times lower latency than a conventional rate coding system.
{"title":"An end-to-end memristive hardware system based on single-spike coding for human–machine interfaces","authors":"Pek Jun Tiw, Rui Yuan, Teng Zhang, Lianfeng Yu, Yuchao Yang","doi":"10.1038/s41928-025-01544-6","DOIUrl":"https://doi.org/10.1038/s41928-025-01544-6","url":null,"abstract":"Neuromorphic systems are crucial for the development of intelligent human–machine interfaces. Memristive hardware can emulate the neuron dynamics of biological systems, but typically uses rate coding, whereas single-spike coding (in which information is expressed by the firing time of a sole spike per neuron and the relative firing times between neurons) is faster and more energy efficient. Here we report a robust memristive hardware system that uses single-spike coding. For input encoding and neural processing, we use uniform vanadium oxide memristors to create a single-spiking circuit with under 1% coding variability. For synaptic computations, we develop a conductance consolidation strategy and mapping scheme to limit conductance drift due to relaxation in a hafnium oxide/tantalum oxide memristor chip, achieving relaxed conductance states with standard deviations within 1.2 μS. We also develop an incremental step and width pulse programming strategy to prevent resource wastage. The combined end-to-end hardware single-spike-coded system exhibits an accuracy degradation under 1.5% relative to a software baseline. We show that this approach can be used for real-time vehicle control from surface electromyography. Simulations show that our system consumes around 38 times lower energy with around 6.4 times lower latency than a conventional rate coding system.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"45 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145968803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-15DOI: 10.1038/s41928-025-01554-4
Bingjie Dang, Teng Zhang, Fanqi Meng, Keqin Liu, Liutao Yu, Qinghua Zhang, Si Wu, Lin Gu, Ru Huang, Yuchao Yang
Neuromorphic systems based on spike-timing-dependent plasticity offer energy-efficient learning but face limitations in terms of adapting to high-frequency inputs, restricting their effectiveness in processing complex temporal information. Synaptic fatigue dynamics, analogous to biological short-term plasticity, can increase the effectiveness, but this feature is difficult to efficiently incorporate in hardware. Here we report a hybrid architecture in which arrays of memristors with distinct dynamics are paired to create synaptic elements with short-term fatigue and long-term memory. The elements consist of an interfacial dynamic memristor with high uniformity and intrinsic fatigue behaviour coupled to a hafnia-based one-transistor–one-non-volatile memristor. The design enables a hardware-efficient implementation of fatigue spike-timing-dependent plasticity, enhancing the temporal learning capabilities of spiking neural networks. We show that the resulting neural network can be used for unsupervised online learning with high adaptability to both rate- and timing-coded spikes, high noise resilience and superior performance over conventional spike-timing-dependent plasticity approaches.
{"title":"Spiking neural networks with fatigue spike-timing-dependent plasticity learning using hybrid memristor arrays","authors":"Bingjie Dang, Teng Zhang, Fanqi Meng, Keqin Liu, Liutao Yu, Qinghua Zhang, Si Wu, Lin Gu, Ru Huang, Yuchao Yang","doi":"10.1038/s41928-025-01554-4","DOIUrl":"https://doi.org/10.1038/s41928-025-01554-4","url":null,"abstract":"Neuromorphic systems based on spike-timing-dependent plasticity offer energy-efficient learning but face limitations in terms of adapting to high-frequency inputs, restricting their effectiveness in processing complex temporal information. Synaptic fatigue dynamics, analogous to biological short-term plasticity, can increase the effectiveness, but this feature is difficult to efficiently incorporate in hardware. Here we report a hybrid architecture in which arrays of memristors with distinct dynamics are paired to create synaptic elements with short-term fatigue and long-term memory. The elements consist of an interfacial dynamic memristor with high uniformity and intrinsic fatigue behaviour coupled to a hafnia-based one-transistor–one-non-volatile memristor. The design enables a hardware-efficient implementation of fatigue spike-timing-dependent plasticity, enhancing the temporal learning capabilities of spiking neural networks. We show that the resulting neural network can be used for unsupervised online learning with high adaptability to both rate- and timing-coded spikes, high noise resilience and superior performance over conventional spike-timing-dependent plasticity approaches.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"65 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145968802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Creating multiple polarization states in a single ferroelectric device is of use in neuromorphic computing to enhance computational resolution. However, the number of stable polarization states in such systems is typically limited to 32 at room temperature. Here we report the manipulation of thousands of non-volatile polarization states at room temperature in a sliding ferroelectric transistor that is composed of an aligned graphene monolayer atop hexagonal boron nitride. Solely regulated by source–drain pulses, more than 36 quasi-continuous polarization states can be generated at one doping level. Superimposing a gate voltage during the source–drain pulses can reversibly regulate the graphene Fermi energy between 84 doping levels, promoting the number of physically distinct polarization states to 3,024 (36 states × 84 doping levels). These polarization states can sustain for over 105 s and could potentially persist for 10 years. The abundant polarization states probably stem from the motion of polar domain walls and the moiré potential localizing the injected carriers. The simulation of during-training quantization in a deep residual network using the 3,024 polarization states shows a floating-point-comparable recognition accuracy (around 93.53%) for fashion images.
{"title":"Manipulating thousands of non-volatile polarization states within one sliding ferroelectric transistor at room temperature","authors":"Xiaofan Wang, Xiaokai Chen, Yuyang Long, Jinguo Liu, Fanrong Lin, Jun Yin, Yanpeng Liu, Wanlin Guo","doi":"10.1038/s41928-025-01551-7","DOIUrl":"https://doi.org/10.1038/s41928-025-01551-7","url":null,"abstract":"Creating multiple polarization states in a single ferroelectric device is of use in neuromorphic computing to enhance computational resolution. However, the number of stable polarization states in such systems is typically limited to 32 at room temperature. Here we report the manipulation of thousands of non-volatile polarization states at room temperature in a sliding ferroelectric transistor that is composed of an aligned graphene monolayer atop hexagonal boron nitride. Solely regulated by source–drain pulses, more than 36 quasi-continuous polarization states can be generated at one doping level. Superimposing a gate voltage during the source–drain pulses can reversibly regulate the graphene Fermi energy between 84 doping levels, promoting the number of physically distinct polarization states to 3,024 (36 states × 84 doping levels). These polarization states can sustain for over 105 s and could potentially persist for 10 years. The abundant polarization states probably stem from the motion of polar domain walls and the moiré potential localizing the injected carriers. The simulation of during-training quantization in a deep residual network using the 3,024 polarization states shows a floating-point-comparable recognition accuracy (around 93.53%) for fashion images.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"56 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145968811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-14DOI: 10.1038/s41928-025-01535-7
A heat-shrinking method for fabricating conformal electronics is realized by patterning semi-liquid metal circuits onto thermoplastic substrates that are then heated to induce shrinkage around a three-dimensional target object. The method can be applied to diverse targets of different shapes and sizes, with the shape-adaptive electronics showing good electrical stability.
{"title":"Heat-shrinking method for the fabrication of conformal electronics","authors":"","doi":"10.1038/s41928-025-01535-7","DOIUrl":"10.1038/s41928-025-01535-7","url":null,"abstract":"A heat-shrinking method for fabricating conformal electronics is realized by patterning semi-liquid metal circuits onto thermoplastic substrates that are then heated to induce shrinkage around a three-dimensional target object. The method can be applied to diverse targets of different shapes and sizes, with the shape-adaptive electronics showing good electrical stability.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 1","pages":"21-22"},"PeriodicalIF":40.9,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146083450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-14DOI: 10.1038/s41928-025-01536-6
Ilia Valov, Xin Zheng
Transmission of information via photons could lead to compact three-dimensional neuromorphic computing hardware.
通过光子传输信息可能导致紧凑的三维神经形态计算硬件。
{"title":"A photonically linked memristive neural network","authors":"Ilia Valov, Xin Zheng","doi":"10.1038/s41928-025-01536-6","DOIUrl":"10.1038/s41928-025-01536-6","url":null,"abstract":"Transmission of information via photons could lead to compact three-dimensional neuromorphic computing hardware.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 1","pages":"19-20"},"PeriodicalIF":40.9,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146083422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In-memory computing combines memory and computing together in a single processing unit, eliminating the energy and latency overheads associated with data transfer between memory and computing units, which occurs in conventional systems. When implemented with crossbar arrays of memory devices, the approach can be used to accelerate low-level, data-intensive algebraic operations such as matrix–vector and inverse matrix–vector multiplication. However, although matrix–vector multiplication has recently been demonstrated, inverse matrix–vector multiplication faces additional challenges because of increased circuit implementation complexity. Here we report a fully integrated analogue closed-loop in-memory computing accelerator for inverse matrix–vector multiplication. The chip is based on static random-access memory and is fabricated in 90-nm complementary metal–oxide–semiconductor technology. It features two 64 × 64 memory arrays, enclosed in an analogue feedback loop by on-chip operational amplifiers, digital-to-analogue and analogue-to-digital converters. We experimentally show that the chip can be used to find solutions to systems of differential equations by recursive block inversion. It can also be used for sounding rocket trajectory tracking by Kalman filter and acceleration of inverse kinematics in robotic arms. The accuracy of the results closely matches fully digital systems working at the equivalent integrated circuit precision, providing advantages in terms of latency, energy and area consumption.
{"title":"A fully integrated analogue closed-loop in-memory computing accelerator based on static random-access memory","authors":"Piergiulio Mannocci, Carlo Zucchelli, Irene Andreoli, Andrea Pezzoli, Enrico Melacarne, Giacomo Pedretti, Flavio Sancandi, Corrado Villa, Zhong Sun, Umberto Spagnolini, Daniele Ielmini","doi":"10.1038/s41928-025-01549-1","DOIUrl":"https://doi.org/10.1038/s41928-025-01549-1","url":null,"abstract":"In-memory computing combines memory and computing together in a single processing unit, eliminating the energy and latency overheads associated with data transfer between memory and computing units, which occurs in conventional systems. When implemented with crossbar arrays of memory devices, the approach can be used to accelerate low-level, data-intensive algebraic operations such as matrix–vector and inverse matrix–vector multiplication. However, although matrix–vector multiplication has recently been demonstrated, inverse matrix–vector multiplication faces additional challenges because of increased circuit implementation complexity. Here we report a fully integrated analogue closed-loop in-memory computing accelerator for inverse matrix–vector multiplication. The chip is based on static random-access memory and is fabricated in 90-nm complementary metal–oxide–semiconductor technology. It features two 64 × 64 memory arrays, enclosed in an analogue feedback loop by on-chip operational amplifiers, digital-to-analogue and analogue-to-digital converters. We experimentally show that the chip can be used to find solutions to systems of differential equations by recursive block inversion. It can also be used for sounding rocket trajectory tracking by Kalman filter and acceleration of inverse kinematics in robotic arms. The accuracy of the results closely matches fully digital systems working at the equivalent integrated circuit precision, providing advantages in terms of latency, energy and area consumption.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"20 1","pages":""},"PeriodicalIF":34.3,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145968804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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