Pub Date : 2026-01-02DOI: 10.1038/s41928-025-01505-z
Bozhi Yin, Hayk Gevorgyan, Deniz Onural, Bohan Zhang, Anatoly Khilo, Miloš A. Popović, Vladimir M. Stojanović
The development of quantum and superconducting computer applications requires high-bandwidth and energy-efficient readout interfaces that can connect superconducting integrated circuits with a room-temperature environment. However, electrical and optical interconnect approaches involve extra amplification stages due to the low outputs of the superconducting circuits, which make them complicated, difficult to scale and a source of heat leakage. Here we describe a single-chip electronic–photonic transmitter that is driven directly by superconducting electronics and is fabricated using a commercial complementary metal–oxide–semiconductor foundry process. A laser-forwarded coherent-link architecture enables the transmitter to be directly driven at 4 K by a superconducting integrated circuit with only millivolt-level voltage swing and at a bit error rate of under 1 × 10−6. The energy efficiency of the link, at a temperature of 4 K and a laser power split ratio of 10/90, is 673 fJ per bit. An electronic–photonic transmitter chip can enable signal readout of superconducting electronics for interfacing with room-temperature environments.
{"title":"A fully packaged cryogenic optical transmitter directly interfaced with a superconducting chip","authors":"Bozhi Yin, Hayk Gevorgyan, Deniz Onural, Bohan Zhang, Anatoly Khilo, Miloš A. Popović, Vladimir M. Stojanović","doi":"10.1038/s41928-025-01505-z","DOIUrl":"10.1038/s41928-025-01505-z","url":null,"abstract":"The development of quantum and superconducting computer applications requires high-bandwidth and energy-efficient readout interfaces that can connect superconducting integrated circuits with a room-temperature environment. However, electrical and optical interconnect approaches involve extra amplification stages due to the low outputs of the superconducting circuits, which make them complicated, difficult to scale and a source of heat leakage. Here we describe a single-chip electronic–photonic transmitter that is driven directly by superconducting electronics and is fabricated using a commercial complementary metal–oxide–semiconductor foundry process. A laser-forwarded coherent-link architecture enables the transmitter to be directly driven at 4 K by a superconducting integrated circuit with only millivolt-level voltage swing and at a bit error rate of under 1 × 10−6. The energy efficiency of the link, at a temperature of 4 K and a laser power split ratio of 10/90, is 673 fJ per bit. An electronic–photonic transmitter chip can enable signal readout of superconducting electronics for interfacing with room-temperature environments.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 1","pages":"78-83"},"PeriodicalIF":40.9,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145894962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-23DOI: 10.1038/s41928-025-01550-8
Technology breakthroughs at the 2025 IEEE International Electron Devices Meeting, which celebrates 100 years of field-effect transistors.
2025年IEEE国际电子器件会议上的技术突破，庆祝场效应晶体管100周年。
{"title":"A device of the past and the future","authors":"","doi":"10.1038/s41928-025-01550-8","DOIUrl":"10.1038/s41928-025-01550-8","url":null,"abstract":"Technology breakthroughs at the 2025 IEEE International Electron Devices Meeting, which celebrates 100 years of field-effect transistors.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1119-1119"},"PeriodicalIF":40.9,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.nature.comhttps://www.nature.com/articles/s41928-025-01550-8.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-22DOI: 10.1038/s41928-025-01543-7
Zhengli Dou, Chuxin Lei, Kai Wu, Guihua Yu
Increasing power densities in microprocessors and artificial intelligence hardware are pushing the thermal limits of electronic systems, and thermal interface materials—thin layers that conduct heat between dissimilar surfaces—are central to addressing this challenge. Classical models suggest that efficient heat transfer is possible with such materials, but real-world performance is always limited by nanoscale roughness, imperfect contacts and degradation under thermal cycling. Here we explore the development of thermal interface materials. We examine the physical origin of interfacial thermal resistance and consider its impact on device scaling, efficiency and reliability. We then discuss material and design strategies that can balance thermal conductivity with mechanical compliance, bond line thickness and electrical insulation. Finally, we highlight the need to treat thermal interface materials, not as passive fillings, but as integral system components that are co-designed alongside device architectures, and propose an integrated engineering framework for the future development of thermal interface materials. This Perspective examines the development of thermal interface materials, exploring material and design strategies that balance thermal conductivity, mechanical compliance, thickness and electrical insulation, and proposes an integrated engineering framework for the future development of the materials.
{"title":"The development of thermal interface materials","authors":"Zhengli Dou, Chuxin Lei, Kai Wu, Guihua Yu","doi":"10.1038/s41928-025-01543-7","DOIUrl":"10.1038/s41928-025-01543-7","url":null,"abstract":"Increasing power densities in microprocessors and artificial intelligence hardware are pushing the thermal limits of electronic systems, and thermal interface materials—thin layers that conduct heat between dissimilar surfaces—are central to addressing this challenge. Classical models suggest that efficient heat transfer is possible with such materials, but real-world performance is always limited by nanoscale roughness, imperfect contacts and degradation under thermal cycling. Here we explore the development of thermal interface materials. We examine the physical origin of interfacial thermal resistance and consider its impact on device scaling, efficiency and reliability. We then discuss material and design strategies that can balance thermal conductivity with mechanical compliance, bond line thickness and electrical insulation. Finally, we highlight the need to treat thermal interface materials, not as passive fillings, but as integral system components that are co-designed alongside device architectures, and propose an integrated engineering framework for the future development of thermal interface materials. This Perspective examines the development of thermal interface materials, exploring material and design strategies that balance thermal conductivity, mechanical compliance, thickness and electrical insulation, and proposes an integrated engineering framework for the future development of the materials.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1146-1155"},"PeriodicalIF":40.9,"publicationDate":"2025-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-19DOI: 10.1038/s41928-025-01537-5
Abhairaj Singh, Manuel Le Gallo, Athanasios Vasilopoulos, Jose Luquin, Pritish Narayanan, Geoffrey W. Burr, Abu Sebastian
Analogue in-memory computing (AIMC) is an emerging computational approach that executes operations directly within memory arrays, reducing the need for data transfer between memory and processing units. AIMC-based accelerators are, in particular, being explored for deep neural network (DNN) inference, with the key element of such accelerators being the AIMC tile, which can be implemented using various conventional volatile charge-based and emerging non-volatile resistive memory (memristive) technologies. Here we examine the design of non-volatile memristive AIMC tiles for DNN accelerators. We explore the different components of a memristive AIMC tile and the range of mapping techniques for encoding signed multibit weights and inputs. We provide an analysis of the efficiency and accuracy of output encoding schemes, including various analogue-to-digital converter approaches. We also provide a comparative analysis of the different memory technologies being explored and projections for how technology scaling may impact key design components. This Perspective examines the design of non-volatile memristive analogue in-memory computing tiles for deep neural network accelerators, considering the challenges and opportunities associated with designing the different components and providing projections for how technology scaling may impact key design elements.
{"title":"The design of analogue in-memory computing tiles","authors":"Abhairaj Singh, Manuel Le Gallo, Athanasios Vasilopoulos, Jose Luquin, Pritish Narayanan, Geoffrey W. Burr, Abu Sebastian","doi":"10.1038/s41928-025-01537-5","DOIUrl":"10.1038/s41928-025-01537-5","url":null,"abstract":"Analogue in-memory computing (AIMC) is an emerging computational approach that executes operations directly within memory arrays, reducing the need for data transfer between memory and processing units. AIMC-based accelerators are, in particular, being explored for deep neural network (DNN) inference, with the key element of such accelerators being the AIMC tile, which can be implemented using various conventional volatile charge-based and emerging non-volatile resistive memory (memristive) technologies. Here we examine the design of non-volatile memristive AIMC tiles for DNN accelerators. We explore the different components of a memristive AIMC tile and the range of mapping techniques for encoding signed multibit weights and inputs. We provide an analysis of the efficiency and accuracy of output encoding schemes, including various analogue-to-digital converter approaches. We also provide a comparative analysis of the different memory technologies being explored and projections for how technology scaling may impact key design components. This Perspective examines the design of non-volatile memristive analogue in-memory computing tiles for deep neural network accelerators, considering the challenges and opportunities associated with designing the different components and providing projections for how technology scaling may impact key design elements.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1156-1169"},"PeriodicalIF":40.9,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-18DOI: 10.1038/s41928-025-01513-z
Claudio Pacchierotti
An 18-gram haptic feedback ring can deliver powerful force sensations while detecting multi-directional touch inputs, potentially transforming the way we can interact with digital environments.
{"title":"Haptic feedback that rings true","authors":"Claudio Pacchierotti","doi":"10.1038/s41928-025-01513-z","DOIUrl":"10.1038/s41928-025-01513-z","url":null,"abstract":"An 18-gram haptic feedback ring can deliver powerful force sensations while detecting multi-directional touch inputs, potentially transforming the way we can interact with digital environments.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1142-1143"},"PeriodicalIF":40.9,"publicationDate":"2025-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145771117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-18DOI: 10.1038/s41928-025-01515-x
Sunju Kang, Mustafa Mete, Srinivas Gandla, Dila Türkmen, Rohit Kadungamparambil John, Merve Acer Kalafat, Sunkook Kim, Jamie Paik
Wearable human–machine interfaces could provide immersive, multisensory interactions, turning everyday items into smart haptic devices for virtual and augmented reality. However, the development of tactile wearables with kinaesthetic feedback remains limited by the size and weight of the devices, which restricts portability and comfort. Here we report a haptic ring that weighs 18 g and offers three-degrees-of-freedom force sensing and feedback. The system has an origami-inspired structural base that provides efficient and compact force transmission, and a soft force-sensing skin capable of simultaneously detecting shear and normal forces. The force-sensing skin is made by combining a topology-optimized, laser-patterned layer that has pyramid microstructures with a layer with four resistive pixels, an approach that ensures linear sensitivity and a rapid response time. The ring, which is powered by soft pneumatic actuators and integrated with inkjet-printed bending sensors, can provide kinaesthetic force feedback of up to 6.5 N. A haptic ring that has a soft multiaxis force-sensing skin capable of simultaneously detecting shear and normal force can provide a kinaesthetic force feedback of up to 6.5 N.
{"title":"An 18-g haptic feedback ring with a three-axis force-sensing skin","authors":"Sunju Kang, Mustafa Mete, Srinivas Gandla, Dila Türkmen, Rohit Kadungamparambil John, Merve Acer Kalafat, Sunkook Kim, Jamie Paik","doi":"10.1038/s41928-025-01515-x","DOIUrl":"10.1038/s41928-025-01515-x","url":null,"abstract":"Wearable human–machine interfaces could provide immersive, multisensory interactions, turning everyday items into smart haptic devices for virtual and augmented reality. However, the development of tactile wearables with kinaesthetic feedback remains limited by the size and weight of the devices, which restricts portability and comfort. Here we report a haptic ring that weighs 18 g and offers three-degrees-of-freedom force sensing and feedback. The system has an origami-inspired structural base that provides efficient and compact force transmission, and a soft force-sensing skin capable of simultaneously detecting shear and normal forces. The force-sensing skin is made by combining a topology-optimized, laser-patterned layer that has pyramid microstructures with a layer with four resistive pixels, an approach that ensures linear sensitivity and a rapid response time. The ring, which is powered by soft pneumatic actuators and integrated with inkjet-printed bending sensors, can provide kinaesthetic force feedback of up to 6.5 N. A haptic ring that has a soft multiaxis force-sensing skin capable of simultaneously detecting shear and normal force can provide a kinaesthetic force feedback of up to 6.5 N.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1234-1246"},"PeriodicalIF":40.9,"publicationDate":"2025-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145771118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-17DOI: 10.1038/s41928-025-01499-8
Najam U Sakib, Chen Chen, Lei Ding, Yang Yang, Joan M. Redwing, Saptarshi Das
As silicon reaches its scaling limits, two-dimensional materials are a promising route for further transistor miniaturization. Advances in contact engineering, channel length (LCH) scaling and high-κ dielectric integration have led to impressive two-dimensional transistor performance, but challenges remain, including high off-state leakage currents due to negative threshold voltage values and high contact resistances as contact length (LC) is reduced. A monolayer-centric approach has also limited the exploration of the advantages that few-layer (two to three) materials may offer. Here we show that industry-compatible metal–organic chemical vapour deposition can be used to grow wafer-scale molybdenum disulfide (MoS2) and fabricate transistors with LCH and LC scaled to 35 nm and 30 nm, respectively. We integrate a high-κ gate dielectric with an equivalent oxide thickness of less than 2.5 nm and create monolayer, bilayer and trilayer MoS2 transistors. The scaled trilayer transistors exhibit an on-state current of 220 µA µm−1, a positive threshold voltage and off-state current below 10 pA µm−1 at zero gate bias. Trilayer MoS2 transistors show enhanced performance compared with monolayer devices at scaled LC due to a shorter transfer length and lower Schottky barrier height. To illustrate the reliability and reproducibility of the approach, we provide statistics for approximately 1,000 scaled devices. Molybdenum disulfide transistors made with an industry-compatible metal–organic chemical vapour deposition method can exhibit both high on-state and low off-state currents with a channel length of 35 nm and contact length of 30 nm.
当硅达到其缩放极限时，二维材料是进一步小型化晶体管的有希望的途径。触点工程、通道长度（LCH）缩放和高κ介电体集成方面的进步已经带来了令人印象深刻的二维晶体管性能，但挑战仍然存在，包括由于负阈值电压值和触点长度（LC）减少而产生的高断开状态泄漏电流和高接触电阻。以单层为中心的方法也限制了对少层（两到三层）材料可能提供的优势的探索。在这里，我们证明了工业兼容的金属有机化学气相沉积可以用于生长晶圆级二硫化钼（MoS2）和制造LCH和LC分别缩放到35 nm和30 nm的晶体管。我们集成了等效氧化物厚度小于2.5 nm的高κ栅极电介质，并创建了单层，双层和三层MoS2晶体管。该三层晶体管在零栅极偏置下具有220 μ A μ m−1的导通电流、正阈值电压和低于10 pA μ m−1的关断电流。由于传输长度较短，肖特基势垒高度较低，三层MoS2晶体管在比例LC下的性能优于单层器件。为了说明该方法的可靠性和可重复性，我们提供了大约1,000个缩放设备的统计数据。
{"title":"High-performance molybdenum disulfide transistors with channel and contact lengths below 35 nm","authors":"Najam U Sakib, Chen Chen, Lei Ding, Yang Yang, Joan M. Redwing, Saptarshi Das","doi":"10.1038/s41928-025-01499-8","DOIUrl":"10.1038/s41928-025-01499-8","url":null,"abstract":"As silicon reaches its scaling limits, two-dimensional materials are a promising route for further transistor miniaturization. Advances in contact engineering, channel length (LCH) scaling and high-κ dielectric integration have led to impressive two-dimensional transistor performance, but challenges remain, including high off-state leakage currents due to negative threshold voltage values and high contact resistances as contact length (LC) is reduced. A monolayer-centric approach has also limited the exploration of the advantages that few-layer (two to three) materials may offer. Here we show that industry-compatible metal–organic chemical vapour deposition can be used to grow wafer-scale molybdenum disulfide (MoS2) and fabricate transistors with LCH and LC scaled to 35 nm and 30 nm, respectively. We integrate a high-κ gate dielectric with an equivalent oxide thickness of less than 2.5 nm and create monolayer, bilayer and trilayer MoS2 transistors. The scaled trilayer transistors exhibit an on-state current of 220 µA µm−1, a positive threshold voltage and off-state current below 10 pA µm−1 at zero gate bias. Trilayer MoS2 transistors show enhanced performance compared with monolayer devices at scaled LC due to a shorter transfer length and lower Schottky barrier height. To illustrate the reliability and reproducibility of the approach, we provide statistics for approximately 1,000 scaled devices. Molybdenum disulfide transistors made with an industry-compatible metal–organic chemical vapour deposition method can exhibit both high on-state and low off-state currents with a channel length of 35 nm and contact length of 30 nm.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1201-1210"},"PeriodicalIF":40.9,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145765584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-17DOI: 10.1038/s41928-025-01500-4
Mingyi Du, Weisheng Li, Guangkai Xiong, Chunsong Zhao, Fuchen Hou, Weizhuo Gan, Xiaoshu Gong, Ningmu Zou, Lei Liu, Xilu Zou, Taotao Li, Wenjie Sun, Dongxu Fan, Zhihao Yu, Xuecou Tu, Yuan Gao, Haoliang Shen, Hao Qiu, Liang Ma, Jinlan Wang, Yuefeng Nie, Li Tao, Jian-Bin Xu, Junhao Lin, Jeffrey Xu, Yi Shi, Xinran Wang
Transition metal dichalcogenides are a potential alternative to silicon and could be used to create transistors with a contacted gate pitch below 40 nm as required by the ångström-node transistor technology. However, it remains challenging to maintain an ohmic contact when the contact length is reduced to less than 20 nm. Here we show that crystalline semi-metallic antimony contacts can be epitaxially grown on molybdenum disulfide (MoS2) by molecular beam epitaxy, creating ohmic contacts with a resistance of 98 Ω µm at a contact length of 18 nm. We use the contacts to build scaled field-effect transistors with a contacted gate pitch of 40 nm with drive currents of 0.85 mA µm−1, 0.95 mA µm−1 and 1.08 mA µm−1 for monolayer, bilayer and trilayer MoS2 channels, respectively. Statistical analysis of transistor arrays confirms that the crystalline antimony contacts are reproducible and stable. Semi-metallic single crystals of antimony can be deposited using molecular beam epitaxy on molybdenum disulfide to create ohmic contacts with resistance of under 100 Ω µm at a contact length of 18 nm.
{"title":"Scaled crystalline antimony ohmic contacts for two-dimensional transistors","authors":"Mingyi Du, Weisheng Li, Guangkai Xiong, Chunsong Zhao, Fuchen Hou, Weizhuo Gan, Xiaoshu Gong, Ningmu Zou, Lei Liu, Xilu Zou, Taotao Li, Wenjie Sun, Dongxu Fan, Zhihao Yu, Xuecou Tu, Yuan Gao, Haoliang Shen, Hao Qiu, Liang Ma, Jinlan Wang, Yuefeng Nie, Li Tao, Jian-Bin Xu, Junhao Lin, Jeffrey Xu, Yi Shi, Xinran Wang","doi":"10.1038/s41928-025-01500-4","DOIUrl":"10.1038/s41928-025-01500-4","url":null,"abstract":"Transition metal dichalcogenides are a potential alternative to silicon and could be used to create transistors with a contacted gate pitch below 40 nm as required by the ångström-node transistor technology. However, it remains challenging to maintain an ohmic contact when the contact length is reduced to less than 20 nm. Here we show that crystalline semi-metallic antimony contacts can be epitaxially grown on molybdenum disulfide (MoS2) by molecular beam epitaxy, creating ohmic contacts with a resistance of 98 Ω µm at a contact length of 18 nm. We use the contacts to build scaled field-effect transistors with a contacted gate pitch of 40 nm with drive currents of 0.85 mA µm−1, 0.95 mA µm−1 and 1.08 mA µm−1 for monolayer, bilayer and trilayer MoS2 channels, respectively. Statistical analysis of transistor arrays confirms that the crystalline antimony contacts are reproducible and stable. Semi-metallic single crystals of antimony can be deposited using molecular beam epitaxy on molybdenum disulfide to create ohmic contacts with resistance of under 100 Ω µm at a contact length of 18 nm.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1191-1200"},"PeriodicalIF":40.9,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145765609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-17DOI: 10.1038/s41928-025-01501-3
Wei Zeng, Su-Ting Han, Ye Zhou
Two papers report molybdenum disulfide transistors with highly scaled channel and contact lengths, which is achieved through multilayer channel optimization in one case and molecular beam epitaxy deposition of single-crystal antimony contacts in the other.
{"title":"Towards 1-nm-node electronics with two-dimensional transistors","authors":"Wei Zeng, Su-Ting Han, Ye Zhou","doi":"10.1038/s41928-025-01501-3","DOIUrl":"10.1038/s41928-025-01501-3","url":null,"abstract":"Two papers report molybdenum disulfide transistors with highly scaled channel and contact lengths, which is achieved through multilayer channel optimization in one case and molecular beam epitaxy deposition of single-crystal antimony contacts in the other.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1138-1139"},"PeriodicalIF":40.9,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145771119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1038/s41928-025-01517-9
Haoxuan Sun, Chen Li, Liang Li, Xiang Zhang, Jiajun Luo, Nur Najihah binti Ahmad Rasid, Nur Wardina Syahirah binti Mohamad Fadil, Maria Vasilopoulou, Abd. Rashid bin Mohd Yusoff
The capabilities of photodetectors based on halide perovskites have advanced rapidly in recent years, with their typical metrics—including responsivity, detectivity and response speed—surpassing those of silicon detectors. However, concerns regarding reliability and manufacturing yield limit commercial interest in replacing established technology with perovskite devices in conventional applications such as communications and imaging. A promising initial step towards the broader commercialization of perovskite detectors lies in customized device architectures for specific applications or products, an approach that can fully leverage the compositional versatility and integration capabilities of perovskite materials. Here we explore the development of traditional standardized perovskite photodetectors and consider the emergence of customized perovskite photodetectors, including shape-customized detectors, selective photodetectors, multidimensional photodetectors, dynamic-tracking detectors and neuromorphic visual sensors. We also consider the key challenges that need to be addressed to deliver application-specific devices for commercial applications. This Review examines perovskite photodetector technology, exploring the development of standardized perovskite photodetectors and the emergence of customized perovskite photodetectors, including shape-customized detectors, selective photodetectors, multidimensional photodetectors, dynamic-tracking detectors and neuromorphic visual sensors.
{"title":"The development of customized perovskite photodetectors","authors":"Haoxuan Sun, Chen Li, Liang Li, Xiang Zhang, Jiajun Luo, Nur Najihah binti Ahmad Rasid, Nur Wardina Syahirah binti Mohamad Fadil, Maria Vasilopoulou, Abd. Rashid bin Mohd Yusoff","doi":"10.1038/s41928-025-01517-9","DOIUrl":"10.1038/s41928-025-01517-9","url":null,"abstract":"The capabilities of photodetectors based on halide perovskites have advanced rapidly in recent years, with their typical metrics—including responsivity, detectivity and response speed—surpassing those of silicon detectors. However, concerns regarding reliability and manufacturing yield limit commercial interest in replacing established technology with perovskite devices in conventional applications such as communications and imaging. A promising initial step towards the broader commercialization of perovskite detectors lies in customized device architectures for specific applications or products, an approach that can fully leverage the compositional versatility and integration capabilities of perovskite materials. Here we explore the development of traditional standardized perovskite photodetectors and consider the emergence of customized perovskite photodetectors, including shape-customized detectors, selective photodetectors, multidimensional photodetectors, dynamic-tracking detectors and neuromorphic visual sensors. We also consider the key challenges that need to be addressed to deliver application-specific devices for commercial applications. This Review examines perovskite photodetector technology, exploring the development of standardized perovskite photodetectors and the emergence of customized perovskite photodetectors, including shape-customized detectors, selective photodetectors, multidimensional photodetectors, dynamic-tracking detectors and neuromorphic visual sensors.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1170-1181"},"PeriodicalIF":40.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145771120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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