Pub Date : 2025-10-17DOI: 10.1038/s41928-025-01470-7
Brittany N. Smith, Faris M. Albarghouthi, James L. Doherty, Xuancheng Pei, Quentin Macfarlane, Matthew Salfity, Daniel Badia, Marc Pascual, Pascal Boncenne, Nathan Bigan, Amin M’Barki, Aaron D. Franklin
Printed transistors have a wide range of applications, but the limited resolution of printing techniques (10–30 µm) has been a barrier to utility and scalability. Printed submicrometre channel lengths have previously been achieved. However, this has required chemical processes or tedious post-processing, which limits applicability. Here we show that capillary flow printing can create submicrometre carbon nanotube thin-film transistors without chemical modification or physical manipulation after printing. We show that the approach can be used to print conducting, semiconducting and insulating inks on different types of substrate (silicon, Kapton and paper), and can be used to fabricate various thin-film transistor device architectures. The printed carbon nanotube thin-film transistors exhibit on-currents of 1.12 mA mm−1 when back gated on Si/SiO2 and 490 µA mm−1 when side gated through ion gel on Kapton. We also show that devices printed on Kapton offer mechanical bending and sweep rate resilience, illustrating the potential of these printed devices for flexible applications. A capillary flow printing technique can be used to fabricate printed carbon nanotube thin-film transistors with submicrometre channel lengths on rigid or flexible substrates.
印刷晶体管具有广泛的应用，但印刷技术的有限分辨率（10-30 μ m）一直是实用性和可扩展性的障碍。印刷亚微米通道长度以前已经实现。然而，这需要化学过程或繁琐的后处理，这限制了适用性。在这里，我们证明了毛细管流动印刷可以在印刷后不需要化学修饰或物理操作的情况下制造亚微米碳纳米管薄膜晶体管。我们证明，该方法可用于在不同类型的衬底（硅、卡普顿和纸）上印刷导电、半导体和绝缘油墨，并可用于制造各种薄膜晶体管器件结构。在Si/SiO2上背门控时，碳纳米管薄膜晶体管的导通电流为1.12 mA mm−1，在Kapton上通过离子凝胶侧门控时，导通电流为490µA mm−1。我们还表明，在Kapton上印刷的设备具有机械弯曲和扫描速率弹性，说明了这些印刷设备在灵活应用方面的潜力。毛细管流动印刷技术可用于在刚性或柔性衬底上制备通道长度为亚微米的碳纳米管薄膜晶体管。
{"title":"Capillary flow printing of submicrometre carbon nanotube transistors","authors":"Brittany N. Smith, Faris M. Albarghouthi, James L. Doherty, Xuancheng Pei, Quentin Macfarlane, Matthew Salfity, Daniel Badia, Marc Pascual, Pascal Boncenne, Nathan Bigan, Amin M’Barki, Aaron D. Franklin","doi":"10.1038/s41928-025-01470-7","DOIUrl":"10.1038/s41928-025-01470-7","url":null,"abstract":"Printed transistors have a wide range of applications, but the limited resolution of printing techniques (10–30 µm) has been a barrier to utility and scalability. Printed submicrometre channel lengths have previously been achieved. However, this has required chemical processes or tedious post-processing, which limits applicability. Here we show that capillary flow printing can create submicrometre carbon nanotube thin-film transistors without chemical modification or physical manipulation after printing. We show that the approach can be used to print conducting, semiconducting and insulating inks on different types of substrate (silicon, Kapton and paper), and can be used to fabricate various thin-film transistor device architectures. The printed carbon nanotube thin-film transistors exhibit on-currents of 1.12 mA mm−1 when back gated on Si/SiO2 and 490 µA mm−1 when side gated through ion gel on Kapton. We also show that devices printed on Kapton offer mechanical bending and sweep rate resilience, illustrating the potential of these printed devices for flexible applications. A capillary flow printing technique can be used to fabricate printed carbon nanotube thin-film transistors with submicrometre channel lengths on rigid or flexible substrates.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 11","pages":"1027-1037"},"PeriodicalIF":40.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145382429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1038/s41928-025-01467-2
Hansol Park, Cheong Beom Lee, Jongmin Lee, Seon-Jeong Lim, Bum Ho Jeong, Hakjun Kim, Seong Jae Lee, Hayoung Oh, Hyungju Ahn, Do Hwan Kim, Kyeounghak Kim, Hui Joon Park
Tin halide perovskites are a potential p-type channel material for thin-film transistors due to their high room-temperature hole mobility and easy processability. However, creating a high-quality thin film with a three-dimensional tin halide perovskite is challenging due to its inherent instability and defect density. Here we show that the coordinated control of A-site cations and X-site anions in a three-dimensional perovskite, formamidinium tin iodide (FASnI3), using methylammonium chloride (MACl) can stabilize the crystal structure. Unlike lead halide perovskites, where MACl functions only as a volatile intermediate-phase stabilizer, we show that MACl is incorporated into the FASnI3 crystal structure through the substitution of FA and I components with MA and Cl, which enhances its stability. The resulting uniform thin films offer improved crystallinity and larger grain sizes. A MACl-substituted FASnI3 transistor exhibits a field-effect hole mobility of over 80 cm2 V−1 s−1, an on/off current ratio over 3.0 × 109 and a threshold voltage of around 0 V, as well as high operational reliability and hysteresis-free behaviour. A three-dimensional tin halide perovskite can be stabilized by incorporating methylammonium chloride into the perovskite structure and used to create p-type thin-film transistors with a hole mobility of over 80 cm2 V−1 s−1.
{"title":"Non-volatile methylammonium chloride substitution for tin halide perovskite transistors","authors":"Hansol Park, Cheong Beom Lee, Jongmin Lee, Seon-Jeong Lim, Bum Ho Jeong, Hakjun Kim, Seong Jae Lee, Hayoung Oh, Hyungju Ahn, Do Hwan Kim, Kyeounghak Kim, Hui Joon Park","doi":"10.1038/s41928-025-01467-2","DOIUrl":"10.1038/s41928-025-01467-2","url":null,"abstract":"Tin halide perovskites are a potential p-type channel material for thin-film transistors due to their high room-temperature hole mobility and easy processability. However, creating a high-quality thin film with a three-dimensional tin halide perovskite is challenging due to its inherent instability and defect density. Here we show that the coordinated control of A-site cations and X-site anions in a three-dimensional perovskite, formamidinium tin iodide (FASnI3), using methylammonium chloride (MACl) can stabilize the crystal structure. Unlike lead halide perovskites, where MACl functions only as a volatile intermediate-phase stabilizer, we show that MACl is incorporated into the FASnI3 crystal structure through the substitution of FA and I components with MA and Cl, which enhances its stability. The resulting uniform thin films offer improved crystallinity and larger grain sizes. A MACl-substituted FASnI3 transistor exhibits a field-effect hole mobility of over 80 cm2 V−1 s−1, an on/off current ratio over 3.0 × 109 and a threshold voltage of around 0 V, as well as high operational reliability and hysteresis-free behaviour. A three-dimensional tin halide perovskite can be stabilized by incorporating methylammonium chloride into the perovskite structure and used to create p-type thin-film transistors with a hole mobility of over 80 cm2 V−1 s−1.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 10","pages":"934-948"},"PeriodicalIF":40.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145371944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1038/s41928-025-01415-0
Yuanyuan Hu, Lang Jiang
{"title":"Third-party certification of high mobility values in perovskite transistors","authors":"Yuanyuan Hu, Lang Jiang","doi":"10.1038/s41928-025-01415-0","DOIUrl":"10.1038/s41928-025-01415-0","url":null,"abstract":"","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 10","pages":"873-873"},"PeriodicalIF":40.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145371954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1038/s41928-025-01469-0
Saravanan Yuvaraja, Mohamad Insan Nugraha, Qiao He, Leo Raj Solay, Patsy Arely Miranda Cortez, Na Xiao, Martin Heeney, Thomas D. Anthopoulos, Xiaohang Li
The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal oxide thin-film transistors and p-type organic thin-film transistors offers a potential solution. However, increasing the transistor density of these systems through vertical stacking is challenging due to issues related to thermal budget and interface roughness. Here we report a six-stack hybrid complementary transistor technology that has 41 layers and uses n-type indium oxide (In2O3) and a p-type organic semiconductor (C16IDT-BT) as channel materials. We test 600 transistors and show that n-type oxide devices and p-type organic devices exhibit comparable field-effect mobilities and saturation currents. We also create 300 hybrid inverters by integrating the oxide and organic transistors; the circuits exhibit a gain of 94.84 V V−1 and a power consumption of 0.47 µW. We also fabricate NAND and NOR gates comprising transistors from four stacks. Thermal stability analysis shows that device characteristics begin to degrade above 50 °C, a known limitation of low-thermal-budget processes. Such performance is sufficient for many large-area electronics applications, but further thermal optimization will be necessary to extend operational robustness towards standard industrial conditions. A six-stack hybrid complementary transistor technology that uses n-type indium oxide and a p-type organic semiconductor as channel materials can be used to build inverters that exhibit a gain of 94.84 V V−1 and a power consumption of 0.47 µW.
低功耗计算领域的发展需要紧凑、节能和高性能的集成电路。结合n型金属氧化物薄膜晶体管和p型有机薄膜晶体管的混合技术提供了一个潜在的解决方案。然而，由于与热预算和界面粗糙度相关的问题，通过垂直堆叠来增加这些系统的晶体管密度是具有挑战性的。在这里，我们报告了一种六层混合互补晶体管技术，该技术有41层，使用n型氧化铟（In2O3）和p型有机半导体（C16IDT-BT）作为通道材料。我们测试了600个晶体管，并表明n型氧化物器件和p型有机器件具有相当的场效应迁移率和饱和电流。我们还通过集成氧化物和有机晶体管创造了300个混合逆变器；电路增益为94.84 V V−1，功耗为0.47µW。我们还制造由四层晶体管组成的NAND和NOR门。热稳定性分析表明，器件特性在50°C以上开始退化，这是已知的低热预算工艺的限制。这样的性能对于许多大面积的电子应用来说已经足够了，但是进一步的热优化将是必要的，以扩展在标准工业条件下的操作稳健性。采用n型氧化铟和p型有机半导体作为沟道材料的六叠混合互补晶体管技术可用于构建增益为94.84 V V−1，功耗为0.47 μ W的逆变器。
{"title":"Three-dimensional integrated hybrid complementary circuits for large-area electronics","authors":"Saravanan Yuvaraja, Mohamad Insan Nugraha, Qiao He, Leo Raj Solay, Patsy Arely Miranda Cortez, Na Xiao, Martin Heeney, Thomas D. Anthopoulos, Xiaohang Li","doi":"10.1038/s41928-025-01469-0","DOIUrl":"10.1038/s41928-025-01469-0","url":null,"abstract":"The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal oxide thin-film transistors and p-type organic thin-film transistors offers a potential solution. However, increasing the transistor density of these systems through vertical stacking is challenging due to issues related to thermal budget and interface roughness. Here we report a six-stack hybrid complementary transistor technology that has 41 layers and uses n-type indium oxide (In2O3) and a p-type organic semiconductor (C16IDT-BT) as channel materials. We test 600 transistors and show that n-type oxide devices and p-type organic devices exhibit comparable field-effect mobilities and saturation currents. We also create 300 hybrid inverters by integrating the oxide and organic transistors; the circuits exhibit a gain of 94.84 V V−1 and a power consumption of 0.47 µW. We also fabricate NAND and NOR gates comprising transistors from four stacks. Thermal stability analysis shows that device characteristics begin to degrade above 50 °C, a known limitation of low-thermal-budget processes. Such performance is sufficient for many large-area electronics applications, but further thermal optimization will be necessary to extend operational robustness towards standard industrial conditions. A six-stack hybrid complementary transistor technology that uses n-type indium oxide and a p-type organic semiconductor as channel materials can be used to build inverters that exhibit a gain of 94.84 V V−1 and a power consumption of 0.47 µW.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 10","pages":"969-980"},"PeriodicalIF":40.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.nature.comhttps://www.nature.com/articles/s41928-025-01469-0.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145371971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-16DOI: 10.1038/s41928-025-01460-9
Hongji Zhou, Tianchi Zhou, Yaxin Zhang, Hongxin Zeng, Shixiong Liang, Jun Zhou, Huajie Liang, Lin Huang, Sen Gong, Yazhou Dong, Jingrui Liang, Hailong Guo, Zhihong Feng, Ziqiang Yang, Daniel M. Mittleman
Frequency multiplier devices based on Schottky barrier diodes can be used to generate terahertz radiation, offering high power output and potential integration into all-solid-state systems. However, the scaling of the output power of such devices is often limited by the power handling capacity of a single diode. A connected chain of Schottky barrier diodes, together with a power combining approach, can be used to increase the terahertz output power. However, the uneven field distribution among the diodes—which is related to the similarity between the terahertz wavelength and the physical dimensions of the diodes themselves—leads to lower efficiency and premature breakdown. Here we report an asymmetric double-layer C-shaped diode chain structure that can adjust the local electromagnetic field distribution and enhance the conversion efficiency of the diode chain. Our resulting device has a frequency doubling efficiency of 38%, with an output exceeding 300 mW at 170 GHz. An asymmetric double-layer C-shaped diode chain structure that can adjust the local electromagnetic field distribution can be used to create a terahertz device with a frequency doubling efficiency of 38%.
{"title":"A terahertz nonlinear diode chain based on an asymmetric double-layer topology","authors":"Hongji Zhou, Tianchi Zhou, Yaxin Zhang, Hongxin Zeng, Shixiong Liang, Jun Zhou, Huajie Liang, Lin Huang, Sen Gong, Yazhou Dong, Jingrui Liang, Hailong Guo, Zhihong Feng, Ziqiang Yang, Daniel M. Mittleman","doi":"10.1038/s41928-025-01460-9","DOIUrl":"10.1038/s41928-025-01460-9","url":null,"abstract":"Frequency multiplier devices based on Schottky barrier diodes can be used to generate terahertz radiation, offering high power output and potential integration into all-solid-state systems. However, the scaling of the output power of such devices is often limited by the power handling capacity of a single diode. A connected chain of Schottky barrier diodes, together with a power combining approach, can be used to increase the terahertz output power. However, the uneven field distribution among the diodes—which is related to the similarity between the terahertz wavelength and the physical dimensions of the diodes themselves—leads to lower efficiency and premature breakdown. Here we report an asymmetric double-layer C-shaped diode chain structure that can adjust the local electromagnetic field distribution and enhance the conversion efficiency of the diode chain. Our resulting device has a frequency doubling efficiency of 38%, with an output exceeding 300 mW at 170 GHz. An asymmetric double-layer C-shaped diode chain structure that can adjust the local electromagnetic field distribution can be used to create a terahertz device with a frequency doubling efficiency of 38%.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 10","pages":"895-905"},"PeriodicalIF":40.9,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145371943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Non-volatile compute-in-memory macros can reduce data transfer between processing and memory units, providing fast and energy-efficient artificial intelligence computations. However, the non-volatile compute-in-memory architecture typically relies on analogue computing, which is limited in terms of accuracy, scalability and robustness. Here we report a 64-kb non-volatile digital compute-in-memory macro based on 40-nm spin-transfer torque magnetic random-access memory technology. Our macro features in situ multiplication and digitization at the bitcell level, precision-reconfigurable digital addition and accumulation at the macro level and a toggle-rate-aware training scheme at the algorithm level. The macro supports lossless matrix–vector multiplications with flexible input and weight precisions (4, 8, 12 and 16 bits), and can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision. Our non-volatile compute-in-memory macro has computation latencies of 7.4–29.6 ns and energy efficiencies of 7.02–112.3 tera-operations per second per watt for fully parallel matrix–vector multiplications across precision configurations ranging from 4 to 16 bits. A 64-kb non-volatile digital compute-in-memory macro that is based on 40-nm spin-transfer torque magnetic random-access memory technology can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision.
{"title":"A lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips","authors":"Humiao Li, Zheng Chai, Weirong Dong, Junjie He, Ruijie Peng, Shiheng Li, Zhen Kong, Xihui Yuan, Xianwang Wang, Zhengke Yang, Haoran Lyu, Haofeng Yu, Xue Zhou, Jiamin Li, Feichi Zhou, Yida Li, Zongben Xu, Tai Min, Longyang Lin","doi":"10.1038/s41928-025-01479-y","DOIUrl":"10.1038/s41928-025-01479-y","url":null,"abstract":"Non-volatile compute-in-memory macros can reduce data transfer between processing and memory units, providing fast and energy-efficient artificial intelligence computations. However, the non-volatile compute-in-memory architecture typically relies on analogue computing, which is limited in terms of accuracy, scalability and robustness. Here we report a 64-kb non-volatile digital compute-in-memory macro based on 40-nm spin-transfer torque magnetic random-access memory technology. Our macro features in situ multiplication and digitization at the bitcell level, precision-reconfigurable digital addition and accumulation at the macro level and a toggle-rate-aware training scheme at the algorithm level. The macro supports lossless matrix–vector multiplications with flexible input and weight precisions (4, 8, 12 and 16 bits), and can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision. Our non-volatile compute-in-memory macro has computation latencies of 7.4–29.6 ns and energy efficiencies of 7.02–112.3 tera-operations per second per watt for fully parallel matrix–vector multiplications across precision configurations ranging from 4 to 16 bits. A 64-kb non-volatile digital compute-in-memory macro that is based on 40-nm spin-transfer torque magnetic random-access memory technology can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 11","pages":"1046-1058"},"PeriodicalIF":40.9,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145382430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-15DOI: 10.1038/s41928-025-01483-2
Dashan Shang, Qing Luo
An energy-efficient hybrid memory that incorporates both ferroelectric capacitors and analogue memristors can accelerate on-chip inference and training.
结合铁电电容器和模拟忆阻器的节能混合存储器可以加速片上推理和训练。
{"title":"Hybrid memory to empower edge AI","authors":"Dashan Shang, Qing Luo","doi":"10.1038/s41928-025-01483-2","DOIUrl":"10.1038/s41928-025-01483-2","url":null,"abstract":"An energy-efficient hybrid memory that incorporates both ferroelectric capacitors and analogue memristors can accelerate on-chip inference and training.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 10","pages":"880-881"},"PeriodicalIF":40.9,"publicationDate":"2025-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145371935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1038/s41928-025-01478-z
Yizhou Zhong, Sahika Inal
A stretchable biosensor with a diode-connected extended-gate transistor pair design can avoid problems related to signal drift, providing reliable detection of biomarkers directly from sweat.
{"title":"Sweat sensors that won’t catch your drift","authors":"Yizhou Zhong, Sahika Inal","doi":"10.1038/s41928-025-01478-z","DOIUrl":"10.1038/s41928-025-01478-z","url":null,"abstract":"A stretchable biosensor with a diode-connected extended-gate transistor pair design can avoid problems related to signal drift, providing reliable detection of biomarkers directly from sweat.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 10","pages":"884-885"},"PeriodicalIF":40.9,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145371942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Precision has long been the central bottleneck of analogue computing. Bit-slicing or analogue compensation can be used to perform matrix–vector multiplication with precision, but solving matrix equations using such techniques is challenging. Here we describe a precise and scalable analogue matrix inversion solver. Our approach uses an iterative algorithm that combines analogue low-precision matrix inversion and analogue high-precision matrix–vector multiplication operations. Both operations are implemented using 3-bit resistive random-access memory chips that are fabricated in a foundry. By combining these with a block matrix algorithm, inversion problems involving 16 × 16 real-valued matrices are experimentally solved with 24-bit fixed-point precision (comparable to 32-bit floating point; FP32). Applied to signal detection in massive multi-input and multi-output systems, our approach achieves performance comparable to FP32 digital processors in just three iterations. Benchmarking shows that our analogue computing approach could offer a 1,000 times higher throughput and 100 times better energy efficiency than state-of-the-art digital processors for the same precision. An analogue matrix solver that combines low-precision matrix inversion and high-precision matrix–vector multiplication can be used to solve inversion problems involving 16 × 16 real-valued matrices with precision comparable to 32-bit floating point.
{"title":"Precise and scalable analogue matrix equation solving using resistive random-access memory chips","authors":"Pushen Zuo, Qishen Wang, Yubiao Luo, Ruiqing Xie, Shiqing Wang, Zezhi Cheng, Lin Bao, Zongwei Wang, Yimao Cai, Ru Huang, Zhong Sun","doi":"10.1038/s41928-025-01477-0","DOIUrl":"10.1038/s41928-025-01477-0","url":null,"abstract":"Precision has long been the central bottleneck of analogue computing. Bit-slicing or analogue compensation can be used to perform matrix–vector multiplication with precision, but solving matrix equations using such techniques is challenging. Here we describe a precise and scalable analogue matrix inversion solver. Our approach uses an iterative algorithm that combines analogue low-precision matrix inversion and analogue high-precision matrix–vector multiplication operations. Both operations are implemented using 3-bit resistive random-access memory chips that are fabricated in a foundry. By combining these with a block matrix algorithm, inversion problems involving 16 × 16 real-valued matrices are experimentally solved with 24-bit fixed-point precision (comparable to 32-bit floating point; FP32). Applied to signal detection in massive multi-input and multi-output systems, our approach achieves performance comparable to FP32 digital processors in just three iterations. Benchmarking shows that our analogue computing approach could offer a 1,000 times higher throughput and 100 times better energy efficiency than state-of-the-art digital processors for the same precision. An analogue matrix solver that combines low-precision matrix inversion and high-precision matrix–vector multiplication can be used to solve inversion problems involving 16 × 16 real-valued matrices with precision comparable to 32-bit floating point.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"8 12","pages":"1222-1233"},"PeriodicalIF":40.9,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.nature.comhttps://www.nature.com/articles/s41928-025-01477-0.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-08DOI: 10.1038/s41928-025-01466-3
Hans Kleemann
Organic thin-film tunnel transistors with subthreshold swings as low as 24.2 mV dec−1 can be created with the help of a molecular decoupling layer that lowers the energy barrier to tunnelling.
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