Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988957
Lin Wei, Cheng Chao, U. Singh, Ruchil Jain, Li Leng Goh, P. R. Verma
A new kind of field plate as contact field plate is fabricated for hot carrier injection improvement, significant decrease in the specified on resistance degradation is observed without substantially affecting the breakdown voltage of devices. Charge pumping method and simulation are carried out to study the degradation mechanism. Our results clearly show that the application of contact field plate can improve the device robustness in terms of hot carrier injection.
{"title":"A novel contact field plate application in drain-extended-MOSFET transistors","authors":"Lin Wei, Cheng Chao, U. Singh, Ruchil Jain, Li Leng Goh, P. R. Verma","doi":"10.23919/ISPSD.2017.7988957","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988957","url":null,"abstract":"A new kind of field plate as contact field plate is fabricated for hot carrier injection improvement, significant decrease in the specified on resistance degradation is observed without substantially affecting the breakdown voltage of devices. Charge pumping method and simulation are carried out to study the degradation mechanism. Our results clearly show that the application of contact field plate can improve the device robustness in terms of hot carrier injection.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127394181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988899
Weifeng Sun, Jing Zhu, Zhuo Yang, F. Bian, Xin Tong, Ye Tian, Y. Yi, Yan Gu, Sen Zhang, Wei Su
A composite device structure on Silicon-On-Insulator (SOI) layer named Self-adjust Conductivity Modulation SOI-LIGBT (SCM-LIGBT) is proposed. It can be divided into three parts: the normal LIGBT region (NLT structure), the EM-NMOS region (ENM structure) and the diode region (DIO structure). The drain of the ENM structure is connected with the n+ emitter of the NLT structure while the p+ region in the emitter side of the NLT structure is connected to the anode of the DIO structure. The gates of the NLT structure and the ENM structure are connected together and they acted as the gate of the proposed SCM-LIGBT structure. In the on-state, the NPN parasitic bipolar structure of the NLT structure is triggered and the conductivity modulation is dramatically enhanced, which leads to the reduction on the on-state voltage. In addition, due to the base voltage of the NPN parasitic bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe-operating-area (FBSOA). The experiments demonstrate that the proposed SCM-LIGBT achieves the Vf lower than 1.18V at JA=150A/cm2.
{"title":"A composite structure named self-adjusted conductivity modulation SOI-LIGBT with low on-state voltage","authors":"Weifeng Sun, Jing Zhu, Zhuo Yang, F. Bian, Xin Tong, Ye Tian, Y. Yi, Yan Gu, Sen Zhang, Wei Su","doi":"10.23919/ISPSD.2017.7988899","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988899","url":null,"abstract":"A composite device structure on Silicon-On-Insulator (SOI) layer named Self-adjust Conductivity Modulation SOI-LIGBT (SCM-LIGBT) is proposed. It can be divided into three parts: the normal LIGBT region (NLT structure), the EM-NMOS region (ENM structure) and the diode region (DIO structure). The drain of the ENM structure is connected with the n+ emitter of the NLT structure while the p+ region in the emitter side of the NLT structure is connected to the anode of the DIO structure. The gates of the NLT structure and the ENM structure are connected together and they acted as the gate of the proposed SCM-LIGBT structure. In the on-state, the NPN parasitic bipolar structure of the NLT structure is triggered and the conductivity modulation is dramatically enhanced, which leads to the reduction on the on-state voltage. In addition, due to the base voltage of the NPN parasitic bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe-operating-area (FBSOA). The experiments demonstrate that the proposed SCM-LIGBT achieves the Vf lower than 1.18V at JA=150A/cm2.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988893
Masahiro Tanaka, A. Nakagawa
It was experimentally found that the short-circuit withstand capability of very narrow mesa IGBTs is degraded because of CIBL. In this paper, we report, for the first time, that conductivity modulation in the channel inversion layer of narrow mesa IGBT is the cause of CIBL. It is shown that the combination of the conductivity modulation and avalanche generation due to MOSFET-Mode operation causes short-circuit failure. We also propose a new cell design principle of narrow mesa IGBTs for low on-state voltage drop and good short-circuit withstand capability.
{"title":"Conductivity modulation in the channel inversion layer of very narrow mesa IGBT","authors":"Masahiro Tanaka, A. Nakagawa","doi":"10.23919/ISPSD.2017.7988893","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988893","url":null,"abstract":"It was experimentally found that the short-circuit withstand capability of very narrow mesa IGBTs is degraded because of CIBL. In this paper, we report, for the first time, that conductivity modulation in the channel inversion layer of narrow mesa IGBT is the cause of CIBL. It is shown that the combination of the conductivity modulation and avalanche generation due to MOSFET-Mode operation causes short-circuit failure. We also propose a new cell design principle of narrow mesa IGBTs for low on-state voltage drop and good short-circuit withstand capability.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133963488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988939
Riteshkumar Bhojani, J. Lutz, R. Baburske, H. Schulze, F.-J. Niedemostheide
In this work, we introduce a new collector IGBT structure that shows a huge improvement of the short-circuit (SC) ruggedness without deteriorating the static and dynamic losses of the device. The Injection Enhanced Floating Emitter (IEFE) concept enhances the emitter efficiency at the collector side by means of higher hole current injection which increases the bipolar current gain of the IGBT device. The simulation results indicate that the proposed structure can suppress a SC turn-off failure due to an electrical current crowding to a considerable extent. The critical pulse width to avoid thermal runaway of the leakage current after the SC event can be increased.
{"title":"A novel Injection Enhanced Floating Emitter (IEFE) IGBT structure improving the ruggedness against short-circuit and thermal destruction","authors":"Riteshkumar Bhojani, J. Lutz, R. Baburske, H. Schulze, F.-J. Niedemostheide","doi":"10.23919/ISPSD.2017.7988939","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988939","url":null,"abstract":"In this work, we introduce a new collector IGBT structure that shows a huge improvement of the short-circuit (SC) ruggedness without deteriorating the static and dynamic losses of the device. The Injection Enhanced Floating Emitter (IEFE) concept enhances the emitter efficiency at the collector side by means of higher hole current injection which increases the bipolar current gain of the IGBT device. The simulation results indicate that the proposed structure can suppress a SC turn-off failure due to an electrical current crowding to a considerable extent. The critical pulse width to avoid thermal runaway of the leakage current after the SC event can be increased.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988880
Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku
A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.
{"title":"A new ESD self-protection structure for 700V high side gate drive IC","authors":"Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku","doi":"10.23919/ISPSD.2017.7988880","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988880","url":null,"abstract":"A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"647 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116091017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988987
M. Sometani, Y. Iwahashi, M. Okamoto, S. Harada, Y. Yonezawa, H. Okumura, H. Yano
In this study, we constructed a novel measurement setup with a large current rating to measure fast Id change, and evaluated the decrease in Id due to positive AC gate bias, using commercially available SiC MOSFETs. In addition, by comparing the obtained fast 7d change results with the threshold voltage (Vth) shift measured by a conventional DC gate stress test, we verified that the conventional DC stress test is not sufficient for accurate evaluation of the Vth shift.
{"title":"Evaluation of drain current decrease by AC gate bias stress in commercially available SiC MOSFETs","authors":"M. Sometani, Y. Iwahashi, M. Okamoto, S. Harada, Y. Yonezawa, H. Okumura, H. Yano","doi":"10.23919/ISPSD.2017.7988987","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988987","url":null,"abstract":"In this study, we constructed a novel measurement setup with a large current rating to measure fast Id change, and evaluated the decrease in Id due to positive AC gate bias, using commercially available SiC MOSFETs. In addition, by comparing the obtained fast 7d change results with the threshold voltage (Vth) shift measured by a conventional DC gate stress test, we verified that the conventional DC stress test is not sufficient for accurate evaluation of the Vth shift.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988970
M. Tsukuda, Daisuke Yuki, H. Tomonaga, Hyoungseop Kim, I. Omura
We developed a screening equipment for ceramic substrate level power module of IGBT. The equipment realizes a new screening test with current distribution. The equipment acquires magnetic field signals over bonding wires and finally classifies to normal/abnormal module automatically. We established statistics based normal/abnormal classification with image processing. It is expected to be applied for screening in a production line and analysis to prevent the failure of power modules.
{"title":"Current distribution based power module screening by new normal/abnormal classification method with image processing","authors":"M. Tsukuda, Daisuke Yuki, H. Tomonaga, Hyoungseop Kim, I. Omura","doi":"10.23919/ISPSD.2017.7988970","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988970","url":null,"abstract":"We developed a screening equipment for ceramic substrate level power module of IGBT. The equipment realizes a new screening test with current distribution. The equipment acquires magnetic field signals over bonding wires and finally classifies to normal/abnormal module automatically. We established statistics based normal/abnormal classification with image processing. It is expected to be applied for screening in a production line and analysis to prevent the failure of power modules.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122873591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988982
H. Kitai, Y. Hozumi, H. Shiomi, K. Fukuda, Masaki Furumai
In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (RonA) was estimated to be 169 mΩ·cm2. The blocking voltage (BVDSS) of 13.1 kV was obtained at 10 μA/cm2. Owing to a low electric field in the gate oxide (Eox), a threshold voltage (Vth) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.
本文研制了一种在结场效应晶体管(JFET)区域逆行掺杂的13kv SiC MOSFET，该MOSFET由多能态氮离子注入，用于x射线发生器和加速电压大于10kv的电子枪的电源。通过器件仿真对JFET区域进行优化，降低导通电阻。采用5 mm × 5 mm的晶片尺寸制备了具有优化JFET区域的SiC MOSFET。比导通电阻(RonA)估计为169 mΩ·cm2。在10 μA/cm2下获得了13.1 kV的阻断电压(BVDSS)。由于栅极氧化物(Eox)中的电场较低，在−15 V的栅极电压(等于−3 MV/cm的电场)和200℃下，在1000小时内实现了阈值电压(Vth)的±0.06 V的位移。在感应负载下的动态试验结果表明，在室温下，直流母线电压为10 kV时，关断和导通速度分别为75 kV/μs和114 kV/μs。
{"title":"Low on-resistance and fast switching of 13-kV SiC MOSFETs with optimized junction field-effect transistor region","authors":"H. Kitai, Y. Hozumi, H. Shiomi, K. Fukuda, Masaki Furumai","doi":"10.23919/ISPSD.2017.7988982","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988982","url":null,"abstract":"In this paper, a 13-kV SiC MOSFET with a retrograde doping profile in junction field-effect transistor (JFET) regions, which were implanted by nitrogen ions with multiple energies, has been developed for power supplies of X-ray generators and electron guns with an accelerating voltage greater than 10 kV. A JFET region was optimized with device simulation to reduce on-resistance. A SiC MOSFET with an optimized JFET region was fabricated with a 5 mm × 5 mm die size. The specific on-resistance (R<inf>onA</inf>) was estimated to be 169 mΩ·cm<sup>2</sup>. The blocking voltage (BV<inf>DSS</inf>) of 13.1 kV was obtained at 10 μA/cm<sup>2</sup>. Owing to a low electric field in the gate oxide (E<inf>ox</inf>), a threshold voltage (V<inf>th</inf>) shift within ± 0.06 V was achieved at the gate voltage of −15 V (equal to an electric field of −3 MV/cm) and 200 °C for 1000 hours. The dynamic test with inductive load resulted in turn-off and turn-on switching speeds of 75 kV/μs and 114 kV/μs, respectively, for the DC bus voltage of 10 kV at room temperature.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988949
Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang
A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (Iesd) path to improve the holding voltage (Vh) and failure current (It2). The relation between Vh and base-concentration (Nb) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing Vh by changing Nb. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the IESD distribution and Vh. The longer ESD current path improves the Vh by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the It2. DC and dynamic TLP simulation results show the Vh = 5.3 V of proposed SCR is achieved with a higher failure current (It2) of 1.68e-2A/μm.
{"title":"Investigation of a latch-up immune silicon controlled rectifier for robust ESD application","authors":"Zhao Qi, M. Qiao, Xin Zhou, Wen Yang, Dong Fang, Shikang Cheng, Sen Zhang, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988949","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988949","url":null,"abstract":"A latch-up immune robust SCR with an N+ top layer and an additional Nwell region (Nwell2) is proposed in this paper. The N+ top layer and Nwell2 divide the original SCR into three new SCRs with sharing emitter, which provide the deeper ESD current (I<inf>esd</inf>) path to improve the holding voltage (V<inf>h</inf>) and failure current (I<inf>t2</inf>). The relation between V<inf>h</inf> and base-concentration (N<inf>b</inf>) for LVTSCR is given to provide an in-depth insight into the mechanism for enhancing V<inf>h</inf> by changing N<inf>b</inf>. The N+ top layer and NWELL2 form three base regions (B1, B2 and B3) with different concentration to optimize the I<inf>ESD</inf> distribution and V<inf>h</inf>. The longer ESD current path improves the V<inf>h</inf> by reducing the current gain. The deeper current distribution makes the total temperature is endured by inner lattice instead of surface lattice, which improves the I<inf>t2</inf>. DC and dynamic TLP simulation results show the V<inf>h</inf> = 5.3 V of proposed SCR is achieved with a higher failure current (I<inf>t2</inf>) of 1.68e-2A/μm.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125253698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988955
A. Sakai, K. Eikyu, H. Fujii, T. Mori, Y. Akiyama, Y. Yamaguchi
This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without degrading typical figure of merits such as breakdown voltage BV and specific on-resistance Rsp. The superiority of a novel STI-based p-channel LDMOSFET with a hot electron cooling (HEC) layer against the conventional method to improve HC immunity (i.e. extending the p-drift length) is confirmed by TCAD simulation.
{"title":"Simple and efficient approach to improve hot carrier immunity of a p-LDMOSFET","authors":"A. Sakai, K. Eikyu, H. Fujii, T. Mori, Y. Akiyama, Y. Yamaguchi","doi":"10.23919/ISPSD.2017.7988955","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988955","url":null,"abstract":"This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without degrading typical figure of merits such as breakdown voltage BV and specific on-resistance Rsp. The superiority of a novel STI-based p-channel LDMOSFET with a hot electron cooling (HEC) layer against the conventional method to improve HC immunity (i.e. extending the p-drift length) is confirmed by TCAD simulation.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"34 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114154547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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