Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988957
Lin Wei, Cheng Chao, U. Singh, Ruchil Jain, Li Leng Goh, P. R. Verma
A new kind of field plate as contact field plate is fabricated for hot carrier injection improvement, significant decrease in the specified on resistance degradation is observed without substantially affecting the breakdown voltage of devices. Charge pumping method and simulation are carried out to study the degradation mechanism. Our results clearly show that the application of contact field plate can improve the device robustness in terms of hot carrier injection.
{"title":"A novel contact field plate application in drain-extended-MOSFET transistors","authors":"Lin Wei, Cheng Chao, U. Singh, Ruchil Jain, Li Leng Goh, P. R. Verma","doi":"10.23919/ISPSD.2017.7988957","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988957","url":null,"abstract":"A new kind of field plate as contact field plate is fabricated for hot carrier injection improvement, significant decrease in the specified on resistance degradation is observed without substantially affecting the breakdown voltage of devices. Charge pumping method and simulation are carried out to study the degradation mechanism. Our results clearly show that the application of contact field plate can improve the device robustness in terms of hot carrier injection.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127394181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988899
Weifeng Sun, Jing Zhu, Zhuo Yang, F. Bian, Xin Tong, Ye Tian, Y. Yi, Yan Gu, Sen Zhang, Wei Su
A composite device structure on Silicon-On-Insulator (SOI) layer named Self-adjust Conductivity Modulation SOI-LIGBT (SCM-LIGBT) is proposed. It can be divided into three parts: the normal LIGBT region (NLT structure), the EM-NMOS region (ENM structure) and the diode region (DIO structure). The drain of the ENM structure is connected with the n+ emitter of the NLT structure while the p+ region in the emitter side of the NLT structure is connected to the anode of the DIO structure. The gates of the NLT structure and the ENM structure are connected together and they acted as the gate of the proposed SCM-LIGBT structure. In the on-state, the NPN parasitic bipolar structure of the NLT structure is triggered and the conductivity modulation is dramatically enhanced, which leads to the reduction on the on-state voltage. In addition, due to the base voltage of the NPN parasitic bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe-operating-area (FBSOA). The experiments demonstrate that the proposed SCM-LIGBT achieves the Vf lower than 1.18V at JA=150A/cm2.
{"title":"A composite structure named self-adjusted conductivity modulation SOI-LIGBT with low on-state voltage","authors":"Weifeng Sun, Jing Zhu, Zhuo Yang, F. Bian, Xin Tong, Ye Tian, Y. Yi, Yan Gu, Sen Zhang, Wei Su","doi":"10.23919/ISPSD.2017.7988899","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988899","url":null,"abstract":"A composite device structure on Silicon-On-Insulator (SOI) layer named Self-adjust Conductivity Modulation SOI-LIGBT (SCM-LIGBT) is proposed. It can be divided into three parts: the normal LIGBT region (NLT structure), the EM-NMOS region (ENM structure) and the diode region (DIO structure). The drain of the ENM structure is connected with the n+ emitter of the NLT structure while the p+ region in the emitter side of the NLT structure is connected to the anode of the DIO structure. The gates of the NLT structure and the ENM structure are connected together and they acted as the gate of the proposed SCM-LIGBT structure. In the on-state, the NPN parasitic bipolar structure of the NLT structure is triggered and the conductivity modulation is dramatically enhanced, which leads to the reduction on the on-state voltage. In addition, due to the base voltage of the NPN parasitic bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe-operating-area (FBSOA). The experiments demonstrate that the proposed SCM-LIGBT achieves the Vf lower than 1.18V at JA=150A/cm2.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988893
Masahiro Tanaka, A. Nakagawa
It was experimentally found that the short-circuit withstand capability of very narrow mesa IGBTs is degraded because of CIBL. In this paper, we report, for the first time, that conductivity modulation in the channel inversion layer of narrow mesa IGBT is the cause of CIBL. It is shown that the combination of the conductivity modulation and avalanche generation due to MOSFET-Mode operation causes short-circuit failure. We also propose a new cell design principle of narrow mesa IGBTs for low on-state voltage drop and good short-circuit withstand capability.
{"title":"Conductivity modulation in the channel inversion layer of very narrow mesa IGBT","authors":"Masahiro Tanaka, A. Nakagawa","doi":"10.23919/ISPSD.2017.7988893","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988893","url":null,"abstract":"It was experimentally found that the short-circuit withstand capability of very narrow mesa IGBTs is degraded because of CIBL. In this paper, we report, for the first time, that conductivity modulation in the channel inversion layer of narrow mesa IGBT is the cause of CIBL. It is shown that the combination of the conductivity modulation and avalanche generation due to MOSFET-Mode operation causes short-circuit failure. We also propose a new cell design principle of narrow mesa IGBTs for low on-state voltage drop and good short-circuit withstand capability.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133963488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988939
Riteshkumar Bhojani, J. Lutz, R. Baburske, H. Schulze, F.-J. Niedemostheide
In this work, we introduce a new collector IGBT structure that shows a huge improvement of the short-circuit (SC) ruggedness without deteriorating the static and dynamic losses of the device. The Injection Enhanced Floating Emitter (IEFE) concept enhances the emitter efficiency at the collector side by means of higher hole current injection which increases the bipolar current gain of the IGBT device. The simulation results indicate that the proposed structure can suppress a SC turn-off failure due to an electrical current crowding to a considerable extent. The critical pulse width to avoid thermal runaway of the leakage current after the SC event can be increased.
{"title":"A novel Injection Enhanced Floating Emitter (IEFE) IGBT structure improving the ruggedness against short-circuit and thermal destruction","authors":"Riteshkumar Bhojani, J. Lutz, R. Baburske, H. Schulze, F.-J. Niedemostheide","doi":"10.23919/ISPSD.2017.7988939","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988939","url":null,"abstract":"In this work, we introduce a new collector IGBT structure that shows a huge improvement of the short-circuit (SC) ruggedness without deteriorating the static and dynamic losses of the device. The Injection Enhanced Floating Emitter (IEFE) concept enhances the emitter efficiency at the collector side by means of higher hole current injection which increases the bipolar current gain of the IGBT device. The simulation results indicate that the proposed structure can suppress a SC turn-off failure due to an electrical current crowding to a considerable extent. The critical pulse width to avoid thermal runaway of the leakage current after the SC event can be increased.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124151955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988978
J. Driesen
This paper discusses the technology trends behind the energy transition happening in the energy system of modern cities, linked to electrification, decentralization and digitalization. The role of power electronics, with a focus on building-level technologies, and the derived future requirements for converters and components are discussed. It is demonstrated using relevant use cases that power electronics represents “the new blocks that keep the building upright”.
{"title":"Power electronics as the enabling technology for sustainable energy in the smart city","authors":"J. Driesen","doi":"10.23919/ISPSD.2017.7988978","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988978","url":null,"abstract":"This paper discusses the technology trends behind the energy transition happening in the energy system of modern cities, linked to electrification, decentralization and digitalization. The role of power electronics, with a focus on building-level technologies, and the derived future requirements for converters and components are discussed. It is demonstrated using relevant use cases that power electronics represents “the new blocks that keep the building upright”.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124586905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Short circuit capability of a 1200V SiC MOSFET and a 1200V Si IGBT is compared and analyzed in this work, and the channel mobility in the SiC MOSFET over a broad temperature range from room temperature up to 2000 °C has been extracted for the first time. Experimental results show that SiC MOSFET exhibits shorter short circuit withstand time (SCWT) compared to Si IGBT. 1-D transient finite element thermal models of SiC MOSFETs and Si IGBTs have been implemented to simulate the dynamic temperature profiles in devices during short circuit tests. The junction temperature of SiC MOSFET rises much faster than that of Si IGBT and the heat spreading thickness of SiC MOSFET is much narrower, leading to shorter SCWT of the SiC MOSFET. Combining the experimental and thermal simulation results, the temperature-dependent saturation drain current in SiC MOSFETs is extracted. Based on this, the channel mobility over a wide temperature range is obtained.
本文对1200V SiC MOSFET和1200V Si IGBT的短路性能进行了比较和分析，并首次提取了SiC MOSFET在室温至2000°C的宽温度范围内的沟道迁移率。实验结果表明，SiC MOSFET比Si IGBT具有更短的耐短路时间(SCWT)。建立了SiC mosfet和Si igbt的一维瞬态有限元热模型，用于模拟器件在短路测试过程中的动态温度分布。SiC MOSFET的结温上升速度比Si IGBT快得多，且SiC MOSFET的散热厚度窄得多，导致SiC MOSFET的SCWT较短。结合实验和热仿真结果，提取了SiC mosfet中温度相关的饱和漏极电流。在此基础上，获得了宽温度范围内的通道迁移率。
{"title":"Short circuit capability and high temperature channel mobility of SiC MOSFETs","authors":"Jiahui Sun, Hongyi Xu, Xinke Wu, Shu Yang, Qing Guo, Kuang Sheng","doi":"10.23919/ISPSD.2017.7988988","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988988","url":null,"abstract":"Short circuit capability of a 1200V SiC MOSFET and a 1200V Si IGBT is compared and analyzed in this work, and the channel mobility in the SiC MOSFET over a broad temperature range from room temperature up to 2000 °C has been extracted for the first time. Experimental results show that SiC MOSFET exhibits shorter short circuit withstand time (SCWT) compared to Si IGBT. 1-D transient finite element thermal models of SiC MOSFETs and Si IGBTs have been implemented to simulate the dynamic temperature profiles in devices during short circuit tests. The junction temperature of SiC MOSFET rises much faster than that of Si IGBT and the heat spreading thickness of SiC MOSFET is much narrower, leading to shorter SCWT of the SiC MOSFET. Combining the experimental and thermal simulation results, the temperature-dependent saturation drain current in SiC MOSFETs is extracted. Based on this, the channel mobility over a wide temperature range is obtained.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988880
Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku
A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.
{"title":"A new ESD self-protection structure for 700V high side gate drive IC","authors":"Sunglyong Kim, D. LaFonteese, Danyang Zhu, D. Sridhar, S. Pendharkar, Hiromi Endoh, K. Boku","doi":"10.23919/ISPSD.2017.7988880","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988880","url":null,"abstract":"A new concept to realize self-protected ESD structure for 700V high side gate drive IC without additional process steps and area penalty is presented. The device was verified by simulation and confirmed by experimental results. A parasitic NPN structure integrated in high voltage level shifter LDMOS enables LDMOS to be operated within safe operating area when ESD strikes the high side driver part with respect to the low voltage controller by triggering snapback right after breakdown. The new ESD self-protected LDMOS and high voltage junction termination structure in conjunction with parasitic NPN showed remarkable improvement in HBM ESD level from 1.4kV to 6.8kV.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"647 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116091017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988987
M. Sometani, Y. Iwahashi, M. Okamoto, S. Harada, Y. Yonezawa, H. Okumura, H. Yano
In this study, we constructed a novel measurement setup with a large current rating to measure fast Id change, and evaluated the decrease in Id due to positive AC gate bias, using commercially available SiC MOSFETs. In addition, by comparing the obtained fast 7d change results with the threshold voltage (Vth) shift measured by a conventional DC gate stress test, we verified that the conventional DC stress test is not sufficient for accurate evaluation of the Vth shift.
{"title":"Evaluation of drain current decrease by AC gate bias stress in commercially available SiC MOSFETs","authors":"M. Sometani, Y. Iwahashi, M. Okamoto, S. Harada, Y. Yonezawa, H. Okumura, H. Yano","doi":"10.23919/ISPSD.2017.7988987","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988987","url":null,"abstract":"In this study, we constructed a novel measurement setup with a large current rating to measure fast Id change, and evaluated the decrease in Id due to positive AC gate bias, using commercially available SiC MOSFETs. In addition, by comparing the obtained fast 7d change results with the threshold voltage (Vth) shift measured by a conventional DC gate stress test, we verified that the conventional DC stress test is not sufficient for accurate evaluation of the Vth shift.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122465805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988909
I. Kasko, S. Berberich, M. Gross, P. Beckedahl, S. Buetow
A holistic approach taking benefit from optimization of chip, assembly technology and module design was utilized to exploit the performance potential of SiC power modules. A novel MOSFET SiC module (1200V, 400A) with extremely low inductance (1.4nH) was designed and assembled using Semikron DPD (Direct Pressed Die) technology. The electrical measurements showed excellent switching performance (switching speed up to ∼53kV/μs for dv/dt and ∼67kA/μs for di/dt) and very low energy losses (80% lower than state of the art Si based IGBT module). The enhanced reliability was demonstrated by power cycling tests (8–10x life time improvement compared to conventional assembly of SiC devices).
{"title":"High efficient approach to utilize SiC MOSFET potential in power modules","authors":"I. Kasko, S. Berberich, M. Gross, P. Beckedahl, S. Buetow","doi":"10.23919/ISPSD.2017.7988909","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988909","url":null,"abstract":"A holistic approach taking benefit from optimization of chip, assembly technology and module design was utilized to exploit the performance potential of SiC power modules. A novel MOSFET SiC module (1200V, 400A) with extremely low inductance (1.4nH) was designed and assembled using Semikron DPD (Direct Pressed Die) technology. The electrical measurements showed excellent switching performance (switching speed up to ∼53kV/μs for dv/dt and ∼67kA/μs for di/dt) and very low energy losses (80% lower than state of the art Si based IGBT module). The enhanced reliability was demonstrated by power cycling tests (8–10x life time improvement compared to conventional assembly of SiC devices).","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988970
M. Tsukuda, Daisuke Yuki, H. Tomonaga, Hyoungseop Kim, I. Omura
We developed a screening equipment for ceramic substrate level power module of IGBT. The equipment realizes a new screening test with current distribution. The equipment acquires magnetic field signals over bonding wires and finally classifies to normal/abnormal module automatically. We established statistics based normal/abnormal classification with image processing. It is expected to be applied for screening in a production line and analysis to prevent the failure of power modules.
{"title":"Current distribution based power module screening by new normal/abnormal classification method with image processing","authors":"M. Tsukuda, Daisuke Yuki, H. Tomonaga, Hyoungseop Kim, I. Omura","doi":"10.23919/ISPSD.2017.7988970","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988970","url":null,"abstract":"We developed a screening equipment for ceramic substrate level power module of IGBT. The equipment realizes a new screening test with current distribution. The equipment acquires magnetic field signals over bonding wires and finally classifies to normal/abnormal module automatically. We established statistics based normal/abnormal classification with image processing. It is expected to be applied for screening in a production line and analysis to prevent the failure of power modules.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122873591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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