Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988979
K. Yasuda
While the future of the world economy is uncertain, the robotic market is steadily growing. This growth is not only quantitatively expansive in the robotic market, but there is growth in related technological markets, such as networking. In this paper, I discuss the current trends in the robotic market and current problems that are being considered. Then I discuss how Yaskawa Electric is dealing with these problems.
{"title":"The future vision of industrial robot","authors":"K. Yasuda","doi":"10.23919/ISPSD.2017.7988979","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988979","url":null,"abstract":"While the future of the world economy is uncertain, the robotic market is steadily growing. This growth is not only quantitatively expansive in the robotic market, but there is growth in related technological markets, such as networking. In this paper, I discuss the current trends in the robotic market and current problems that are being considered. Then I discuss how Yaskawa Electric is dealing with these problems.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121653075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988894
M. Sawada, Y. Sakurai, K. Ohi, Y. Ikura, Y. Onozawa, T. Yamazaki, Y. Nabetani
This paper presents the “Hole Path Concept” in trench gate IGBTs in order to have extended performance in faster switching with balance low switching loss and low ElectroMagnetic Interference (EMI) noise. The hole path IGET which is utilized narrow hole extraction regions in floating p-region can realize a better turn-on di/dt controllability with high IE effect.
{"title":"Hole path concept for low switching loss and low EMI noise with high IE-effect","authors":"M. Sawada, Y. Sakurai, K. Ohi, Y. Ikura, Y. Onozawa, T. Yamazaki, Y. Nabetani","doi":"10.23919/ISPSD.2017.7988894","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988894","url":null,"abstract":"This paper presents the “Hole Path Concept” in trench gate IGBTs in order to have extended performance in faster switching with balance low switching loss and low ElectroMagnetic Interference (EMI) noise. The hole path IGET which is utilized narrow hole extraction regions in floating p-region can realize a better turn-on di/dt controllability with high IE effect.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122645007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988954
Shikang Cheng, Dong Fang, M. Qiao, Sen Zhang, Guangsheng Zhang, Yan Gu, Yitao He, Xin Zhou, Zhao Qi, Zhaoji Li, Bo Zhang
A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the Ron, sp is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with Ron, sp of 96.2 mΩ·cm2 and BV of 758 V is experimentally achieved, which breaks the conventional Ron, sp-BV silicon limit of double RESURF technology.
{"title":"A novel 700V deep trench isolated double RESURF LDMOS with P-sink layer","authors":"Shikang Cheng, Dong Fang, M. Qiao, Sen Zhang, Guangsheng Zhang, Yan Gu, Yitao He, Xin Zhou, Zhao Qi, Zhaoji Li, Bo Zhang","doi":"10.23919/ISPSD.2017.7988954","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988954","url":null,"abstract":"A novel DTI double RESURF LDMOS with P-sink layer is presented and experimentally demonstrated in this paper. The novel structure features a P-sink layer around the bottom of deep trench, which is formed with the Deep N-type Well (DNW) after the process of high temperature driving in. The highly doped P-sink layer restrains the extension of depletion region along the horizontal direction, improving the isolation performance. According to the simulation results, the surface electric field peak of the proposed DTI LDMOS is reduced by 35 % due to the enhanced depletion effect of P-sink layer. Meanwhile, the concentration of DNW and P-top region are increased, thus the Ron, sp is decreased. Furthermore, the isolation region area is reduced significantly so that the chip size will be minimized. The LDMOS with Ron, sp of 96.2 mΩ·cm2 and BV of 758 V is experimentally achieved, which breaks the conventional Ron, sp-BV silicon limit of double RESURF technology.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122748309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988875
M. Takamiya, K. Miyazaki, H. Obara, T. Sai, K. Wada, T. Sakurai
The emerging trend of internet of things (IoT) and artificial intelligence (AI) technologies will bring about a major change in power electronics and create a new generation of the power electronics (Power Electronics 2.0). To enable the IoT- and Al-assisted Power Electronics 2.0, the integration of the sensors, the programmable hardware, and VLSIs for the controller into the power devices/modules is very important. In this paper, a 6-bit programmable gate driver IC with automatic optimization of gate driving waveform for IGBT is presented as the first step toward Power Electronics 2.0. In the proposed gate driver, the 6-bit gate control signals with four 160-ns time steps are globally optimized using a simulated annealing algorithm, reducing the collector current overshoot by 37% and the switching loss by 47% at the double pulse test of 300V, 50A IGBT. The gate driver is also applied to a half-bridge inverter, where the gate driving waveform is changed depending on the load current.
{"title":"Power electronics 2.0: IoT-connected and Al-controlled power electronics operating optimally for each user","authors":"M. Takamiya, K. Miyazaki, H. Obara, T. Sai, K. Wada, T. Sakurai","doi":"10.23919/ISPSD.2017.7988875","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988875","url":null,"abstract":"The emerging trend of internet of things (IoT) and artificial intelligence (AI) technologies will bring about a major change in power electronics and create a new generation of the power electronics (Power Electronics 2.0). To enable the IoT- and Al-assisted Power Electronics 2.0, the integration of the sensors, the programmable hardware, and VLSIs for the controller into the power devices/modules is very important. In this paper, a 6-bit programmable gate driver IC with automatic optimization of gate driving waveform for IGBT is presented as the first step toward Power Electronics 2.0. In the proposed gate driver, the 6-bit gate control signals with four 160-ns time steps are globally optimized using a simulated annealing algorithm, reducing the collector current overshoot by 37% and the switching loss by 47% at the double pulse test of 300V, 50A IGBT. The gate driver is also applied to a half-bridge inverter, where the gate driving waveform is changed depending on the load current.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121629185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988973
S. Buetow, R. Herzer, Gunter Koenigsmann, M. Rossberg, A. Maul
The paper presents the benefit of an optimized gate drive which can be achieved with a new generation of very low inductive 1200V, 400A SiC-MOSFET half bridge module and a new and adapted gate driver. After presenting the influence of the dead time to the static and dynamic losses of SiC-MOSFET and internal body diode a calculation of the possible output current versus frequency is performed. Finally the results are verified by calorimetrie measurements in a real inverter application.
{"title":"High power, high frequency SiC-MOSFET system with outstanding performance, power density and reliability","authors":"S. Buetow, R. Herzer, Gunter Koenigsmann, M. Rossberg, A. Maul","doi":"10.23919/ISPSD.2017.7988973","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988973","url":null,"abstract":"The paper presents the benefit of an optimized gate drive which can be achieved with a new generation of very low inductive 1200V, 400A SiC-MOSFET half bridge module and a new and adapted gate driver. After presenting the influence of the dead time to the static and dynamic losses of SiC-MOSFET and internal body diode a calculation of the possible output current versus frequency is performed. Finally the results are verified by calorimetrie measurements in a real inverter application.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124805375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988911
S. Tabata, K. Hasegawa, M. Tsukuda, I. Omura
This paper proposes a new power module concept that integrates output current measurement function to make inverters compact. The current measurement function is realized by tiny printed-circuit-board (PCB) Rogowski coils. The PCB Rogowski coil picks up a switching current flowing through an IGBT chip, and then a combination of a digital circuit based on a field-programmable-gate-array (FPGA) and an integrator circuit reproduces the output current of the inverter from the switching current. A major concern of the new power module is the effect of reverse recovery current of free-wheeling diodes because the reverse recovery current is superimposed on the switching current. This paper proposes a mitigating method of the reverse recovery current.
{"title":"New power module integrating output current measurement function","authors":"S. Tabata, K. Hasegawa, M. Tsukuda, I. Omura","doi":"10.23919/ISPSD.2017.7988911","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988911","url":null,"abstract":"This paper proposes a new power module concept that integrates output current measurement function to make inverters compact. The current measurement function is realized by tiny printed-circuit-board (PCB) Rogowski coils. The PCB Rogowski coil picks up a switching current flowing through an IGBT chip, and then a combination of a digital circuit based on a field-programmable-gate-array (FPGA) and an integrator circuit reproduces the output current of the inverter from the switching current. A major concern of the new power module is the effect of reverse recovery current of free-wheeling diodes because the reverse recovery current is superimposed on the switching current. This paper proposes a mitigating method of the reverse recovery current.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129416261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988898
M. Mudholkar, M. Quddus, Yohai Kalderon, M. Thomason, A. Salih
A design methodology to optimize the drift region doping properties in trench Schottky rectifiers has been presented. Advanced lithography is being used for trench devices that are designed for smaller die sizes in wireless applications. Such devices feature narrow active trenches to maximize active area utilization in combination with a wide termination trench to support the breakdown voltage. Such different trench aspect ratios create a depth mismatch, if they are formed in a single etch step. It has been shown that designing the drift region while accounting for the trench depth difference is vital to properly optimize the device electrical parameters. A new trench architecture has also been proposed which features alternating deeper active trenches. The new trench architecture is shown to have the best performance trade-off at the cost of one additional mask step.
{"title":"Trench schottky rectifiers with non-uniform trench depths","authors":"M. Mudholkar, M. Quddus, Yohai Kalderon, M. Thomason, A. Salih","doi":"10.23919/ISPSD.2017.7988898","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988898","url":null,"abstract":"A design methodology to optimize the drift region doping properties in trench Schottky rectifiers has been presented. Advanced lithography is being used for trench devices that are designed for smaller die sizes in wireless applications. Such devices feature narrow active trenches to maximize active area utilization in combination with a wide termination trench to support the breakdown voltage. Such different trench aspect ratios create a depth mismatch, if they are formed in a single etch step. It has been shown that designing the drift region while accounting for the trench depth difference is vital to properly optimize the device electrical parameters. A new trench architecture has also been proposed which features alternating deeper active trenches. The new trench architecture is shown to have the best performance trade-off at the cost of one additional mask step.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129434164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988906
T. Hosoi, Shuji Azumo, Y. Kashiwagi, S. Hosaka, Kenji Yamamoto, M. Aketa, H. Asahara, Takashi Nakamura, T. Kimoto, T. Shimura, Heiji Watanabe
Advanced metal/high-k gate stack technology for SiC-based power MOSFET was demonstrated. We found that the Hf incorporation into aluminum oxynitride (HfAlON gate insulator) combined with TIN electrode effectively improves the stability of threshold voltage under both negative and positive bias temperature stresses. Since the relative permittivity of HfAlON increases with increasing Hf content, peak transconductance enhancement up to 3.4 times with acceptable reliability margin was achieved in the state-of-the-art trench MOSFET by implementing TiN/HfA10N(Hf50%) gate stack.
{"title":"Reliability-aware design of metal/high-k gate stack for high-performance SiC power MOSFET","authors":"T. Hosoi, Shuji Azumo, Y. Kashiwagi, S. Hosaka, Kenji Yamamoto, M. Aketa, H. Asahara, Takashi Nakamura, T. Kimoto, T. Shimura, Heiji Watanabe","doi":"10.23919/ISPSD.2017.7988906","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988906","url":null,"abstract":"Advanced metal/high-k gate stack technology for SiC-based power MOSFET was demonstrated. We found that the Hf incorporation into aluminum oxynitride (HfAlON gate insulator) combined with TIN electrode effectively improves the stability of threshold voltage under both negative and positive bias temperature stresses. Since the relative permittivity of HfAlON increases with increasing Hf content, peak transconductance enhancement up to 3.4 times with acceptable reliability margin was achieved in the state-of-the-art trench MOSFET by implementing TiN/HfA10N(Hf50%) gate stack.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127517722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988891
A. Mihaila, E. Bianda, L. Knoll, U. Vemulapati, L. Kranz, G. Alfieri, V. Soler, P. Godignon, C. Papadopoulos, Munaf T. A. Rahimo
This paper presents an experimental investigation of the dynamic performance of SiC 6.5kV JBS diodes. Using a hybrid Si SPT IGBT/SiC JBS diodes combination, we have analyzed the turn-off behavior limits of SiC JBS diodes and compared the result against a state-of-the-art Si PiN diode. The experimental results show that the JBS diodes can handle about 40A/chip at 125°C before going into thermal runaway. This maximum turn-off current value increases by about 50% when the diodes are operated at room temperature. The diodes dI/dt behaviour appear to be virtually independent of the DC-link voltage (at RG=18Ω). The comparison between turn-off curves for 6.5kV SiC and Si diodes shows that the use of SiC JBS diodes reduces the reverse recovery losses by more than 98%.
{"title":"Experimental investigation of SiC 6.5kV JBS diodes safe operating area","authors":"A. Mihaila, E. Bianda, L. Knoll, U. Vemulapati, L. Kranz, G. Alfieri, V. Soler, P. Godignon, C. Papadopoulos, Munaf T. A. Rahimo","doi":"10.23919/ISPSD.2017.7988891","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988891","url":null,"abstract":"This paper presents an experimental investigation of the dynamic performance of SiC 6.5kV JBS diodes. Using a hybrid Si SPT IGBT/SiC JBS diodes combination, we have analyzed the turn-off behavior limits of SiC JBS diodes and compared the result against a state-of-the-art Si PiN diode. The experimental results show that the JBS diodes can handle about 40A/chip at 125°C before going into thermal runaway. This maximum turn-off current value increases by about 50% when the diodes are operated at room temperature. The diodes dI/dt behaviour appear to be virtually independent of the DC-link voltage (at RG=18Ω). The comparison between turn-off curves for 6.5kV SiC and Si diodes shows that the use of SiC JBS diodes reduces the reverse recovery losses by more than 98%.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126502706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.23919/ISPSD.2017.7988932
I. Deviny, H. Luo, Q. Xiao, Yao Yao, Chunlin Zhu, L. Ngwendson, Haibo Xiao, X. Dai, Guoyou Liu
In this paper, a novel 1700V recessed emitter trench IGBT (RET-IGBT) is proposed. The RET-IGBT features an additional recessed trench between two adjacent active trenches and under the emitter contact, which reduces the drawn trench to trench separation from 6μm to 2μm. Combined with a double-dose carrier storage (CS) layers, the injection enhancement effect is enhanced. As a result, the trade-off relationship between Vce(on) and £off is improved. The fabricated RET-IGBT shows record low Vce(on) of 1.65V at 150A(110A/cm−2), no degradation in breakdown voltage and short circuit performances whilst enhancing the current handling capability in spite of increased current density.
{"title":"A novel 1700V RET-IGBT (recessed emitter trench IGBT) shows record low VCE(ON), enhanced current handling capability and short circuit robustness","authors":"I. Deviny, H. Luo, Q. Xiao, Yao Yao, Chunlin Zhu, L. Ngwendson, Haibo Xiao, X. Dai, Guoyou Liu","doi":"10.23919/ISPSD.2017.7988932","DOIUrl":"https://doi.org/10.23919/ISPSD.2017.7988932","url":null,"abstract":"In this paper, a novel 1700V recessed emitter trench IGBT (RET-IGBT) is proposed. The RET-IGBT features an additional recessed trench between two adjacent active trenches and under the emitter contact, which reduces the drawn trench to trench separation from 6μm to 2μm. Combined with a double-dose carrier storage (CS) layers, the injection enhancement effect is enhanced. As a result, the trade-off relationship between Vce(on) and £off is improved. The fabricated RET-IGBT shows record low Vce(on) of 1.65V at 150A(110A/cm−2), no degradation in breakdown voltage and short circuit performances whilst enhancing the current handling capability in spite of increased current density.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125823317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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