Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010219
F. Borghetti, A. Esposito, U. Gatti, P. Malcovati, F. Maloberti
In this paper we present a resonator circuit suitable for the implementation of high speed switched-capacitor n-path bandpass /spl Sigma//spl Delta/ modulators. The resonator, implemented using a 0.8 /spl mu/m SiGe BiCMOS process (f/sub T/=35 GHz), exploits switched buffers realized using bipolar transistors to emulate the CMOS switches behavior at much higher speed. The circuit has a resonance frequency of 77.5 MHz and operates at a clock frequency of 160 MHz, consuming 120 mA from a 5 V power supply. Moreover, simulations have confirmed that with the proposed technique clock frequencies up to 200 MHz can be used without significant degradation of the performance.
{"title":"BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulator","authors":"F. Borghetti, A. Esposito, U. Gatti, P. Malcovati, F. Maloberti","doi":"10.1109/ISCAS.2002.1010219","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010219","url":null,"abstract":"In this paper we present a resonator circuit suitable for the implementation of high speed switched-capacitor n-path bandpass /spl Sigma//spl Delta/ modulators. The resonator, implemented using a 0.8 /spl mu/m SiGe BiCMOS process (f/sub T/=35 GHz), exploits switched buffers realized using bipolar transistors to emulate the CMOS switches behavior at much higher speed. The circuit has a resonance frequency of 77.5 MHz and operates at a clock frequency of 160 MHz, consuming 120 mA from a 5 V power supply. Moreover, simulations have confirmed that with the proposed technique clock frequencies up to 200 MHz can be used without significant degradation of the performance.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010542
K. Moolpho, J. Ngarmnil, K. Nandhasri
This paper proposes a new current amplifier circuit totally formed in the class AB structure utilizing CMOS inverters and the recently proposed additive analog inverter using floating-gate MOSFETs. Operating in a negative feedback topology, the amplifier can deal with wide signal swings up to /spl plusmn/200 /spl mu/A, with 1% of the THD and 10 pF of C/sub L/. Designs and HSPICE simulation results are demonstrated on 0.5 /spl mu/m double poly CMOS processes with 1.5 V and 1 V power supplies to indicate high frequency and low power capabilities respectively.
{"title":"A low-voltage wide-swing FGMOS current amplifier","authors":"K. Moolpho, J. Ngarmnil, K. Nandhasri","doi":"10.1109/ISCAS.2002.1010542","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010542","url":null,"abstract":"This paper proposes a new current amplifier circuit totally formed in the class AB structure utilizing CMOS inverters and the recently proposed additive analog inverter using floating-gate MOSFETs. Operating in a negative feedback topology, the amplifier can deal with wide signal swings up to /spl plusmn/200 /spl mu/A, with 1% of the THD and 10 pF of C/sub L/. Designs and HSPICE simulation results are demonstrated on 0.5 /spl mu/m double poly CMOS processes with 1.5 V and 1 V power supplies to indicate high frequency and low power capabilities respectively.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130904192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010217
N. A. Fraser, B. Nowrouzian
Concerns the development of a novel technique for the determination of the moments of the quantizer input signal for /spl Sigma/-/spl Delta/ A/D converters. The starting point in this technique is the characterization of the quantizer output signal bit pattern. In the case of first-order /spl Sigma/-/spl Delta/ A/D converters this is facilitated by exploiting the fact that the spectrum of this bit pattern contains a dominant tone indicating that the bit pattern is almost periodic. In the case of higher-order A/D converters, this is achieved by taking into account that in stable /spl Sigma/-/spl Delta/ A/D converters, the constituent quantizer almost always operates in its overload-free region. Then, the quantizer input signal can be determined in terms of the DC input signal and in terms of the estimated quantizer output signal bit pattern. The desired quantizer input signal moments can then be obtained in a straightforward fashion. An application example is given to illustrate the accuracy of the proposed moment estimation technique.
{"title":"A novel technique to estimate the statistical properties of /spl Sigma/-/spl Delta/ A/D converters for the investigation of DC stability","authors":"N. A. Fraser, B. Nowrouzian","doi":"10.1109/ISCAS.2002.1010217","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010217","url":null,"abstract":"Concerns the development of a novel technique for the determination of the moments of the quantizer input signal for /spl Sigma/-/spl Delta/ A/D converters. The starting point in this technique is the characterization of the quantizer output signal bit pattern. In the case of first-order /spl Sigma/-/spl Delta/ A/D converters this is facilitated by exploiting the fact that the spectrum of this bit pattern contains a dominant tone indicating that the bit pattern is almost periodic. In the case of higher-order A/D converters, this is achieved by taking into account that in stable /spl Sigma/-/spl Delta/ A/D converters, the constituent quantizer almost always operates in its overload-free region. Then, the quantizer input signal can be determined in terms of the DC input signal and in terms of the estimated quantizer output signal bit pattern. The desired quantizer input signal moments can then be obtained in a straightforward fashion. An application example is given to illustrate the accuracy of the proposed moment estimation technique.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132898962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010162
R. Tonelli, L. Chua, F. Meloni
Built a map relating single atoms in the Periodic Table and different nonlinear Chua's circuits. We show that is possible to connect energy levels in atoms, (as calculated by the simple quantization Bohr's rules), with certain special values of the circuit's resistors. These values are the ones at which the system undergoes a bifurcation, characterizing the period-doubling sequence leading to the chaotic state. We found a quite universal relationship relating atoms to electronic nonlinear circuits that allows one to calculate spectroscopy levels starting from the bifurcation analysis or, vice-versa, bifurcation values from the knowledge of atomic energy levels.
{"title":"Mapping atoms to nonlinear Chua's circuits","authors":"R. Tonelli, L. Chua, F. Meloni","doi":"10.1109/ISCAS.2002.1010162","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010162","url":null,"abstract":"Built a map relating single atoms in the Periodic Table and different nonlinear Chua's circuits. We show that is possible to connect energy levels in atoms, (as calculated by the simple quantization Bohr's rules), with certain special values of the circuit's resistors. These values are the ones at which the system undergoes a bifurcation, characterizing the period-doubling sequence leading to the chaotic state. We found a quite universal relationship relating atoms to electronic nonlinear circuits that allows one to calculate spectroscopy levels starting from the bifurcation analysis or, vice-versa, bifurcation values from the knowledge of atomic energy levels.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133694225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010315
Ching-Che Chung, Chen-Yi Lee
An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35 /spl mu/m 1P4M CMOS process can operate from 40 MHz to 540 MHz. The p-p jitter of the output clock is less than /spl plusmn/170 ps, and the rms jitter of the output clock is less than 39 ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications.
{"title":"An all-digital phase-locked loop for high-speed clock generation","authors":"Ching-Che Chung, Chen-Yi Lee","doi":"10.1109/ISCAS.2002.1010315","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010315","url":null,"abstract":"An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35 /spl mu/m 1P4M CMOS process can operate from 40 MHz to 540 MHz. The p-p jitter of the output clock is less than /spl plusmn/170 ps, and the rms jitter of the output clock is less than 39 ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133285957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010259
Chunyu Xin, B. Xia, W. Sheng, A. Valero-López, E. Sánchez-Sinencio
The paper describes a novel mixed-mode GFSK demodulator with a frequency offset cancellation circuit as part of a low-IF Bluetooth receiver. The demodulator is fabricated in TSMC 0.35 /spl mu/m standard CMOS process, consumes 3 mA from a 3 V power supply and occupies 0.7mm/sup 2/ of silicon area. For 10/sup -3/ BER as specified in Bluetooth standard, only 16.2 dB input SNR is required. The co-channel interference rejection is about 11 dB. The demodulator is robust to process technology variation, and no calibration is required. It can track and cancel the time-varying local oscillator (LO) frequency offset between transmitter and receiver during the whole reception time.
{"title":"A mixed-mode IF GFSK demodulator for Bluetooth","authors":"Chunyu Xin, B. Xia, W. Sheng, A. Valero-López, E. Sánchez-Sinencio","doi":"10.1109/ISCAS.2002.1010259","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010259","url":null,"abstract":"The paper describes a novel mixed-mode GFSK demodulator with a frequency offset cancellation circuit as part of a low-IF Bluetooth receiver. The demodulator is fabricated in TSMC 0.35 /spl mu/m standard CMOS process, consumes 3 mA from a 3 V power supply and occupies 0.7mm/sup 2/ of silicon area. For 10/sup -3/ BER as specified in Bluetooth standard, only 16.2 dB input SNR is required. The co-channel interference rejection is about 11 dB. The demodulator is robust to process technology variation, and no calibration is required. It can track and cancel the time-varying local oscillator (LO) frequency offset between transmitter and receiver during the whole reception time.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133336801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009786
H. Tenhunen, D. Pamunuwa
In deep sub-micron technologies, as the wires are placed ever closer and signal rise and fall times go into the sub-nano second region, increased crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. Here we show that in uniform coupled lines, the response for several important switching configurations has a dominant pole characteristic. This allows easy prediction for the average, worst-case and best-case delay of buffered lines. We show that the repeater numbering and sizing can be optimised to deal with crosstalk under different constraints to best match the application. Area and power issues are considered and all equations are checked against a dynamic circuit simulator (SPECTRE).
{"title":"On dynamic delay and repeater insertion","authors":"H. Tenhunen, D. Pamunuwa","doi":"10.1109/ISCAS.2002.1009786","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009786","url":null,"abstract":"In deep sub-micron technologies, as the wires are placed ever closer and signal rise and fall times go into the sub-nano second region, increased crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. Here we show that in uniform coupled lines, the response for several important switching configurations has a dominant pole characteristic. This allows easy prediction for the average, worst-case and best-case delay of buffered lines. We show that the repeater numbering and sizing can be optimised to deal with crosstalk under different constraints to best match the application. Area and power issues are considered and all equations are checked against a dynamic circuit simulator (SPECTRE).","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011482
Hoi Lee, P. Mok
Most slew rate enhancement circuits can either be used in current-mirror amplifiers or folded-cascode amplifiers, but not in both. In this paper, a new class of slew rate enhancement (SRE) circuits is proposed. By using a single-point detection (SPD) technique at the active load device of the core amplifier to sense the fast signal transient, the new SRE circuits can be used in both current-mirror and folded-cascode amplifiers. In addition, the simple SRE circuits serve as a plug-in feature to the core amplifier and do not affect its original small-signal frequency response. Implemented by an AMS 0.6 /spl mu/m CMOS process, the current-mirror amplifier with SRE circuit occupies an area of 0.027 mm/sup 2/ and achieves 1.5 V//spl mu/s slew rate with 470 pF capacitive load while only dissipating 90 /spl mu/A total static current. Similarly, the folded-cascode amplifier with SRE circuit occupies an area of 0.03 mm/sup 2/ and achieves 1.52 V//spl mu/s slew rate with 470 pF loading while only 84 /spl mu/A total static current is dissipated.
{"title":"Single-point-detection slew-rate enhancement circuits for single-stage amplifiers","authors":"Hoi Lee, P. Mok","doi":"10.1109/ISCAS.2002.1011482","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011482","url":null,"abstract":"Most slew rate enhancement circuits can either be used in current-mirror amplifiers or folded-cascode amplifiers, but not in both. In this paper, a new class of slew rate enhancement (SRE) circuits is proposed. By using a single-point detection (SPD) technique at the active load device of the core amplifier to sense the fast signal transient, the new SRE circuits can be used in both current-mirror and folded-cascode amplifiers. In addition, the simple SRE circuits serve as a plug-in feature to the core amplifier and do not affect its original small-signal frequency response. Implemented by an AMS 0.6 /spl mu/m CMOS process, the current-mirror amplifier with SRE circuit occupies an area of 0.027 mm/sup 2/ and achieves 1.5 V//spl mu/s slew rate with 470 pF capacitive load while only dissipating 90 /spl mu/A total static current. Similarly, the folded-cascode amplifier with SRE circuit occupies an area of 0.03 mm/sup 2/ and achieves 1.52 V//spl mu/s slew rate with 470 pF loading while only 84 /spl mu/A total static current is dissipated.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132273348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010830
E. Kussener, H. Barthélemy, A. Malherbe, A. Kaiser
A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.
{"title":"Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter","authors":"E. Kussener, H. Barthélemy, A. Malherbe, A. Kaiser","doi":"10.1109/ISCAS.2002.1010830","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010830","url":null,"abstract":"A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132448511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010352
C. S. Chan, W. Ki, C. Tsui
A bi-directional switched-capacitor power converter that converts 1.8V to 4.5V from the low voltage (LV) port to the high voltage (HV) port and 4.5V back to 1.8V from the HV port to the LV port is proposed. Each port voltage can be regulated using technique of switching low dropout regulator when it serves as the output. The converter is designed using an AMS 0.6 /spl mu/m n-well process. Simulation results show that each output delivers a maximum load current of 100 mA with good line and load regulation. The efficiencies are 81% for the step-up case and 72% for the step-down case.
{"title":"Bi-directional integrated charge pumps","authors":"C. S. Chan, W. Ki, C. Tsui","doi":"10.1109/ISCAS.2002.1010352","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010352","url":null,"abstract":"A bi-directional switched-capacitor power converter that converts 1.8V to 4.5V from the low voltage (LV) port to the high voltage (HV) port and 4.5V back to 1.8V from the HV port to the LV port is proposed. Each port voltage can be regulated using technique of switching low dropout regulator when it serves as the output. The converter is designed using an AMS 0.6 /spl mu/m n-well process. Simulation results show that each output delivers a maximum load current of 100 mA with good line and load regulation. The efficiencies are 81% for the step-up case and 72% for the step-down case.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132565324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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