Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733441
Tejas Manohar Kesarkar, Nitesh Kumar Sardana
For an electronic product, its housing plays a critical role in protecting the electronic components from environmental loads. In past few years, electronics industry has developed several housing designs. One of the most common designs is a metallic housing, having heat sink and fins.Heat Sink is an important part of a metallic housing. There are several factors affecting the performance of heat sink. One important factor is the Thermal Interface Material (TIM), which is used to ensure physical contact between the Printed Circuit Board (PCB) and heat sink, and to avoid electrical contact between the two parts. The performance of heat sink is affected by the thickness, cross-sectional area and thermal conductivity of TIM.In this study, the importance of TIM is evaluated, by varying all the three parameters viz. thickness (t), thermal conductivity (k) and cross-sectional area (A), of TIM which in turn affect the performance of heat sink.In first part of the study, a typical TIM of typical thickness is used. And evaluations are carried out by varying the percentage area coverage.In second part of the study, the thickness of TIM is varied for constant value of thermal conductivity. The thickness variation is done within the recommended range of thicknesses for materials under study.In third part of the study, thermal conductivity of TIM is varied. The variation is between the TIMs having the highest to the lowest thermal conductivity, which are available in the market for industrial use.All the simulations were steady state simulations, carried out in FloTHERM™ and all three modes of heat transfer i.e. Conduction, Convection and Radiation are considered. The ambient around the electronics is considered to be similar to that faced by automotive electronics in the field. All simulations are carried out for natural convection air flow conditions.These studies will help any electronics development engineer understand the significance of TIM on temperatures of power dissipating components in an ECU. Since the change in material leads to change in cost of the electronics, this study can help the product managers understand trade-off of changing material of TIM, without having to do any new studies.
{"title":"How TIM impacts thermal performance of electronics: : A thermal point of view study to understand impact of Thermal Interface Material (TIM)","authors":"Tejas Manohar Kesarkar, Nitesh Kumar Sardana","doi":"10.23919/ICEP.2019.8733441","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733441","url":null,"abstract":"For an electronic product, its housing plays a critical role in protecting the electronic components from environmental loads. In past few years, electronics industry has developed several housing designs. One of the most common designs is a metallic housing, having heat sink and fins.Heat Sink is an important part of a metallic housing. There are several factors affecting the performance of heat sink. One important factor is the Thermal Interface Material (TIM), which is used to ensure physical contact between the Printed Circuit Board (PCB) and heat sink, and to avoid electrical contact between the two parts. The performance of heat sink is affected by the thickness, cross-sectional area and thermal conductivity of TIM.In this study, the importance of TIM is evaluated, by varying all the three parameters viz. thickness (t), thermal conductivity (k) and cross-sectional area (A), of TIM which in turn affect the performance of heat sink.In first part of the study, a typical TIM of typical thickness is used. And evaluations are carried out by varying the percentage area coverage.In second part of the study, the thickness of TIM is varied for constant value of thermal conductivity. The thickness variation is done within the recommended range of thicknesses for materials under study.In third part of the study, thermal conductivity of TIM is varied. The variation is between the TIMs having the highest to the lowest thermal conductivity, which are available in the market for industrial use.All the simulations were steady state simulations, carried out in FloTHERM™ and all three modes of heat transfer i.e. Conduction, Convection and Radiation are considered. The ambient around the electronics is considered to be similar to that faced by automotive electronics in the field. All simulations are carried out for natural convection air flow conditions.These studies will help any electronics development engineer understand the significance of TIM on temperatures of power dissipating components in an ECU. Since the change in material leads to change in cost of the electronics, this study can help the product managers understand trade-off of changing material of TIM, without having to do any new studies.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733423
Wanli Li, Qingqing Sun, Xuying Liu, K. Suganuma, T. Minari
In this work, two kinds of photonic sintering methods: laser sintering and intense pulsed light sintering are used to sinter air-stable Cu complex inks and achieve dense microstructures of Cu patterns. It is found that the microstructure of sintered Cu patterns from Cu complex inks is highly depended on the removal process of organic matter during the decomposition process. It is difficult to achieve dense and uniform microstructure of Cu pattern by using photonic sintering because of the rapid evaporation of organic matter. The introduction of the low-temperature pre-curing process before photonic sintering can drive the decomposition of Cu complex in a mild way and realize a uniform structure of Cu patterns. The subsequent intense pulsed light can further drive the sintering of Cu patterns to form a highly dense and uniform microstructure of Cu patterns and achieve high conductivity and reliability.
{"title":"Air-stable Cu complex inks for printed electronics with high conductivity and high reliability","authors":"Wanli Li, Qingqing Sun, Xuying Liu, K. Suganuma, T. Minari","doi":"10.23919/ICEP.2019.8733423","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733423","url":null,"abstract":"In this work, two kinds of photonic sintering methods: laser sintering and intense pulsed light sintering are used to sinter air-stable Cu complex inks and achieve dense microstructures of Cu patterns. It is found that the microstructure of sintered Cu patterns from Cu complex inks is highly depended on the removal process of organic matter during the decomposition process. It is difficult to achieve dense and uniform microstructure of Cu pattern by using photonic sintering because of the rapid evaporation of organic matter. The introduction of the low-temperature pre-curing process before photonic sintering can drive the decomposition of Cu complex in a mild way and realize a uniform structure of Cu patterns. The subsequent intense pulsed light can further drive the sintering of Cu patterns to form a highly dense and uniform microstructure of Cu patterns and achieve high conductivity and reliability.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130356208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733561
Qingqing Sun, Wanli Li, Xuying Liu, M. Kanehara, Jianwen Zhao, T. Minari
The flexible field effect transistors (TFTs) play an important role in the application of sensors, artificial intelligence and human-machine interactions and so on. However, the high driving voltage of the TFTs have limited their application in the practical application which require low costs and high performance. Therefore, in our work, the functional semiconducting single-wall carbon nanotubes (f-ss-CNTs) are employed as the semiconducting layer to fabricate the CNTs-based TFTs by room-temperature printing process. The results show that the low driving voltage around 10 V and high on/off ration of 106. Therefore, the CNTs-based TFTs are promising to be applied in a much wider field, such as biosensors and other devices which need low driving voltages.
{"title":"Room-temperature printing of CNTs-based flexible TFTs with high performance","authors":"Qingqing Sun, Wanli Li, Xuying Liu, M. Kanehara, Jianwen Zhao, T. Minari","doi":"10.23919/ICEP.2019.8733561","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733561","url":null,"abstract":"The flexible field effect transistors (TFTs) play an important role in the application of sensors, artificial intelligence and human-machine interactions and so on. However, the high driving voltage of the TFTs have limited their application in the practical application which require low costs and high performance. Therefore, in our work, the functional semiconducting single-wall carbon nanotubes (f-ss-CNTs) are employed as the semiconducting layer to fabricate the CNTs-based TFTs by room-temperature printing process. The results show that the low driving voltage around 10 V and high on/off ration of 106. Therefore, the CNTs-based TFTs are promising to be applied in a much wider field, such as biosensors and other devices which need low driving voltages.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114604014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733603
Mika Kurosawa, Takuro Sasaki, Masaya Ohara, Taisuke Tanaka, Yuichiro Hayakawa, M. Kaneko, F. Uchikoba, K. Saeki, Ken Saito
The authors are studying a robot controlling system using hardware neural networks (HNN). Previously, the authors succeeded to locomote the quadruped-type and the hexapod-type microrobot systems using the HNN integrated circuit (IC). The HNN IC outputs four-phase pulse waveforms to drive both microrobot systems. However, gait patterns need 1.0 s pulse period which requires large capacitors. A large capacitor could not mount on IC; therefore, the external capacitors mounted on the circuit board. The further miniaturization of the HNN IC needs to minimize the capacitors. In this paper, the authors constructed HNN which can generate a large pulse period without using large capacitors. The interstitial cell model is used as a basic element of the HNN to generate a large time constant. The authors designed two types of HNN which can generate a tripod gait pattern and a ripple gait pattern which are typical walking patterns of insects. As a result, designed HNN can generate gait patterns without using external capacitors. The capacitors could construct inside the IC using the interstitial cell model.
{"title":"Gait Pattern Generation of Hexapod-Type Microrobot Using Interstitial Cell Model Based Hardware Neural Networks IC","authors":"Mika Kurosawa, Takuro Sasaki, Masaya Ohara, Taisuke Tanaka, Yuichiro Hayakawa, M. Kaneko, F. Uchikoba, K. Saeki, Ken Saito","doi":"10.23919/ICEP.2019.8733603","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733603","url":null,"abstract":"The authors are studying a robot controlling system using hardware neural networks (HNN). Previously, the authors succeeded to locomote the quadruped-type and the hexapod-type microrobot systems using the HNN integrated circuit (IC). The HNN IC outputs four-phase pulse waveforms to drive both microrobot systems. However, gait patterns need 1.0 s pulse period which requires large capacitors. A large capacitor could not mount on IC; therefore, the external capacitors mounted on the circuit board. The further miniaturization of the HNN IC needs to minimize the capacitors. In this paper, the authors constructed HNN which can generate a large pulse period without using large capacitors. The interstitial cell model is used as a basic element of the HNN to generate a large time constant. The authors designed two types of HNN which can generate a tripod gait pattern and a ripple gait pattern which are typical walking patterns of insects. As a result, designed HNN can generate gait patterns without using external capacitors. The capacitors could construct inside the IC using the interstitial cell model.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733501
Ami Tezuka, H. Kuwae, Kosuke Yamada, S. Shoji, S. Kakio, J. Mizuno
LiTaO3 (LT) or LiNbO3 (LN)/Quartz bonded substrates with an amorphous intermediate layer were proposed to achieve both a large surface acoustic wave (SAW) velocity and a smaller temperature coefficient of frequency. Residual stress reduction of the amorphous film is expected to improve the bonding strength of a SAW substrate. In this report, we studied a method of low-residual stress amorphous film deposition for LT or LN/Quartz bonding. The residual stress of the LT substrate with an amorphous SiO2 or Al2O3 film deposited by ion beam sputtering, electron cyclotron resonance sputtering, and atomic layer deposition was evaluated. The LT substrate with the amorphous Al2O3 film deposited by ALD had the minimum warpage (-0.152 μm) and residual stress (127.3 MPa). The residual stress of the Al2O3 film deposited by ALD might be reduced because almost the same thickness of the Al2O3 film was deposited on both sides of the LT substrate at the same time. The maximum bonding strength of 3.7 MPa was achieved in the substrate with the Al2O3 film deposited by ALD. From these results, LT or LN/Quartz substrates with the Al2O3 film deposited by ALD are promising materials to reduce residual stress toward SAW devices for 5G mobile communication.
{"title":"Study of Low-residual Stress Amorphous Film Deposition Method for LiTaO3/Quartz or LiNbO3/Quartz Bonding toward 5G Surface Acoustic Wave Devices","authors":"Ami Tezuka, H. Kuwae, Kosuke Yamada, S. Shoji, S. Kakio, J. Mizuno","doi":"10.23919/ICEP.2019.8733501","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733501","url":null,"abstract":"LiTaO<inf>3</inf> (LT) or LiNbO<inf>3</inf> (LN)/Quartz bonded substrates with an amorphous intermediate layer were proposed to achieve both a large surface acoustic wave (SAW) velocity and a smaller temperature coefficient of frequency. Residual stress reduction of the amorphous film is expected to improve the bonding strength of a SAW substrate. In this report, we studied a method of low-residual stress amorphous film deposition for LT or LN/Quartz bonding. The residual stress of the LT substrate with an amorphous SiO<inf>2</inf> or Al<inf>2</inf>O<inf>3</inf> film deposited by ion beam sputtering, electron cyclotron resonance sputtering, and atomic layer deposition was evaluated. The LT substrate with the amorphous Al<inf>2</inf>O<inf>3</inf> film deposited by ALD had the minimum warpage (-0.152 μm) and residual stress (127.3 MPa). The residual stress of the Al<inf>2</inf>O<inf>3</inf> film deposited by ALD might be reduced because almost the same thickness of the Al<inf>2</inf>O<inf>3</inf> film was deposited on both sides of the LT substrate at the same time. The maximum bonding strength of 3.7 MPa was achieved in the substrate with the Al<inf>2</inf>O<inf>3</inf> film deposited by ALD. From these results, LT or LN/Quartz substrates with the Al<inf>2</inf>O<inf>3</inf> film deposited by ALD are promising materials to reduce residual stress toward SAW devices for 5G mobile communication.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131379108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733557
N. Hasegawa, K. Hashizume, Toshiya Murata
So far, we investigated the influence of phosphorus content and Sulfur content in electroless Ni-P plating films on film properties. As a result, we reported that the film containing low phosphorus content and containing no Sulfur is less susceptible to embrittlement during heat treatment. However, in the films reported so far, there are cases where sufficient cracks resistance cannot be obtained when the heat treatment temperature is 350 °C. Therefore, in this paper, we report on the development of a film which does not have cracks even after heat treatment at 400 °C by no Sulfur and low phosphorus content than films reported so far.
{"title":"Development of Electroless Ni-P Plating Film for Power Modules","authors":"N. Hasegawa, K. Hashizume, Toshiya Murata","doi":"10.23919/ICEP.2019.8733557","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733557","url":null,"abstract":"So far, we investigated the influence of phosphorus content and Sulfur content in electroless Ni-P plating films on film properties. As a result, we reported that the film containing low phosphorus content and containing no Sulfur is less susceptible to embrittlement during heat treatment. However, in the films reported so far, there are cases where sufficient cracks resistance cannot be obtained when the heat treatment temperature is 350 °C. Therefore, in this paper, we report on the development of a film which does not have cracks even after heat treatment at 400 °C by no Sulfur and low phosphorus content than films reported so far.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115827759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733553
Meiyu Wang, Yanliang Shan, Y. Mei, Xin Li, G. Lu
Die-attach by metal-powder sintering is being widely adopted in the power electronics industry for manufacturing power semiconductor discrete devices and modules. Thus far, the most widely practiced process involves pressure-assisted silver sintering on direct-bond copper (DBC) substrates that are surface-finished with a coating of silver or gold. In this paper, sintering die-attach processes were done on native DBC substrates by pressure- less sintering of a silver paste and pressure-assisted sintering of a copper paste. To prevent copper oxidation, the silver die-attach process was done in a mixture of formic- acid gas and air, while the copper process in forming-gas (4%H2/N2). The effects of sintering atmosphere, temperature, and pressure on die shear strength were investigated. We achieved strong die-shear strength and oxidation-free sintered bond-line with either bonding process under less stringent demands on materials and processing conditions for low-cost implementation of the die-attach technology in manufacturing.
{"title":"Processing and Characterization of Die-attach on Uncoated Copper by Pressure-less Silver Sintering and Low-pressure-assisted Copper Sintering","authors":"Meiyu Wang, Yanliang Shan, Y. Mei, Xin Li, G. Lu","doi":"10.23919/ICEP.2019.8733553","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733553","url":null,"abstract":"Die-attach by metal-powder sintering is being widely adopted in the power electronics industry for manufacturing power semiconductor discrete devices and modules. Thus far, the most widely practiced process involves pressure-assisted silver sintering on direct-bond copper (DBC) substrates that are surface-finished with a coating of silver or gold. In this paper, sintering die-attach processes were done on native DBC substrates by pressure- less sintering of a silver paste and pressure-assisted sintering of a copper paste. To prevent copper oxidation, the silver die-attach process was done in a mixture of formic- acid gas and air, while the copper process in forming-gas (4%H2/N2). The effects of sintering atmosphere, temperature, and pressure on die shear strength were investigated. We achieved strong die-shear strength and oxidation-free sintered bond-line with either bonding process under less stringent demands on materials and processing conditions for low-cost implementation of the die-attach technology in manufacturing.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128953491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733459
Y. Ishitsuka
Cosmetics are beneficial tools that fulfill the wishes of people to remain youthful. We as a cosmetic manufacturer have conducted various research and development to provide customers with those excellent tools. In the research and development of cosmetics for skin and hair, sensing technology has greatly played an important role. This report will explain the roles of sensing technology as it outlines the current situation of cosmetic research. Furthermore, the possibility of the further fusion of cosmetic research and electronics will be examined.
{"title":"Possibility of Fusion: Cosmetic Research and Electronics","authors":"Y. Ishitsuka","doi":"10.23919/ICEP.2019.8733459","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733459","url":null,"abstract":"Cosmetics are beneficial tools that fulfill the wishes of people to remain youthful. We as a cosmetic manufacturer have conducted various research and development to provide customers with those excellent tools. In the research and development of cosmetics for skin and hair, sensing technology has greatly played an important role. This report will explain the roles of sensing technology as it outlines the current situation of cosmetic research. Furthermore, the possibility of the further fusion of cosmetic research and electronics will be examined.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130824339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733495
Huang Hung-Hsien, Cheng-Yu Tsai, Jung-Che Tsai, M. Shih, David C. Tang, C. Hung
The 2.5-D semiconductor package is the most popular package structure for high end applications. In this study, for thermal enhancement of a 2.5-D package, several thermal solutions such as lid attachment, fin heat sink, and fan-cooled heat sink with or without embedded heat pipe are considered in thermal simulation and measurement analysis of a 2.5-D thermal test vehicle with multi chips on interposer. All the designs rely on 6L printed circuit board to maximize power dissipation. The heat sink is mounted on top of the package to minimize thermal resistance. Anodized aluminum extrusion fin heat sink is used for low power condition (12 W) while fan-cooled heat sink is used for input power above 60 W to reduce heat accumulation. An interesting observation is that there is no significant difference of thermal enhancement in high power (168 W) thermal measurement between heat sink with or without the heat pipe. However, thermal simulation results indicate that this case has a noticeable thermal enhancement, as a decrease of about 8 °C was observed in the junction temperature. Thus, the heat sink performance has been verified by Qmax measurement. In addition, the thermal interface material coverage issues were considered while examining high power thermal performance by simulating two different reducing volume conditions, namely, void dispersion and volume shrinkage. The results indicate that the shrinkage is a major factor to be considered for all the simulation conditions.
{"title":"From Package to System Thermal Characterization and Design of High Power 2.5-D IC","authors":"Huang Hung-Hsien, Cheng-Yu Tsai, Jung-Che Tsai, M. Shih, David C. Tang, C. Hung","doi":"10.23919/ICEP.2019.8733495","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733495","url":null,"abstract":"The 2.5-D semiconductor package is the most popular package structure for high end applications. In this study, for thermal enhancement of a 2.5-D package, several thermal solutions such as lid attachment, fin heat sink, and fan-cooled heat sink with or without embedded heat pipe are considered in thermal simulation and measurement analysis of a 2.5-D thermal test vehicle with multi chips on interposer. All the designs rely on 6L printed circuit board to maximize power dissipation. The heat sink is mounted on top of the package to minimize thermal resistance. Anodized aluminum extrusion fin heat sink is used for low power condition (12 W) while fan-cooled heat sink is used for input power above 60 W to reduce heat accumulation. An interesting observation is that there is no significant difference of thermal enhancement in high power (168 W) thermal measurement between heat sink with or without the heat pipe. However, thermal simulation results indicate that this case has a noticeable thermal enhancement, as a decrease of about 8 °C was observed in the junction temperature. Thus, the heat sink performance has been verified by Qmax measurement. In addition, the thermal interface material coverage issues were considered while examining high power thermal performance by simulating two different reducing volume conditions, namely, void dispersion and volume shrinkage. The results indicate that the shrinkage is a major factor to be considered for all the simulation conditions.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114413717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733446
S. Lin, Hseng-ming Liao, Che-yu Yeh, Chih-han Yang
In recent years, electronic devices used in our ordinary life become powerful and multifunctional, such as virtual reality (VR), internet of things (IoT), also the electrical vehicle. 3D IC and wide bandgap (WBG) semiconductor packaging are one of the most notable technologies in electronic packaging industries [1]–[3]. However, Conventional packaging technologies are gradually unable to meet the requirements of 3D IC or high-power devices operated in extremely harsh environments. In our previous work, we proposed a novel approach based on a transient liquid phase (TLP) bonding for forming face-centered cubic solid-solution joints without the formation of intermetallic compounds. A trace amount of gallium (Ga) and nickel (Ni) in an under-bump-metallurgy (UBM) process at 300°C for 24 h with high-strength and excellent thermal stability. In this study, due to the high surface tension of liquid Ga and the long time it takes to form the bonding joints, liquid Ga was replaced with Ga-based submicron particles (SMPs) by a sonochemical process. With Ga-based paste and Ni UBM, high-strength, thermally stable, and low resistance Cu-to-Cu bonding joints can be fabricated at a relatively low temperature and short bonding time comparing to the process reported in our previous work. The industrial application of Ga-based SMPs was conclusively demonstrated by a series of evaluations of Ga-based SMPs and Cu-to-Cu bonding joints.
{"title":"A novel TLP bonding based on sub-micron Ga particles","authors":"S. Lin, Hseng-ming Liao, Che-yu Yeh, Chih-han Yang","doi":"10.23919/ICEP.2019.8733446","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733446","url":null,"abstract":"In recent years, electronic devices used in our ordinary life become powerful and multifunctional, such as virtual reality (VR), internet of things (IoT), also the electrical vehicle. 3D IC and wide bandgap (WBG) semiconductor packaging are one of the most notable technologies in electronic packaging industries [1]–[3]. However, Conventional packaging technologies are gradually unable to meet the requirements of 3D IC or high-power devices operated in extremely harsh environments. In our previous work, we proposed a novel approach based on a transient liquid phase (TLP) bonding for forming face-centered cubic solid-solution joints without the formation of intermetallic compounds. A trace amount of gallium (Ga) and nickel (Ni) in an under-bump-metallurgy (UBM) process at 300°C for 24 h with high-strength and excellent thermal stability. In this study, due to the high surface tension of liquid Ga and the long time it takes to form the bonding joints, liquid Ga was replaced with Ga-based submicron particles (SMPs) by a sonochemical process. With Ga-based paste and Ni UBM, high-strength, thermally stable, and low resistance Cu-to-Cu bonding joints can be fabricated at a relatively low temperature and short bonding time comparing to the process reported in our previous work. The industrial application of Ga-based SMPs was conclusively demonstrated by a series of evaluations of Ga-based SMPs and Cu-to-Cu bonding joints.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115288080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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