Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733470
T. Fukumori, T. Akahoshi, D. Mizutani, S. Sakuyama
For high-speed signal transmission lines in printed wiring boards, a parameter is required to determine the insertion loss in the line. Surface relative conductivity (σr) is considered to be a promising option. However, surface σr cannot always be measured because of the surface treatment or semi-additive process used. In this report, we characterize the conditions of the interface conductor by the interface σr. The results show a strong correlation between insertion loss and interface or. Therefore, we consider interface or to be useful in characterizing the conductor interface conditions with respect to insertion losses.
{"title":"Correlation between Insertion Loss and Interface Relative Conductivity","authors":"T. Fukumori, T. Akahoshi, D. Mizutani, S. Sakuyama","doi":"10.23919/ICEP.2019.8733470","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733470","url":null,"abstract":"For high-speed signal transmission lines in printed wiring boards, a parameter is required to determine the insertion loss in the line. Surface relative conductivity (σr) is considered to be a promising option. However, surface σr cannot always be measured because of the surface treatment or semi-additive process used. In this report, we characterize the conditions of the interface conductor by the interface σr. The results show a strong correlation between insertion loss and interface or. Therefore, we consider interface or to be useful in characterizing the conductor interface conditions with respect to insertion losses.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733506
D. B. Milo
One of the most complicated process in semiconductor packaging is wire bonding. Not only is wire bonding process dynamic due to varying conditions and parameters, complex wire layout with use of multiple and thin wires laid out on a single layered lead frame makes it more difficult. Challenges posed by this process and material combinations hinder the opportunity to grow and gain more of the market, especially in high pin-count QFN package.This paper will discuss QFN multi-level pin routing, an innovation in QFN lead frame design which will enable complex wire bonding layout for high pin-count QFN packages. This design provides elevated bonding sites positioned to avoid wire sweeps, sags, risks of short circuits and other damages which are attributed to complex wire layouts. Signals from the bond sites can be routed to the package leads by the multilevel leadframe, providing a cost effective and highly manufacturable package.
{"title":"QFN Multi-Level Pin Routing:Innovative Design Approach Enabling Complex Wire Bonding Layout","authors":"D. B. Milo","doi":"10.23919/ICEP.2019.8733506","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733506","url":null,"abstract":"One of the most complicated process in semiconductor packaging is wire bonding. Not only is wire bonding process dynamic due to varying conditions and parameters, complex wire layout with use of multiple and thin wires laid out on a single layered lead frame makes it more difficult. Challenges posed by this process and material combinations hinder the opportunity to grow and gain more of the market, especially in high pin-count QFN package.This paper will discuss QFN multi-level pin routing, an innovation in QFN lead frame design which will enable complex wire bonding layout for high pin-count QFN packages. This design provides elevated bonding sites positioned to avoid wire sweeps, sags, risks of short circuits and other damages which are attributed to complex wire layouts. Signals from the bond sites can be routed to the package leads by the multilevel leadframe, providing a cost effective and highly manufacturable package.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115353010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733503
Juncai Hou, Chengxin Li, Sijie Huang, H. Nishikawa
Reliable die-attach bonding is critical for high temperature electronic packaging. A Cu-to-Cu bonding was attempted by using an in stiu nanocrystallized surface on commerical microscale Cu cold spray deposition without using organic solvents. During sintering at 300 °C, Cu2O nano particles were formed on the surface of the cold spray deposition and then were reduced into Cu nano particles by formic acid. The shear strength reaches 20.7 MPa under applied pressure of 5 MPa and was increased with an increase of applied pressure. The formation of nanoparticles lead to a much higher shear strength compared to the joint fabricated by using microscale Cu particles. Cu2O would be further oxidized at higher temperature transferring into CuO and consequently CuO would be firstly reduced to Cu2O gradually. Subsequently, Cu2O can be reduced into Cu finally. Controlling the oxidation temperature could achieve Cu-to-Cu bonding quickly. An economical approach to implement Cu-to-Cu bonding was established.
{"title":"Bonding strength of Cu-to-Cu joints using Cu cold spray deposition by an oxidation and reduction process for power device package","authors":"Juncai Hou, Chengxin Li, Sijie Huang, H. Nishikawa","doi":"10.23919/ICEP.2019.8733503","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733503","url":null,"abstract":"Reliable die-attach bonding is critical for high temperature electronic packaging. A Cu-to-Cu bonding was attempted by using an in stiu nanocrystallized surface on commerical microscale Cu cold spray deposition without using organic solvents. During sintering at 300 °C, Cu2O nano particles were formed on the surface of the cold spray deposition and then were reduced into Cu nano particles by formic acid. The shear strength reaches 20.7 MPa under applied pressure of 5 MPa and was increased with an increase of applied pressure. The formation of nanoparticles lead to a much higher shear strength compared to the joint fabricated by using microscale Cu particles. Cu2O would be further oxidized at higher temperature transferring into CuO and consequently CuO would be firstly reduced to Cu2O gradually. Subsequently, Cu2O can be reduced into Cu finally. Controlling the oxidation temperature could achieve Cu-to-Cu bonding quickly. An economical approach to implement Cu-to-Cu bonding was established.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123069398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733532
R. Takayanagi, K. Taniguchi, M. Hoya, N. Kanai, T. Tsuji, M. Hori, Y. Ikeda, K. Maruyama, I. Kawamura
3.3 kV / 200 A All-SiC module with trench-gate SiC MOSFETs is developed for static var compensator (SVC), a type of the electric distribution equipment. This module has the structural feature; resin-mold single-switch units are arrayed and electrically connected by bus-bars to make the circuit configuration dual (2-in-1). This structure leads to the smaller stack and the higher long-term reliability. Applied trench-gate SiC MOSFETs, lower loss is also accomplished. ON-state resistance is reduced around 10%. In addition, 60% reduction of total switching loss is achieved. These characteristics of low energy loss can contribute to downsizing of SVC equipment as well as energy saving.
{"title":"3.3kV Power Module for Electric Distribution Equipment with SiC Trench-Gate MOSFET","authors":"R. Takayanagi, K. Taniguchi, M. Hoya, N. Kanai, T. Tsuji, M. Hori, Y. Ikeda, K. Maruyama, I. Kawamura","doi":"10.23919/ICEP.2019.8733532","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733532","url":null,"abstract":"3.3 kV / 200 A All-SiC module with trench-gate SiC MOSFETs is developed for static var compensator (SVC), a type of the electric distribution equipment. This module has the structural feature; resin-mold single-switch units are arrayed and electrically connected by bus-bars to make the circuit configuration dual (2-in-1). This structure leads to the smaller stack and the higher long-term reliability. Applied trench-gate SiC MOSFETs, lower loss is also accomplished. ON-state resistance is reduced around 10%. In addition, 60% reduction of total switching loss is achieved. These characteristics of low energy loss can contribute to downsizing of SVC equipment as well as energy saving.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122711215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733457
X. Qiu, J. Lo, S. R. Ricky Lee, Ying-Hong Liou, P. Chiu
Cu pillar micro-bumps are the enabling technology for high-density fine-pitch interconnection in flip-chip die stacking and 3D IC integration. Due to the significant mismatch in coefficient of thermal expansion (CTE) between the silicon chip and organic substrate or the printed circuit board (PCB), the rigid joints made of pure Cu pillars may suffer rather high thermomechanical stress during reflow bonding and operations. Cu pillar micro-bumps with printed polymer core are proposed in this study to reduce thermomechanical stress and improve joint reliability. Micro-scale cylindrical polymer cores with diameter of ~20μm and height of ~25μm were fabricated by synchronized UV-cured polymer jetting and real-time in situ UV LED curing. Height uniformity of printed polymer cores in a piece of wafer (14700 polymer cores) was characterized and it was concluded that the height variation between two adjacent polymer cores was only 1.4 × 10−3%. For one chip with 588 polymer cores, the height variation was within 1%. It was concluded that the printed polymer cores were uniform in height and the fabrication process for printed polymer cores was acceptable. After surface metallization, Cu pillars micro-bumps with printed polymer core with diameter of ~30μm and height of ~30μm were achieved. Shear test showed that shear strength of Cu pillar micro-bumps with printed polymer core was 20% higher than that of conventional Cu pillars because adhesion between UV-cured polymer and SiO2 surface was better than fracture toughness of TiW layer. It was concluded that Cu pillars micro-bumps with printed polymer core were capable to be applied in high-density fine-pitch interconnection based on height uniformity and shear force characterization.
{"title":"Evaluation and Benchmarking of Cu Pillar Micro-bumps with Printed Polymer Core","authors":"X. Qiu, J. Lo, S. R. Ricky Lee, Ying-Hong Liou, P. Chiu","doi":"10.23919/ICEP.2019.8733457","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733457","url":null,"abstract":"Cu pillar micro-bumps are the enabling technology for high-density fine-pitch interconnection in flip-chip die stacking and 3D IC integration. Due to the significant mismatch in coefficient of thermal expansion (CTE) between the silicon chip and organic substrate or the printed circuit board (PCB), the rigid joints made of pure Cu pillars may suffer rather high thermomechanical stress during reflow bonding and operations. Cu pillar micro-bumps with printed polymer core are proposed in this study to reduce thermomechanical stress and improve joint reliability. Micro-scale cylindrical polymer cores with diameter of ~20μm and height of ~25μm were fabricated by synchronized UV-cured polymer jetting and real-time in situ UV LED curing. Height uniformity of printed polymer cores in a piece of wafer (14700 polymer cores) was characterized and it was concluded that the height variation between two adjacent polymer cores was only 1.4 × 10−3%. For one chip with 588 polymer cores, the height variation was within 1%. It was concluded that the printed polymer cores were uniform in height and the fabrication process for printed polymer cores was acceptable. After surface metallization, Cu pillars micro-bumps with printed polymer core with diameter of ~30μm and height of ~30μm were achieved. Shear test showed that shear strength of Cu pillar micro-bumps with printed polymer core was 20% higher than that of conventional Cu pillars because adhesion between UV-cured polymer and SiO2 surface was better than fracture toughness of TiW layer. It was concluded that Cu pillars micro-bumps with printed polymer core were capable to be applied in high-density fine-pitch interconnection based on height uniformity and shear force characterization.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115785350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733476
T. Semba, G. Saito, Shuichi Asao, K. Shirasawa, H. Takato
In order to investigate the influence of the difference in module structure on the degradation of the solar cell, two kinds of different solar modules were fabricated, and a high temperature and high humidity test was carried out and the degradation mode was compared by electrical characteristics and electroluminescence inspection. Although degradation of output occurred in both modules, different degradation modes were confirmed by electroluminescence images. It is assumed that the difference in degradation mode between these modular structures is due to the difference in concentration distribution inside the module of moisture intruded into the module and acetic acid generated from the encapsulant inside the module.
{"title":"Influence of Module Structure on Reliability of Silicon Solar Cells","authors":"T. Semba, G. Saito, Shuichi Asao, K. Shirasawa, H. Takato","doi":"10.23919/ICEP.2019.8733476","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733476","url":null,"abstract":"In order to investigate the influence of the difference in module structure on the degradation of the solar cell, two kinds of different solar modules were fabricated, and a high temperature and high humidity test was carried out and the degradation mode was compared by electrical characteristics and electroluminescence inspection. Although degradation of output occurred in both modules, different degradation modes were confirmed by electroluminescence images. It is assumed that the difference in degradation mode between these modular structures is due to the difference in concentration distribution inside the module of moisture intruded into the module and acetic acid generated from the encapsulant inside the module.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126413809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733601
K. Ong, W. K. Loh, R. Kulterman, Chih Chung Hsu, Jenn An Wang, H. Fu
Simulation tools such as FEA or CFD are widely employed to predict the thermal mechanical behavior of an electronic package based on the design and material attributes. Prediction accuracy and representation are highly dependent on the material model (visco-elastic, chemical shrinkage etc) and analysis approach especially for mold encapsulated packaging. In this paper, a basic evaluation was conducted using an arbitrary bi-material model to compare the material model of visco-elastic, time-temperature superposition shift factor and chemical shrinkage based on PVTC in both Moldex3D and FEA-A tools. The impact of visco-elastic constitutive property with temperature effects were included with a two steps shift factor model of Arrhenius and WLF functions. The implementation equations and analytical solutions are presented together with a detail discussion of the property model used. Transient heat transfer and structural analysis steps were incorporated to simulate the impact of visco-elastic property and shrinkage to the bi-material model.
{"title":"Molded Electronic Package Warpage Predictive Modelling Methodologies","authors":"K. Ong, W. K. Loh, R. Kulterman, Chih Chung Hsu, Jenn An Wang, H. Fu","doi":"10.23919/ICEP.2019.8733601","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733601","url":null,"abstract":"Simulation tools such as FEA or CFD are widely employed to predict the thermal mechanical behavior of an electronic package based on the design and material attributes. Prediction accuracy and representation are highly dependent on the material model (visco-elastic, chemical shrinkage etc) and analysis approach especially for mold encapsulated packaging. In this paper, a basic evaluation was conducted using an arbitrary bi-material model to compare the material model of visco-elastic, time-temperature superposition shift factor and chemical shrinkage based on PVTC in both Moldex3D and FEA-A tools. The impact of visco-elastic constitutive property with temperature effects were included with a two steps shift factor model of Arrhenius and WLF functions. The implementation equations and analytical solutions are presented together with a detail discussion of the property model used. Transient heat transfer and structural analysis steps were incorporated to simulate the impact of visco-elastic property and shrinkage to the bi-material model.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125914129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733515
M. Yasunaga, Shumpei Matsuoka, Yuya Hoshinor, Takashi Matsumoto, T. Odaira
Signal integrity (SI) degradation in printed circuit boards (PCBs) has been becoming more serious problem in GHz domain due to the difficulty of impedance matching designs. In this paper, we propose a novel trace structure called capacitor- segmental transmission line (C-STL) and its design methodology to overcome the SI degradation problem. In the C-STL, we intentionally generate reflection waves, or noises due to impedance mismatching by embedded chip capacitors connected to the trace, or transmission line in the PCB, and superpose the reflection waves onto the distorted digital signals to shape it to ideal ones. We use genetic algorithm to design the C-STL because chip-capacitor-selection becomes a combinatorial explosion problem. We fabricate a C-STL prototype and demonstrate its high SI improvement capability by eye-diagram measurements.
{"title":"A High Signal-Integrity PCB-Trace with Embedded Chip Capacitors and Its Design Methodology Using Genetic Algorithm","authors":"M. Yasunaga, Shumpei Matsuoka, Yuya Hoshinor, Takashi Matsumoto, T. Odaira","doi":"10.23919/ICEP.2019.8733515","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733515","url":null,"abstract":"Signal integrity (SI) degradation in printed circuit boards (PCBs) has been becoming more serious problem in GHz domain due to the difficulty of impedance matching designs. In this paper, we propose a novel trace structure called capacitor- segmental transmission line (C-STL) and its design methodology to overcome the SI degradation problem. In the C-STL, we intentionally generate reflection waves, or noises due to impedance mismatching by embedded chip capacitors connected to the trace, or transmission line in the PCB, and superpose the reflection waves onto the distorted digital signals to shape it to ideal ones. We use genetic algorithm to design the C-STL because chip-capacitor-selection becomes a combinatorial explosion problem. We fabricate a C-STL prototype and demonstrate its high SI improvement capability by eye-diagram measurements.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131531643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733509
T. Onomoto, Y. Yoshida, N. Miki
This paper describes investigation of the brain activity in an adapting process to inversion vision through electroencephalogram (EEG). In particular, we used Candle-like microneedle electrodes, which does not require any preparation for measuring high-quality EEG. Note that conventional wet electrodes require abrasion of stratum corneum and application of electrolyte paste as preparation for measurement of EEG and they give discomfort to subjects and take time for experimenters. In our previous study, the eye movement during the adapting process was measured and the progress of the process was successfully captured. In this study, we measured EEG during the pointing task under an inverse vision state to correlate the perceptual learning with EEG. We discovered that High β wave, Low γ wave and Mid γ wave had strong correlation with the process of adapting to inversed vision.
{"title":"Electroencephalogram Measurement in Adapting Process to Inverse Vision","authors":"T. Onomoto, Y. Yoshida, N. Miki","doi":"10.23919/ICEP.2019.8733509","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733509","url":null,"abstract":"This paper describes investigation of the brain activity in an adapting process to inversion vision through electroencephalogram (EEG). In particular, we used Candle-like microneedle electrodes, which does not require any preparation for measuring high-quality EEG. Note that conventional wet electrodes require abrasion of stratum corneum and application of electrolyte paste as preparation for measurement of EEG and they give discomfort to subjects and take time for experimenters. In our previous study, the eye movement during the adapting process was measured and the progress of the process was successfully captured. In this study, we measured EEG during the pointing task under an inverse vision state to correlate the perceptual learning with EEG. We discovered that High β wave, Low γ wave and Mid γ wave had strong correlation with the process of adapting to inversed vision.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131538448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733416
Y. Susumago, Achille Jacquemond, N. Takahashi, H. Kino, Tetsu Tanaka, T. Fukushima
A new flexible hybrid electronics (FHE) approach is studied for integrating high-performance and scalable flexible systems at the wafer level. The unique structure is consisting of monocrystalline semiconductor dielets embedded in flexible substrates such as elastomers. Stress buffer layers (SBL) as a key material are inserted between inter-dielet wirings and the substrates to enhance wire reliability. The impact of the SBL properties on the bendability of the FHE systems is described in this work.
{"title":"Mechanical Characterization of FOWLPBased Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application","authors":"Y. Susumago, Achille Jacquemond, N. Takahashi, H. Kino, Tetsu Tanaka, T. Fukushima","doi":"10.23919/ICEP.2019.8733416","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733416","url":null,"abstract":"A new flexible hybrid electronics (FHE) approach is studied for integrating high-performance and scalable flexible systems at the wafer level. The unique structure is consisting of monocrystalline semiconductor dielets embedded in flexible substrates such as elastomers. Stress buffer layers (SBL) as a key material are inserted between inter-dielet wirings and the substrates to enhance wire reliability. The impact of the SBL properties on the bendability of the FHE systems is described in this work.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115731474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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