Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733530
T. Iwasaki
A materials-informatics technique for designing strong flat interfaces has been developed by use of advanced simulation that can calculate the delamination energy as the adhesion strength. In this study, this technique is applied to the design of metal (or alloy) with strong adhesion to polyimide, which is an example resin used for printed circuit boards. At the first stage, the interatomic spacings were selected as the important, dominant metal parameters from four metal parameters (the short-distance and long-distance interatomic spacings, electronegativity, and surface energy density) by using sensitivity analysis based on the design-of-experiments method with the delamination-energy data calculated from the advanced simulation. At the second stage, the adhesion strength (delamination energy) is expressed as a function of the important alloy parameters (i.e., the short-distance and long-distance interatomic spacings) by using Kriging-method-based artificial intelligence. At the third stage, by solving the maximum-value problem of the function, it was found that the metal that has the same short-distance and long-distance interatomic spacings as those of the resin has the strongest adhesion to the resin. Finally, it was confirmed that the metal (Ni-12%Mn) that satisfies this lattice-matching condition has the strongest adhesion by conducting a scratch test. Thus, lattice matching was found to be the most important factor in the adhesion.
{"title":"Materials Informatics Technique for Designing Strong-Adhesion Interfaces in Electronics Devices","authors":"T. Iwasaki","doi":"10.23919/ICEP.2019.8733530","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733530","url":null,"abstract":"A materials-informatics technique for designing strong flat interfaces has been developed by use of advanced simulation that can calculate the delamination energy as the adhesion strength. In this study, this technique is applied to the design of metal (or alloy) with strong adhesion to polyimide, which is an example resin used for printed circuit boards. At the first stage, the interatomic spacings were selected as the important, dominant metal parameters from four metal parameters (the short-distance and long-distance interatomic spacings, electronegativity, and surface energy density) by using sensitivity analysis based on the design-of-experiments method with the delamination-energy data calculated from the advanced simulation. At the second stage, the adhesion strength (delamination energy) is expressed as a function of the important alloy parameters (i.e., the short-distance and long-distance interatomic spacings) by using Kriging-method-based artificial intelligence. At the third stage, by solving the maximum-value problem of the function, it was found that the metal that has the same short-distance and long-distance interatomic spacings as those of the resin has the strongest adhesion to the resin. Finally, it was confirmed that the metal (Ni-12%Mn) that satisfies this lattice-matching condition has the strongest adhesion by conducting a scratch test. Thus, lattice matching was found to be the most important factor in the adhesion.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115674124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733569
M. Hachiya, M. Yoshikawa
General purpose computing on GPU (Graphics Processing Units) is gaining momentum, however, GPU is reaching air cooling limit at the same time. As thermal resistance of GPU’s heat sink is already minimized, thermal resistance between GPU and heat sink is required to be reduced in order to overcome the air cooling limit. The present study investigates an enhanced vapor chamber using dielectric organic refrigerant in place of water as working fluid. It is important to increase evaporative heat transfer coefficient in order to reduce thermal resistance of a vapor chamber, and it is confirmed that evaporative heat transfer coefficient at the heat flux of GPU can be increased by utilizing refrigerant, because bubble generation frequency becomes significantly higher due to weaker surface tension although heat transfer quantity by generating a vapor bubble becomes smaller due to smaller thermal conductivity and specific heat. In addition, the presented vapor chamber can be applied to immersion cooling as refrigerant is dielectric, and thermal resistance of grease between GPU and vapor chamber can be eliminated. On the other hand, wick redesign is necessary because thermal diffusion performance of the vapor chamber is greatly degraded due to the weaker surface tension. It is also revealed that evaporative heat transfer coefficient is decreased by making effective capillary diameter of wick smaller, therefore, the vapor chamber (and the wick) should be made thicker contrary to the conventional design. The air cooling limit is estimated to be increased by 5%, and for future work, is aimed to be doubled by applying to immersion cooling.
{"title":"An Enhanced Vapor Chamber using Dielectric Organic Refrigerant","authors":"M. Hachiya, M. Yoshikawa","doi":"10.23919/ICEP.2019.8733569","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733569","url":null,"abstract":"General purpose computing on GPU (Graphics Processing Units) is gaining momentum, however, GPU is reaching air cooling limit at the same time. As thermal resistance of GPU’s heat sink is already minimized, thermal resistance between GPU and heat sink is required to be reduced in order to overcome the air cooling limit. The present study investigates an enhanced vapor chamber using dielectric organic refrigerant in place of water as working fluid. It is important to increase evaporative heat transfer coefficient in order to reduce thermal resistance of a vapor chamber, and it is confirmed that evaporative heat transfer coefficient at the heat flux of GPU can be increased by utilizing refrigerant, because bubble generation frequency becomes significantly higher due to weaker surface tension although heat transfer quantity by generating a vapor bubble becomes smaller due to smaller thermal conductivity and specific heat. In addition, the presented vapor chamber can be applied to immersion cooling as refrigerant is dielectric, and thermal resistance of grease between GPU and vapor chamber can be eliminated. On the other hand, wick redesign is necessary because thermal diffusion performance of the vapor chamber is greatly degraded due to the weaker surface tension. It is also revealed that evaporative heat transfer coefficient is decreased by making effective capillary diameter of wick smaller, therefore, the vapor chamber (and the wick) should be made thicker contrary to the conventional design. The air cooling limit is estimated to be increased by 5%, and for future work, is aimed to be doubled by applying to immersion cooling.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124013394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733583
I. Masada, S. Fujii, S. Imazumi, K. Fujinami, Y. Kanechika, T. Nawata, M. Ueda
In order to investigate the possibility of high thermal conductivity material, composite resin sheets combining large grain size AlN filler and agglomerated BN filler were prepared and heat conductivity characteristics were evaluated. In combination with BN filler, the superiority of AlN filler to Al2O3 filler was confirmed. We investigated the influence of particle size and blending amount of AlN filler and sheet forming conditions and discussed the problem of high thermal conductivity.
{"title":"High thermal conductivity composite resin sheet filled with large diameter aluminum nitride and aggregated boron nitride","authors":"I. Masada, S. Fujii, S. Imazumi, K. Fujinami, Y. Kanechika, T. Nawata, M. Ueda","doi":"10.23919/ICEP.2019.8733583","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733583","url":null,"abstract":"In order to investigate the possibility of high thermal conductivity material, composite resin sheets combining large grain size AlN filler and agglomerated BN filler were prepared and heat conductivity characteristics were evaluated. In combination with BN filler, the superiority of AlN filler to Al2O3 filler was confirmed. We investigated the influence of particle size and blending amount of AlN filler and sheet forming conditions and discussed the problem of high thermal conductivity.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733604
Cheng-Ying Yang, Kuo-Shen Chen, Tian-Shian g Yang, T. Chiu, Ching-Jenq Ho
Wafer reconstitution fan-out is a vital process for serving as a buffer to decouple the processing developments between IC fabrication and electronics packaging. By this approach, the IC packaging is then independent from the chip processing. However, such a process brings numerous mechanical loadings during molding and curing phases. In this work, it is desired to examine the key factor of reconstituted wafer warpage by performing solid thermo-mechanical analyses. To have a deeper insight, simplified 2D and detailed 3D finite element analyses have been constructed to mimic the entire Recon process. Detail thermo-mechanical processing steps are then emulated by these finite element models. After model validation, systematic parametric studies are then performed to investigate the controlling factors for dominating the wafer warpage. The simulation results indicated that the thermal expansion coefficients and the Young’s modulus of molding compounds could be the dominated factor. By choosing compounds with more desirable above-mentioned mechanical properties, it is expected that a 20 to 30 percentage reduction of warpage can be achieved.
{"title":"Thermo-Mechanical Process Emulation and Sensitivity Analysis of Wafer Warpage after Reconstitution in Fan-out Packaging","authors":"Cheng-Ying Yang, Kuo-Shen Chen, Tian-Shian g Yang, T. Chiu, Ching-Jenq Ho","doi":"10.23919/ICEP.2019.8733604","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733604","url":null,"abstract":"Wafer reconstitution fan-out is a vital process for serving as a buffer to decouple the processing developments between IC fabrication and electronics packaging. By this approach, the IC packaging is then independent from the chip processing. However, such a process brings numerous mechanical loadings during molding and curing phases. In this work, it is desired to examine the key factor of reconstituted wafer warpage by performing solid thermo-mechanical analyses. To have a deeper insight, simplified 2D and detailed 3D finite element analyses have been constructed to mimic the entire Recon process. Detail thermo-mechanical processing steps are then emulated by these finite element models. After model validation, systematic parametric studies are then performed to investigate the controlling factors for dominating the wafer warpage. The simulation results indicated that the thermal expansion coefficients and the Young’s modulus of molding compounds could be the dominated factor. By choosing compounds with more desirable above-mentioned mechanical properties, it is expected that a 20 to 30 percentage reduction of warpage can be achieved.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129498561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733438
S. Maetani, N. Araki, Y. Kim, S. Kodama, T. Ohba
The material viscosities of permanent and temporary adhesives were examined using the rigid body pendulum method to reveal a suitable for the wafer bonding process at 100 °C. Properties suited for the debonding process The adhesive is applied to wafer-on-wafer (WOW) stacking with bumpless dual-damascene interconnect (via-last after bonding) technology, which enables multilevel stacking using ultra-thin wafers of several micrometers or less at low cost.
{"title":"New Adhesive Design and Evaluation for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration","authors":"S. Maetani, N. Araki, Y. Kim, S. Kodama, T. Ohba","doi":"10.23919/ICEP.2019.8733438","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733438","url":null,"abstract":"The material viscosities of permanent and temporary adhesives were examined using the rigid body pendulum method to reveal a suitable for the wafer bonding process at 100 °C. Properties suited for the debonding process The adhesive is applied to wafer-on-wafer (WOW) stacking with bumpless dual-damascene interconnect (via-last after bonding) technology, which enables multilevel stacking using ultra-thin wafers of several micrometers or less at low cost.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126105681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733443
Norimasa Fukazawa, Akira Murakawa, Wataru Fujikawa, Jun Shirakami
We propose a novel silver-seed semi-additive process (S-SAP) for fabricating electrical circuit of high quality. Thin coated silver layer is used as a conductive seed for plating and is easily removed by selective etching without defects of plated copper wirings. In this system, it was found that the reproducibility of the designed circuit design and the rectangular shape of the wiring are maintained. Therefore, this process has great advantages against the conventional MSAP utilizing copper seed. Here, we will report the results of demonstration of electrical circuit fabrication by silver-seed SAP and discuss the difference between the new process (S-SAP) and conventional Cu-MSAP.
{"title":"Novel Silver-seed Semi-Additive Process for High Quality Circuit Formation","authors":"Norimasa Fukazawa, Akira Murakawa, Wataru Fujikawa, Jun Shirakami","doi":"10.23919/ICEP.2019.8733443","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733443","url":null,"abstract":"We propose a novel silver-seed semi-additive process (S-SAP) for fabricating electrical circuit of high quality. Thin coated silver layer is used as a conductive seed for plating and is easily removed by selective etching without defects of plated copper wirings. In this system, it was found that the reproducibility of the designed circuit design and the rectangular shape of the wiring are maintained. Therefore, this process has great advantages against the conventional MSAP utilizing copper seed. Here, we will report the results of demonstration of electrical circuit fabrication by silver-seed SAP and discuss the difference between the new process (S-SAP) and conventional Cu-MSAP.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122002193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advancement of technology and the electronics is getting smaller and smaller, the probability of being affected by electrostatic discharge (ESD) has also increased. The failure and destruction of electronic products caused by high voltage input, which was because of being touched by human or the machine during the processes of production or transportation, make lifetime of products decrease greatly and cost of production increase. Consequently, the design of electrostatic discharge protection circuit for system-level circuit is getting more and more important. The main purpose of this paper is to analyze the effect of the application of energy band gap (EBG) to electrostatic discharge protection.
{"title":"Effect Analysis of Application of Energy Band Gap to Electrostatic Discharge Protection","authors":"Hong-Yin Hsieh, Jheng-Yuan Ruan, Min-Jun Guo, Wei-chiao Wang, Sheng-Wei Guan, S. Wu","doi":"10.23919/ICEP.2019.8733475","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733475","url":null,"abstract":"With the advancement of technology and the electronics is getting smaller and smaller, the probability of being affected by electrostatic discharge (ESD) has also increased. The failure and destruction of electronic products caused by high voltage input, which was because of being touched by human or the machine during the processes of production or transportation, make lifetime of products decrease greatly and cost of production increase. Consequently, the design of electrostatic discharge protection circuit for system-level circuit is getting more and more important. The main purpose of this paper is to analyze the effect of the application of energy band gap (EBG) to electrostatic discharge protection.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131894374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.4071/2380-4505-2018.1.000153
S. Endo, Shintaro Yabu, Tomoyuki Habu
The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process "Integrated dry process" using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove a smear remaining behind in the via bottom by Photodesmear. Furthermore, we improved adhesion between copper metal and epoxy resin in a sputtering seed together. We made the large experimental tool that Photodesmear could process an actually size of the print circuit board by static irradiation. And we proved that handling of panel size was technically possible. The connection reliability of the contact via is evaluated after electric copper plating by quick via peel examination. I made a cross section sample of the via and, about the smear removal properties of wet desmear processing and the Photodesmear processing, was compared with the residual smear and the oxidation thin layer by the observation of the connection interface. The interfacial surface state after the desmear processing was analyzed in X-ray probe analyzer. We produced the test vehicle using Photodesmear technology and a sputtering seed technology. We compared it with the same pattern sample produced by a process conventionally. In this paper, we report the result of the high accelerated temperature and humidity stress test.
{"title":"Result of high accelerated stress test of organic substrate made by integrated dry process","authors":"S. Endo, Shintaro Yabu, Tomoyuki Habu","doi":"10.4071/2380-4505-2018.1.000153","DOIUrl":"https://doi.org/10.4071/2380-4505-2018.1.000153","url":null,"abstract":"The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process \"Integrated dry process\" using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove a smear remaining behind in the via bottom by Photodesmear. Furthermore, we improved adhesion between copper metal and epoxy resin in a sputtering seed together. We made the large experimental tool that Photodesmear could process an actually size of the print circuit board by static irradiation. And we proved that handling of panel size was technically possible. The connection reliability of the contact via is evaluated after electric copper plating by quick via peel examination. I made a cross section sample of the via and, about the smear removal properties of wet desmear processing and the Photodesmear processing, was compared with the residual smear and the oxidation thin layer by the observation of the connection interface. The interfacial surface state after the desmear processing was analyzed in X-ray probe analyzer. We produced the test vehicle using Photodesmear technology and a sputtering seed technology. We compared it with the same pattern sample produced by a process conventionally. In this paper, we report the result of the high accelerated temperature and humidity stress test.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128637507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since the Copper resistivity is second lowest next to the Silver, the Copper electrodeposits have been very intensively used in the wiring for the semiconductor and the printed circuit board(PCB). The Copper problem is the thermal coefficient of expansion(TCE). The Silicon is 2x10−6(1/K) and the copper is 18x10−6. If the composite of the Silicon and the Copper(semiconductor and PCB), warpage, protrusion or delamination occurs. Warpage, protrusion or delamination resolution are reported for the cases of Through Silicon Via(TSV), Glass interposer, Insulated Gate Bipolar Transistor(IGBT), Coreless Printed Circuit board(PCB) and IGBT packaging
{"title":"What Happens To Low TCE Copper With Annealing","authors":"K. Kondo","doi":"10.1149/08608.0023ECST","DOIUrl":"https://doi.org/10.1149/08608.0023ECST","url":null,"abstract":"Since the Copper resistivity is second lowest next to the Silver, the Copper electrodeposits have been very intensively used in the wiring for the semiconductor and the printed circuit board(PCB). The Copper problem is the thermal coefficient of expansion(TCE). The Silicon is 2x10−6(1/K) and the copper is 18x10−6. If the composite of the Silicon and the Copper(semiconductor and PCB), warpage, protrusion or delamination occurs. Warpage, protrusion or delamination resolution are reported for the cases of Through Silicon Via(TSV), Glass interposer, Insulated Gate Bipolar Transistor(IGBT), Coreless Printed Circuit board(PCB) and IGBT packaging","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124276758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-04-20DOI: 10.23919/ICEP.2019.8733511
I. Weng, H. Hung, Szu-Chi Yang, Y. H. Chen, C. Kao
Nowadays, many research groups are developing low-temperature and pressureless copper-to-copper interconnection bonding methods. Among them, controlled flow electroless nickel plating, which utilizes the feature of autocatalysis of electroless plating to join copper pillars, is the most promising one [1]. However, for high frequency application, nickel is a ferromagnetic material and would trigger skin effect seriously, which could greatly reduce the effective area for signal to pass through. To deal with this issue, other electroless plating materials needs to be investigated.Among them, copper is a suitable material for interconnection due to its excellent electrical conductivity. Previously, the chip-to-substrate all-copper connections were formed by joining the two pillars with electroless copper plating followed by an annealing process at 180°C [2]. Although the anneal process could enhance the bond strength up to 148MPa, it contradicts the advantage of electroless plating process, which is a low temperature process. In this research, to avoid the post annealing process, we conducted the electroless copper plating under controlled flow to fabricate the interconnection. All the process temperature in our research is below 50°C. The bonding result is very well without any extraneous deposition.
{"title":"Bonding of Copper Pillars Using Electroless Cu Plating","authors":"I. Weng, H. Hung, Szu-Chi Yang, Y. H. Chen, C. Kao","doi":"10.23919/ICEP.2019.8733511","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733511","url":null,"abstract":"Nowadays, many research groups are developing low-temperature and pressureless copper-to-copper interconnection bonding methods. Among them, controlled flow electroless nickel plating, which utilizes the feature of autocatalysis of electroless plating to join copper pillars, is the most promising one [1]. However, for high frequency application, nickel is a ferromagnetic material and would trigger skin effect seriously, which could greatly reduce the effective area for signal to pass through. To deal with this issue, other electroless plating materials needs to be investigated.Among them, copper is a suitable material for interconnection due to its excellent electrical conductivity. Previously, the chip-to-substrate all-copper connections were formed by joining the two pillars with electroless copper plating followed by an annealing process at 180°C [2]. Although the anneal process could enhance the bond strength up to 148MPa, it contradicts the advantage of electroless plating process, which is a low temperature process. In this research, to avoid the post annealing process, we conducted the electroless copper plating under controlled flow to fabricate the interconnection. All the process temperature in our research is below 50°C. The bonding result is very well without any extraneous deposition.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120837979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：