Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733543
Feng Xue, Joe Zou, Cindy Han, C. Reynolds, T. Wassick, Glenn Pomerantz, Jason L. Frankel, R. Bonam, C. Woychik, M. Tsuriya
The demand for integrated silicon packages is driving packaging advancements for increasingly fine circuit pattern designs. Due to the thinner copper and finer features required for advanced packaging, copper line defects can significantly impact yield and reliability. Industry Automated Optical Inspection (AOI) capabilities for packaging features are reaching detection limits.Phase One of the iNEMI metrology project surveyed industry capability and completed a gap analysis. This work established the basis for the current activities in Phase Two. A fine featured test vehicle was designed and fabricated using thin film processing technologies on both glass and silicon substrates to evaluate and assess the limits of today’s AOI metrology equipment. The test vehicle also provided a platform to develop future metrology capability required to close the technical gaps with respect to product requirements and process and material capabilities.The test vehicle samples were provided to various industrial AOI equipment suppliers to evaluate their capabilities in evaluating fine lines and spaces. The integrity of the fine wiring lines and spaces was compared between a control pattern and known defects utilizing wiring patterns from 10 μm lines and spaces to 1 μm lines and spaces. Various types of features including different orientations were evaluated: a) Line width violations; b) Spacing violations; c) Excess copper or missing copper; d) Shorts; e) Opens. This paper will review the details of the Phase Two test vehicle and the results from the AOI evaluations, and present a roadmap for the next phase of the study with test vehicles on organic substrates.
{"title":"Inspection / Metrology Evaluation of Fine Pitch Test Vehicles for Advanced Packages","authors":"Feng Xue, Joe Zou, Cindy Han, C. Reynolds, T. Wassick, Glenn Pomerantz, Jason L. Frankel, R. Bonam, C. Woychik, M. Tsuriya","doi":"10.23919/ICEP.2019.8733543","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733543","url":null,"abstract":"The demand for integrated silicon packages is driving packaging advancements for increasingly fine circuit pattern designs. Due to the thinner copper and finer features required for advanced packaging, copper line defects can significantly impact yield and reliability. Industry Automated Optical Inspection (AOI) capabilities for packaging features are reaching detection limits.Phase One of the iNEMI metrology project surveyed industry capability and completed a gap analysis. This work established the basis for the current activities in Phase Two. A fine featured test vehicle was designed and fabricated using thin film processing technologies on both glass and silicon substrates to evaluate and assess the limits of today’s AOI metrology equipment. The test vehicle also provided a platform to develop future metrology capability required to close the technical gaps with respect to product requirements and process and material capabilities.The test vehicle samples were provided to various industrial AOI equipment suppliers to evaluate their capabilities in evaluating fine lines and spaces. The integrity of the fine wiring lines and spaces was compared between a control pattern and known defects utilizing wiring patterns from 10 μm lines and spaces to 1 μm lines and spaces. Various types of features including different orientations were evaluated: a) Line width violations; b) Spacing violations; c) Excess copper or missing copper; d) Shorts; e) Opens. This paper will review the details of the Phase Two test vehicle and the results from the AOI evaluations, and present a roadmap for the next phase of the study with test vehicles on organic substrates.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126449929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733490
Runhua Gao, Jiahui Li, Yu-An Shen, H. Nishikawa
Many power semiconductor devices now require high tolerance of current density and reliability at high temperature, therefore Cu-Cu bonding using an insert material has raised the level of concerns for its great thermal stability and conductivity. In this study, a low-pressure bonding process was developed to achieve a Cu-Cu bonding using preoxidized Cu microparticles under formic acid atmosphere. The Cu microparticles were preoxidized to generate oxide films and Cu oxide nanostructures, which were then reduced and bonded at 300 °C under formic acid atmosphere to achieve a Cu-Cu bonding. Shear strength of the Cu-Cu bondings were tested to optimize the parameters of bonding process. Fracture surfaces of the Cu-Cu bonding, as well as cross-sectional microstructures, were observed by scanning electrical microscope (SEM) and components were identified by X-ray diffraction (XRD) to investigate the bonding mechanism. The findings reveal that the oxide films and the nanostructures play key roles in this reduction bonding process, which is a promising method to obtain a Cu-Cu bonding satisfying the requirements of power device packaging.
{"title":"A Cu-Cu Bonding Method Using Preoxidized Cu Microparticles under Formic Acid Atmosphere","authors":"Runhua Gao, Jiahui Li, Yu-An Shen, H. Nishikawa","doi":"10.23919/ICEP.2019.8733490","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733490","url":null,"abstract":"Many power semiconductor devices now require high tolerance of current density and reliability at high temperature, therefore Cu-Cu bonding using an insert material has raised the level of concerns for its great thermal stability and conductivity. In this study, a low-pressure bonding process was developed to achieve a Cu-Cu bonding using preoxidized Cu microparticles under formic acid atmosphere. The Cu microparticles were preoxidized to generate oxide films and Cu oxide nanostructures, which were then reduced and bonded at 300 °C under formic acid atmosphere to achieve a Cu-Cu bonding. Shear strength of the Cu-Cu bondings were tested to optimize the parameters of bonding process. Fracture surfaces of the Cu-Cu bonding, as well as cross-sectional microstructures, were observed by scanning electrical microscope (SEM) and components were identified by X-ray diffraction (XRD) to investigate the bonding mechanism. The findings reveal that the oxide films and the nanostructures play key roles in this reduction bonding process, which is a promising method to obtain a Cu-Cu bonding satisfying the requirements of power device packaging.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130951927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733578
Junya Maki, T. Matsuzoe, M. Kozako, M. Hikita, Y. Nakamura, K. Taniguchi, Y. Ikeda, K. Okamoto
This paper reports on construction and verification of a high space resolution partial discharge (PD) location system for the next generation power module. A novel PD location method (polarity reversion method) is proposed by calculating electromagnetic wave (EMW) propagation characteristics inside the power module using finite difference time domain (FDTD) analysis. In addition, EMW signal characteristics under AC voltage and impulse voltage application are compared. Based on these results, an automatic PD location system has been successfully constructed under the impulse voltage application.
{"title":"Construction and Verification of Novel Insulation Defect Location System with High Space Resolution for Next Generation Power Module","authors":"Junya Maki, T. Matsuzoe, M. Kozako, M. Hikita, Y. Nakamura, K. Taniguchi, Y. Ikeda, K. Okamoto","doi":"10.23919/ICEP.2019.8733578","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733578","url":null,"abstract":"This paper reports on construction and verification of a high space resolution partial discharge (PD) location system for the next generation power module. A novel PD location method (polarity reversion method) is proposed by calculating electromagnetic wave (EMW) propagation characteristics inside the power module using finite difference time domain (FDTD) analysis. In addition, EMW signal characteristics under AC voltage and impulse voltage application are compared. Based on these results, an automatic PD location system has been successfully constructed under the impulse voltage application.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126708794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733433
Y. Kitahara, Joonhaeng Kang
For advanced connecting reliability in micro-via holes, we have newly developed the electroless copper plating solution and investigated the features of the solution. With the conventional electroless copper plating solution containing nickel, when the thickness of electroless copper plating films is very small, the throwing power have dropped at the bottom corners of the micro-via holes; besides, the electrical resistance of the seed layers has increased at the same areas. With the developed solution without nickel but containing agents, it is possible to secure a low sheet resistance and high throwing power in micro- via holes; besides, high thermal resistance can be obtained after soldering because copper crystalline structure continues from the inner copper foil.
{"title":"Effects of electroless copper plating on crystal continuity in via bottom","authors":"Y. Kitahara, Joonhaeng Kang","doi":"10.23919/ICEP.2019.8733433","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733433","url":null,"abstract":"For advanced connecting reliability in micro-via holes, we have newly developed the electroless copper plating solution and investigated the features of the solution. With the conventional electroless copper plating solution containing nickel, when the thickness of electroless copper plating films is very small, the throwing power have dropped at the bottom corners of the micro-via holes; besides, the electrical resistance of the seed layers has increased at the same areas. With the developed solution without nickel but containing agents, it is possible to secure a low sheet resistance and high throwing power in micro- via holes; besides, high thermal resistance can be obtained after soldering because copper crystalline structure continues from the inner copper foil.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122411233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A precise and efficient method to analyze surface oxide using FTIR and electrochemical reduction was successfully developed in this study. Systematic analyses on surface oxide layer of commercial Cu-Fe-Zn-P (C194) lead frames demonstrate that this integrated analytical method can be applied to decide the variation in oxide type from top surface to subsurface and corresponding layer thickness. The results turned out to be in good agreement with XPS and TEM data.
{"title":"Surface Analyses of Oxidized Cu-Fe-Zn-P Lead Frames","authors":"Shi Chao, Jen-Hsiang Liu, Wei-Chen Huang, Jenn-Ming Song, Po-Yen Shen, Chi-Lin Huang, Lung-Tang Hung, Chin-Huang Chang","doi":"10.23919/ICEP.2019.8733471","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733471","url":null,"abstract":"A precise and efficient method to analyze surface oxide using FTIR and electrochemical reduction was successfully developed in this study. Systematic analyses on surface oxide layer of commercial Cu-Fe-Zn-P (C194) lead frames demonstrate that this integrated analytical method can be applied to decide the variation in oxide type from top surface to subsurface and corresponding layer thickness. The results turned out to be in good agreement with XPS and TEM data.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733407
F. Mu, Hui Ren, Lei Liu, Yinghui Wang, G. Zou, T. Suga
A low temperature all-Cu bonding via the sintering of nano-Cu paste in Pt-catalyzed formic acid vapor was studied, which was demonstrated with a large tolerance of surface oxidation. The bonding strength of oxidized-Cu to Cu could be significantly improved via the treatment of Pt-catalyzed formic acid vapor. The interfacial analysis was carried out to understand the mechanisms.
{"title":"Nano-Cu paste sintering in Pt-catalyzed formic acid vapor for Cu bonding at a low temperature","authors":"F. Mu, Hui Ren, Lei Liu, Yinghui Wang, G. Zou, T. Suga","doi":"10.23919/ICEP.2019.8733407","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733407","url":null,"abstract":"A low temperature all-Cu bonding via the sintering of nano-Cu paste in Pt-catalyzed formic acid vapor was studied, which was demonstrated with a large tolerance of surface oxidation. The bonding strength of oxidized-Cu to Cu could be significantly improved via the treatment of Pt-catalyzed formic acid vapor. The interfacial analysis was carried out to understand the mechanisms.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121382458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733519
H. Mizusaki, Toshiro Sato, M. Sonehara
The high-melting point solder, approximately 300°C, is often used for assembling reflow-capable devices. When thermally sensitive devices such as PZT sensors with a Curie temperature of approximately 250 °C are encased in a package using solder, the temperature inside the package must be below 250 °C and precisely measured to avoid thermal damage. In this study, the authors proposed a novel in-situ temperature measurement method inside the package based on a chip-sized thermometer. A new soldering method using a micro-heater was developed to heat solder locally without overheating inside the package. In the conventional soldering method of heating the whole package, the temperature inside the package reached 260 °C; in the new soldering method, it was kept to 180 °C. Moreover, the temperature distribution inside the package was examined in detail by transient heat transfer analysis. The analysis results were in agreement with the experimental results using the two soldering methods. From the analysis results, it was found that the electrically conductive vias inside the package assisted in the transfer of heat to the solder and a Si lid played a role as the heat transfer path.
{"title":"Au–Sn Soldering Using a Micro-heater to Restrain Excess Temperature Rise Inside the Package","authors":"H. Mizusaki, Toshiro Sato, M. Sonehara","doi":"10.23919/ICEP.2019.8733519","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733519","url":null,"abstract":"The high-melting point solder, approximately 300°C, is often used for assembling reflow-capable devices. When thermally sensitive devices such as PZT sensors with a Curie temperature of approximately 250 °C are encased in a package using solder, the temperature inside the package must be below 250 °C and precisely measured to avoid thermal damage. In this study, the authors proposed a novel in-situ temperature measurement method inside the package based on a chip-sized thermometer. A new soldering method using a micro-heater was developed to heat solder locally without overheating inside the package. In the conventional soldering method of heating the whole package, the temperature inside the package reached 260 °C; in the new soldering method, it was kept to 180 °C. Moreover, the temperature distribution inside the package was examined in detail by transient heat transfer analysis. The analysis results were in agreement with the experimental results using the two soldering methods. From the analysis results, it was found that the electrically conductive vias inside the package assisted in the transfer of heat to the solder and a Si lid played a role as the heat transfer path.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116793024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733542
Natsuki Suzuki, T. Ohba
This paper describes a technique for minimizing damage during singulation of wafers using a laser dicing method called Stealth Dicing. We developed a TEG wafer, having multiple wiring lines of Ti/TiN/AlCu layers, to monitor laser damage. The wiring lines were designed so that the change in wiring resistance caused by scattered light could be measured. Laser damage evaluation was carried out at a laser light wavelength of 1342 nm, which has high transmittance in Si wafers. We confirmed that the width of the laser-damaged region could be suppressed to less than 20 μm by optimizing the laser focal position and laser power. By applying this Stealth Dicing technology, damage-free dicing can be achieved, and high-yield singulation for mass production can be expected.
{"title":"Suppression of Backside Damage in Stealth Dicing","authors":"Natsuki Suzuki, T. Ohba","doi":"10.23919/ICEP.2019.8733542","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733542","url":null,"abstract":"This paper describes a technique for minimizing damage during singulation of wafers using a laser dicing method called Stealth Dicing. We developed a TEG wafer, having multiple wiring lines of Ti/TiN/AlCu layers, to monitor laser damage. The wiring lines were designed so that the change in wiring resistance caused by scattered light could be measured. Laser damage evaluation was carried out at a laser light wavelength of 1342 nm, which has high transmittance in Si wafers. We confirmed that the width of the laser-damaged region could be suppressed to less than 20 μm by optimizing the laser focal position and laser power. By applying this Stealth Dicing technology, damage-free dicing can be achieved, and high-yield singulation for mass production can be expected.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115596583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.23919/ICEP.2019.8733558
Shingo Otake, Y. Tateishi, H. Gohara, R. Kato, Y. Ikeda, V. Parque, Muhammed Khairi Faiz, M. Yoshida, T. Miyashita
In recent years, there have been increasing the number of power modules which is required with high performance, miniaturization and weight saving. But these requires cause high heat generation density for power module, which gets junction operation temperature to rise. Cooling unit is thus greatly demanded for high heat dissipation. The simple shaped heatsinks (straight-fin type and pin fin type) were generally used. But they have the limit of cooling performance. In this report, we have developed new heatsink shape to cope with rapidly increasing of the cooling requirement. Cooling performance is shown to thermal resistance and pressure loss. We evaluated them by thermal fluid analysis. In this approach, the spiral-fin heatsink with spiral curved channels has excellent cooling performance. This shape is the unique point in this report. This is because the shape with three-dimensional regular curve has not been studied. The spiral-fin heatsink has many factors (fin thickness, fin pitch, the number of channels, etc.). These factors affect cooler performance. We changed these factors to determine the best shape of spiral-fin. As a result, the best shape is 14.9[%] lower than the straight-fin type in thermal resistance.
{"title":"Heatsink design using spiral-fins considering additive manufacturing","authors":"Shingo Otake, Y. Tateishi, H. Gohara, R. Kato, Y. Ikeda, V. Parque, Muhammed Khairi Faiz, M. Yoshida, T. Miyashita","doi":"10.23919/ICEP.2019.8733558","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733558","url":null,"abstract":"In recent years, there have been increasing the number of power modules which is required with high performance, miniaturization and weight saving. But these requires cause high heat generation density for power module, which gets junction operation temperature to rise. Cooling unit is thus greatly demanded for high heat dissipation. The simple shaped heatsinks (straight-fin type and pin fin type) were generally used. But they have the limit of cooling performance. In this report, we have developed new heatsink shape to cope with rapidly increasing of the cooling requirement. Cooling performance is shown to thermal resistance and pressure loss. We evaluated them by thermal fluid analysis. In this approach, the spiral-fin heatsink with spiral curved channels has excellent cooling performance. This shape is the unique point in this report. This is because the shape with three-dimensional regular curve has not been studied. The spiral-fin heatsink has many factors (fin thickness, fin pitch, the number of channels, etc.). These factors affect cooler performance. We changed these factors to determine the best shape of spiral-fin. As a result, the best shape is 14.9[%] lower than the straight-fin type in thermal resistance.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127318849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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