Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733597
N. Iwamuro
SiC MOSFET device is a one of superior candidates as next power semiconductor device structure for many power transform systems. Owing to high requirement of stability for the whole application systems, it is essential to explore the optimized structures and operations for SiC MOSFETs with not only the extremely low on resistance but also much higher reliability. In this paper, an overview on recent device technologies of SiC MOSFETs is introduced.
SiC MOSFET器件是许多功率转换系统中下一代功率半导体器件结构的首选器件之一。由于整个应用系统对稳定性的要求很高，因此探索具有极低导通电阻和更高可靠性的SiC mosfet的优化结构和操作是非常必要的。本文综述了近年来碳化硅mosfet的器件技术。
{"title":"Recent Progress of SiC-MOSFETs and Their Futures-Competion with state-of-the-art Si-IGBT-","authors":"N. Iwamuro","doi":"10.23919/ICEP.2019.8733597","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733597","url":null,"abstract":"SiC MOSFET device is a one of superior candidates as next power semiconductor device structure for many power transform systems. Owing to high requirement of stability for the whole application systems, it is essential to explore the optimized structures and operations for SiC MOSFETs with not only the extremely low on resistance but also much higher reliability. In this paper, an overview on recent device technologies of SiC MOSFETs is introduced.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123455998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733408
Masaya Tanaka, T. Takano, Yumi Okazaki
We studied the fundamental characteristics of two type passive elements of the integrated passive devices (IPDs) configuration with electromagnetic field analysis and measurement. One is 3D solenoid coil using through glass via (TGV), and another is metal insulator metal (MIM) structured capacitor with inorganic dielectric thin film. Our developed 3D TGV inductor achieved high Q factor by optimizing of solenoid coil design. And our developed MIM capacitor indicates high breakdown voltage by controlling surface roughness condition of metal pad. Furthermore, we demonstrated band pass filter design that passes 2.4GHz to 2.5GHz with the combination of these IPDs. From this evaluation, our developed glass interposer (GiP) with filter function with IPDs achieved very small size, low height and better electrical characteristics compared with conventional LTCC component.
{"title":"Design demonstration of band-pass-filter characteristics with integrated passive device on glass interposer","authors":"Masaya Tanaka, T. Takano, Yumi Okazaki","doi":"10.23919/ICEP.2019.8733408","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733408","url":null,"abstract":"We studied the fundamental characteristics of two type passive elements of the integrated passive devices (IPDs) configuration with electromagnetic field analysis and measurement. One is 3D solenoid coil using through glass via (TGV), and another is metal insulator metal (MIM) structured capacitor with inorganic dielectric thin film. Our developed 3D TGV inductor achieved high Q factor by optimizing of solenoid coil design. And our developed MIM capacitor indicates high breakdown voltage by controlling surface roughness condition of metal pad. Furthermore, we demonstrated band pass filter design that passes 2.4GHz to 2.5GHz with the combination of these IPDs. From this evaluation, our developed glass interposer (GiP) with filter function with IPDs achieved very small size, low height and better electrical characteristics compared with conventional LTCC component.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123354322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733484
T. Blank, V. Dudek, M. Luh, B. An, H. Wurst, B. Leyrer, D. Ishikawa, Marc Weber
This paper describes the properties of GaAs PIN power diodes and demonstrates their utilization in a 650V 10kW LLC converter for fast charging of electric vehicles. The module comprises two SiC MOSFET half-bridges equipped with Rohm S4101 MOSFETs and the GaAs rectifier module packaged in an EconoPACK2 housing. The SiC half-brides and the GaAs rectifier are assembled on 0.38 mm thick zirconia-toughened alumina (ZTA) substrate with a bending strength of 700 MPa and a thermal conductivity of 27 W/mK. The SiC and GaAs semiconductors are silver-sintered onto a 0.3 mm measuring copper thick film layer on the top and bottom side of the substrate. The substrate is pressure sintered by a novel low temperature copper paste to the three mm thick copper base plate. The bow of the base plate with copper sintered substrates measures 200 μm and is comparable to the bow of soldered substrates. The thermal resistance of the GaAs module is calculated to 0.73 K/W. First electrical measurement at an output power of 0.5 kW reveal the extremely fast switching characteristic of the diode, which were validated by double pulse measurements.
{"title":"GaAs Diode Rectifier Power Module in mixed Ag- and Large Area Cu-Sintering Technology for Ultra-Fast and Wireless Electric Vehicle Battery Charging","authors":"T. Blank, V. Dudek, M. Luh, B. An, H. Wurst, B. Leyrer, D. Ishikawa, Marc Weber","doi":"10.23919/ICEP.2019.8733484","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733484","url":null,"abstract":"This paper describes the properties of GaAs PIN power diodes and demonstrates their utilization in a 650V 10kW LLC converter for fast charging of electric vehicles. The module comprises two SiC MOSFET half-bridges equipped with Rohm S4101 MOSFETs and the GaAs rectifier module packaged in an EconoPACK2 housing. The SiC half-brides and the GaAs rectifier are assembled on 0.38 mm thick zirconia-toughened alumina (ZTA) substrate with a bending strength of 700 MPa and a thermal conductivity of 27 W/mK. The SiC and GaAs semiconductors are silver-sintered onto a 0.3 mm measuring copper thick film layer on the top and bottom side of the substrate. The substrate is pressure sintered by a novel low temperature copper paste to the three mm thick copper base plate. The bow of the base plate with copper sintered substrates measures 200 μm and is comparable to the bow of soldered substrates. The thermal resistance of the GaAs module is calculated to 0.73 K/W. First electrical measurement at an output power of 0.5 kW reveal the extremely fast switching characteristic of the diode, which were validated by double pulse measurements.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133074369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733450
Ryuta Ikoma, K. Mawatari, Koji Hashimoto, J. Sato, Nobuyoshi Wakasugi
In order to achieve the stress free structure of the sensor chip, it is necessary to remove the epoxy molding compound (EMC) around the sensor chip. However, removing the EMC close to the sensor chip may damage the sensor chip, and it adversely affects the sensor characteristics. Therefore, it is necessary to develop the processing method that can remove only EMC without damaging the sensor chip. As the processing method, Er:YAG laser is adopted by focusing on the difference of energy absorption rate vs. wavelength between the sensor chip and the EMC. In order to measure the difference of energy absorption rate vs. the laser wavelength, FT-IR was selected Moreover, a laser energy distribution was visualized by a laser beam analysis of a spherical aberration characteristic, and the damaged zone of the sensor chip and the removed zone of the EMC within the laser spot diameter were clarified. With 2940nm wavelength Er:YAG, energy absorption rate of the sensor chip is 12.7% and that of the EMC is 95.5%. From this result, it is estimated that the resin close to the sensor chip can be removed due to high energy absorption rate and the sensor chip is not damaged due to low energy absorption rate. In addition, by visualizing the energy distribution of the laser, the focus position is considered to achieve both the selective removal and a processing time. As a result, selective removal can be achieved by setting the focus position to 0.4 mm out of focus side.
{"title":"Selective removal by laser processing for the sensor mold","authors":"Ryuta Ikoma, K. Mawatari, Koji Hashimoto, J. Sato, Nobuyoshi Wakasugi","doi":"10.23919/ICEP.2019.8733450","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733450","url":null,"abstract":"In order to achieve the stress free structure of the sensor chip, it is necessary to remove the epoxy molding compound (EMC) around the sensor chip. However, removing the EMC close to the sensor chip may damage the sensor chip, and it adversely affects the sensor characteristics. Therefore, it is necessary to develop the processing method that can remove only EMC without damaging the sensor chip. As the processing method, Er:YAG laser is adopted by focusing on the difference of energy absorption rate vs. wavelength between the sensor chip and the EMC. In order to measure the difference of energy absorption rate vs. the laser wavelength, FT-IR was selected Moreover, a laser energy distribution was visualized by a laser beam analysis of a spherical aberration characteristic, and the damaged zone of the sensor chip and the removed zone of the EMC within the laser spot diameter were clarified. With 2940nm wavelength Er:YAG, energy absorption rate of the sensor chip is 12.7% and that of the EMC is 95.5%. From this result, it is estimated that the resin close to the sensor chip can be removed due to high energy absorption rate and the sensor chip is not damaged due to low energy absorption rate. In addition, by visualizing the energy distribution of the laser, the focus position is considered to achieve both the selective removal and a processing time. As a result, selective removal can be achieved by setting the focus position to 0.4 mm out of focus side.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125063107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733602
Michitaka Yamamoto, T. Matsumae, Y. Kurashima, H. Takagi, T. Miyake, T. Suga, T. Itoh, E. Higurashi
Wafer-scale surface activated bonding (SAB) using intermediate layers of ultra-thin Au films was performed by using glow-discharge-type atmospheric-pressure (AP) plasma with a direct plasma system. The entire process, from surface activation to bonding, was performed in ambient air using AP plasma. While partial wafer bonding was obtained with 2.5 s plasma treatment, strong bonding was obtained with both 10 s and 30 s plasma treatment, and the Si substrates were sometimes broken in a razor blade test.
{"title":"Wafer-scale Au-Au surface activated bonding using atmospheric-pressure plasma","authors":"Michitaka Yamamoto, T. Matsumae, Y. Kurashima, H. Takagi, T. Miyake, T. Suga, T. Itoh, E. Higurashi","doi":"10.23919/ICEP.2019.8733602","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733602","url":null,"abstract":"Wafer-scale surface activated bonding (SAB) using intermediate layers of ultra-thin Au films was performed by using glow-discharge-type atmospheric-pressure (AP) plasma with a direct plasma system. The entire process, from surface activation to bonding, was performed in ambient air using AP plasma. While partial wafer bonding was obtained with 2.5 s plasma treatment, strong bonding was obtained with both 10 s and 30 s plasma treatment, and the Si substrates were sometimes broken in a razor blade test.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116999103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733598
Ken Yamamoto, Takuro Suyama, Noriyuki Fujimori
This study focuses on optimization of wafer thinning process by reducing the thickness variation of the temporary adhesive layer. To optimize edge trimming parameters, we evaluated the edge bead height and the width of the adhesive layer coated on the device wafer. After optimizing edge trimming parameters, the thickness distribution of the device wafer and the adhesive layer after thinning was evaluated. There was no difference in the thickness distribution of the device wafer and the adhesive layer after thinning regardless of whatever the edge trimming was applied or not. In contrast, peeling occurred at the edge of the bonded wafer only in the wafer without edge trimming. By measuring the surface shape of the glass wafer at the edge part, it was found that the wafer without edge trimming had a larger deflection than the wafer with edge trimming. Edge trimming is conventionally performed to prevent an edge chipping. Moreover, it has been confirmed that it is also effective to prevent a peeling of a wafer from a supporting substrate.
{"title":"Optimization of Wafer Thinning Process by Reducing Thickness Variation of Temporary Adhesive Layer for Medical Device","authors":"Ken Yamamoto, Takuro Suyama, Noriyuki Fujimori","doi":"10.23919/ICEP.2019.8733598","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733598","url":null,"abstract":"This study focuses on optimization of wafer thinning process by reducing the thickness variation of the temporary adhesive layer. To optimize edge trimming parameters, we evaluated the edge bead height and the width of the adhesive layer coated on the device wafer. After optimizing edge trimming parameters, the thickness distribution of the device wafer and the adhesive layer after thinning was evaluated. There was no difference in the thickness distribution of the device wafer and the adhesive layer after thinning regardless of whatever the edge trimming was applied or not. In contrast, peeling occurred at the edge of the bonded wafer only in the wafer without edge trimming. By measuring the surface shape of the glass wafer at the edge part, it was found that the wafer without edge trimming had a larger deflection than the wafer with edge trimming. Edge trimming is conventionally performed to prevent an edge chipping. Moreover, it has been confirmed that it is also effective to prevent a peeling of a wafer from a supporting substrate.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124038675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733522
Chun-Yi Chen, Junrong Zheng, Kai-Po Hsu, C. Chung
In this study, the silicon-base net-like hollow nano-structure were prepared using single-nozzle electrospinning and heat treatment process. Firstly, a precursor solution is prepared by dissolving an appropriate amount of Polyvinylpyrrolidone (PVP) and Tetraethyl orthosilicate (TEOS) in ethanol and spinning the nanofibers using a single -nozzle electrospinning. Secondly, the morphology of electrospinning nanofibers was controlled, the temperature profile was designed to prepare hollow nanofibers, and the morphology and properties of nanofibers were explored. Molding with traditional methods, such as rapid freezing, 3D printing, and sintering. It is almost impossible to prepare fibers with diameters less than 1 μm. The electrospinning technology is simple in its production process and cab increase the hollow, high length, uniform diameter, and diverse components of the nano-fiber.Finally, the characteristic of nanofibers, following instruments were used: Atomic force microscopy (AFM), Field Emission Scanning Electron Microscope (FE-SEM), Transmission electron microscopy (TEM), X-ray Diffract-ion(XRD). The AFM was used to scan the nanofibers, and 3D Graphics was used to explore the surface morphology of fibers. Using FE-SEM and TEM system is to explore the morphology, diameter of nanofibers, and hollow nanofiber . The electrospinning technique followed by subsequent heat treatment is well developed so that we can successfully prepare silicon-based oxide nanofibers with the hollow structure. Thus, the microstructure and morphology of electrostatic spinning silicon-base oxide hollow nanofibers were explored, and also their crystalline properties and crystal structure were identified.
{"title":"A Hollow Nanostructure of Silicon-Based can be produced by Using Electrospinning process","authors":"Chun-Yi Chen, Junrong Zheng, Kai-Po Hsu, C. Chung","doi":"10.23919/ICEP.2019.8733522","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733522","url":null,"abstract":"In this study, the silicon-base net-like hollow nano-structure were prepared using single-nozzle electrospinning and heat treatment process. Firstly, a precursor solution is prepared by dissolving an appropriate amount of Polyvinylpyrrolidone (PVP) and Tetraethyl orthosilicate (TEOS) in ethanol and spinning the nanofibers using a single -nozzle electrospinning. Secondly, the morphology of electrospinning nanofibers was controlled, the temperature profile was designed to prepare hollow nanofibers, and the morphology and properties of nanofibers were explored. Molding with traditional methods, such as rapid freezing, 3D printing, and sintering. It is almost impossible to prepare fibers with diameters less than 1 μm. The electrospinning technology is simple in its production process and cab increase the hollow, high length, uniform diameter, and diverse components of the nano-fiber.Finally, the characteristic of nanofibers, following instruments were used: Atomic force microscopy (AFM), Field Emission Scanning Electron Microscope (FE-SEM), Transmission electron microscopy (TEM), X-ray Diffract-ion(XRD). The AFM was used to scan the nanofibers, and 3D Graphics was used to explore the surface morphology of fibers. Using FE-SEM and TEM system is to explore the morphology, diameter of nanofibers, and hollow nanofiber . The electrospinning technique followed by subsequent heat treatment is well developed so that we can successfully prepare silicon-based oxide nanofibers with the hollow structure. Thus, the microstructure and morphology of electrostatic spinning silicon-base oxide hollow nanofibers were explored, and also their crystalline properties and crystal structure were identified.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127965992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733599
Yu-Jin Li, W. Hsu, B. Lin, Chia-Cheng Chang, Chih Chen
In the present paper, the nt-Cu were electroplated on the InFO test vehicles with 5 μm line width to compare the reliability with the normal electroplated copper. The temperature of the TCT ranges from -55 to 125°C. The microstructure of the copper traces after 200 cycles and 1000 cycles was shown in the results. The nt-Cu RDL is much stronger than the normal Cu in the thermal cycling test. In order to understand the mechanical property of the nt-Cu and the normal Cu, tensile tests of electroplated copper foils was employed. After annealing at 250°C for 3 hours, the toughness of nt-Cu (about 60MJ/m3) is much higher than normal copper (about 30MJ/m3). In addition, the simulation results shows that the maximum stress on the copper trace during the TCT is about 200MPa which is much lower than the yield point of nt-Cu. In other word, the nt-Cu would return to original size when the stress removed without strain accumulation. In summary, we observed that the nt-Cu performs much better than normal copper in TCT. From the tensile test and simulation, we can understand the mechanical behavior and the typical reason for the high reliability of nt-Cu.
{"title":"High-toughness (111) nano-twinned copper lines for fan-out wafer-level packaging","authors":"Yu-Jin Li, W. Hsu, B. Lin, Chia-Cheng Chang, Chih Chen","doi":"10.23919/ICEP.2019.8733599","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733599","url":null,"abstract":"In the present paper, the nt-Cu were electroplated on the InFO test vehicles with 5 μm line width to compare the reliability with the normal electroplated copper. The temperature of the TCT ranges from -55 to 125°C. The microstructure of the copper traces after 200 cycles and 1000 cycles was shown in the results. The nt-Cu RDL is much stronger than the normal Cu in the thermal cycling test. In order to understand the mechanical property of the nt-Cu and the normal Cu, tensile tests of electroplated copper foils was employed. After annealing at 250°C for 3 hours, the toughness of nt-Cu (about 60MJ/m3) is much higher than normal copper (about 30MJ/m3). In addition, the simulation results shows that the maximum stress on the copper trace during the TCT is about 200MPa which is much lower than the yield point of nt-Cu. In other word, the nt-Cu would return to original size when the stress removed without strain accumulation. In summary, we observed that the nt-Cu performs much better than normal copper in TCT. From the tensile test and simulation, we can understand the mechanical behavior and the typical reason for the high reliability of nt-Cu.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133755054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733595
Naohiro Matsuda, N. Okamoto, Takeyasu Saito
These days, development of new photocatalyst materials have been interested, which can absorb visible light and have photocatalytic activities towards various reaction. In this study, we focused on ZnS as a new photocatalyst material. We prepared ZnS by electrodeposition. At first, we tried to synthesis ZnS with different electrolytic bathes in terms of additive composition and pH. Comparing the properties of samples, the best bath condition was containing EDTA and adjusting pH to 2.00. Secondly, we tried to make the band gap energy of ZnS small by Cu doping. We prepared 3 different bathes in terms of the concentration of Cu; the ratio of Cu to Zn was 1 mol%, 5 mol% and 10 mol% (Cu1, Cu5 and Cu10). The band gap energy of the samples were 2.6 eV, 2.8 eV and 2.4 eV, respectively. The bandgap energy of ZnS without Cu was 3.6 eV, so we assumed that Cu played the role of making band gap energy narrow. According to the XPS analysis, the chemical state of Cu was Cu(metal), CuO, CuS, Cu2O and Cu2S. The chemical state of Zn was Zn(metal), ZnO, ZnS, and Cu10 contains larger amount of ZnS than Cu1 and Cu5. The results of cyclic voltammetory implied that formation of ZnS was suppressed in Cu1 and Cu5. Band gap energy of Cu doped ZnS was 2.8 eV for Cu1, 2.4 eV for Cu5 and 2.6 eV for Cu10, and all of them can absorb visible light(λ < 500 nm). The conduction band potential of Cu1, Cu5 and Cu10 was more highly negative than TiO2 one. It implies that Cu doped ZnS would have stronger phothocatalytic activity for reduction than TiO2 one.
{"title":"Electrodeposition of Cu doped ZnS and evaluation of its photocatalytic property","authors":"Naohiro Matsuda, N. Okamoto, Takeyasu Saito","doi":"10.23919/ICEP.2019.8733595","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733595","url":null,"abstract":"These days, development of new photocatalyst materials have been interested, which can absorb visible light and have photocatalytic activities towards various reaction. In this study, we focused on ZnS as a new photocatalyst material. We prepared ZnS by electrodeposition. At first, we tried to synthesis ZnS with different electrolytic bathes in terms of additive composition and pH. Comparing the properties of samples, the best bath condition was containing EDTA and adjusting pH to 2.00. Secondly, we tried to make the band gap energy of ZnS small by Cu doping. We prepared 3 different bathes in terms of the concentration of Cu; the ratio of Cu to Zn was 1 mol%, 5 mol% and 10 mol% (Cu1, Cu5 and Cu10). The band gap energy of the samples were 2.6 eV, 2.8 eV and 2.4 eV, respectively. The bandgap energy of ZnS without Cu was 3.6 eV, so we assumed that Cu played the role of making band gap energy narrow. According to the XPS analysis, the chemical state of Cu was Cu(metal), CuO, CuS, Cu2O and Cu2S. The chemical state of Zn was Zn(metal), ZnO, ZnS, and Cu10 contains larger amount of ZnS than Cu1 and Cu5. The results of cyclic voltammetory implied that formation of ZnS was suppressed in Cu1 and Cu5. Band gap energy of Cu doped ZnS was 2.8 eV for Cu1, 2.4 eV for Cu5 and 2.6 eV for Cu10, and all of them can absorb visible light(λ < 500 nm). The conduction band potential of Cu1, Cu5 and Cu10 was more highly negative than TiO2 one. It implies that Cu doped ZnS would have stronger phothocatalytic activity for reduction than TiO2 one.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123046246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-17DOI: 10.23919/ICEP.2019.8733518
Cheng-Yu Ho, Sheng-Chi Hsieh, Ming-Fong Jhong, H. Kuo, Chun-Yen Ting, Chen-Chao Wang
This work proposes a low-cost Antenna in package (AiP) solution implemented on Advanced single sided substrates (aS3 package) for 77-GHz automotive radar applications. The impact of fabrication tolerances is also studied in this work. This work demonstrates firstly the 77-GHz losses of the transition from chip to package among flip-chip ball grid array (FCBGA) package, flip chip chip scale (FCCSP) package, Fan out wafer level chip scale package (Fan-out WLP), and aS3 package. Although Fan-out WLP can minimizes 77-GHz losses of transition from chip to package plus package to PCB, low-cost AiP solutions are very important for 77-GHz automotive radar applications. The proposed AiP solution on aS3 package has low losses of transition from chip to package, and the performance of designed antenna on aS3 package meets the requirements of 77-GHz automotive radar systems. Finally, this work also demonstrates the impact of fabrication inaccuracies on the bandwidth and radiation pattern of AiP on aS3 package. This work provides a cost-effective AiP approach for 77-GHz automotive radar systems.
{"title":"A Low-Cost Antenna-in-Package Solution for 77GHz Automotive Radar Applications","authors":"Cheng-Yu Ho, Sheng-Chi Hsieh, Ming-Fong Jhong, H. Kuo, Chun-Yen Ting, Chen-Chao Wang","doi":"10.23919/ICEP.2019.8733518","DOIUrl":"https://doi.org/10.23919/ICEP.2019.8733518","url":null,"abstract":"This work proposes a low-cost Antenna in package (AiP) solution implemented on Advanced single sided substrates (aS3 package) for 77-GHz automotive radar applications. The impact of fabrication tolerances is also studied in this work. This work demonstrates firstly the 77-GHz losses of the transition from chip to package among flip-chip ball grid array (FCBGA) package, flip chip chip scale (FCCSP) package, Fan out wafer level chip scale package (Fan-out WLP), and aS3 package. Although Fan-out WLP can minimizes 77-GHz losses of transition from chip to package plus package to PCB, low-cost AiP solutions are very important for 77-GHz automotive radar applications. The proposed AiP solution on aS3 package has low losses of transition from chip to package, and the performance of designed antenna on aS3 package meets the requirements of 77-GHz automotive radar systems. Finally, this work also demonstrates the impact of fabrication inaccuracies on the bandwidth and radiation pattern of AiP on aS3 package. This work provides a cost-effective AiP approach for 77-GHz automotive radar systems.","PeriodicalId":213025,"journal":{"name":"2019 International Conference on Electronics Packaging (ICEP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130182868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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