Pub Date : 2024-08-27DOI: 10.1088/1361-6641/ad68a0
Weihao Lu, Sheng Li, Ran Ye, Weixiong Mao, Zikang Zhang, Yanfeng Ma, Mingfei Li, Jiaxing Wei, Long Zhang, Jie Ma, Siyang Liu, Weifeng Sun
In this paper, the robustness of a junction temperature sensing method using the peak of the turn-on current slope for enhanced p-GaN high-electron-mobility transistors is investigated in detail. With the help of a repetitive hard-switching test platform, compared to other temperature-sensitive electrical parameters, it is found that the maximum slope of the flowing current at the turn-on transition shows no trend in degradation, regardless of the applied switching stress. This parameter decreases solely with the increase in junction temperature, showing excellent temperature-dependent linearity. Furthermore, the applicability of this method to the detection of junction temperature under different external gate resistances and drain voltages is verified. The sensed junction temperatures are carried over to calculate the thermal resistance, which is also extracted by advanced thermal characterization test equipment as a reference. Therefore, based on the versatility, convenience and accuracy, the peak of the rising drain current slope has been proven to be the preferred alternative in system applications to detect junction temperatures.
{"title":"Investigations into the robustness of the peak turn-on current slope method for junction temperature sensing in p-GaN HEMTs","authors":"Weihao Lu, Sheng Li, Ran Ye, Weixiong Mao, Zikang Zhang, Yanfeng Ma, Mingfei Li, Jiaxing Wei, Long Zhang, Jie Ma, Siyang Liu, Weifeng Sun","doi":"10.1088/1361-6641/ad68a0","DOIUrl":"https://doi.org/10.1088/1361-6641/ad68a0","url":null,"abstract":"In this paper, the robustness of a junction temperature sensing method using the peak of the turn-on current slope for enhanced p-GaN high-electron-mobility transistors is investigated in detail. With the help of a repetitive hard-switching test platform, compared to other temperature-sensitive electrical parameters, it is found that the maximum slope of the flowing current at the turn-on transition shows no trend in degradation, regardless of the applied switching stress. This parameter decreases solely with the increase in junction temperature, showing excellent temperature-dependent linearity. Furthermore, the applicability of this method to the detection of junction temperature under different external gate resistances and drain voltages is verified. The sensed junction temperatures are carried over to calculate the thermal resistance, which is also extracted by advanced thermal characterization test equipment as a reference. Therefore, based on the versatility, convenience and accuracy, the peak of the rising drain current slope has been proven to be the preferred alternative in system applications to detect junction temperatures.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-27DOI: 10.1088/1361-6641/ad6eaf
Hemant K Arora, Nikita Jain, Sunil Kumar, Nitin K Puri
Detection of ethanol gas quickly and efficiently at room temperature is crucial for ensuring environmental, human as well as industrial safety. In this work, we have demonstrated a chemiresistive room temperature ethanol gas sensor based on vertically aligned tin sulfide (SnS) nanoplates. X-ray diffraction (XRD), field-emission scanning electron microscopy (FESEM), and Brunauer–Emmett–Teller (BET) analysis have revealed the formation of orthorhombic, vertically aligned SnS nanoplates with high specific surface area. The sensor has been fabricated by depositing the SnS powder sample on ITO sheets using electrophoretic deposition (EPD), followed by the deposition of silver (Ag) electrodes using the thermal evaporation technique. The sensor obtained has exhibited a response value (Rg/Ra) of 17.4–400 ppm ethanol gas concentration, a quick response, and a recovery time of 12.4 s and 20.2 s at room temperature. The sensor has demonstrated long-term stability of 15 min, impressive selectivity, and remarkable repeatability across three successive test cycles of ethanol gas at 400 ppm. Based on the experimental sensing results, a plausible mechanism has been proposed for the sensor. The sensing response of SnS-based sensor at room temperature expands its potential for innovative applications across industries, marking a significant advancement in sensing technology.
{"title":"Vertically aligned 2D tin sulfide (SnS) nanoplates for selective detection of ethanol gas at room temperature","authors":"Hemant K Arora, Nikita Jain, Sunil Kumar, Nitin K Puri","doi":"10.1088/1361-6641/ad6eaf","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6eaf","url":null,"abstract":"Detection of ethanol gas quickly and efficiently at room temperature is crucial for ensuring environmental, human as well as industrial safety. In this work, we have demonstrated a chemiresistive room temperature ethanol gas sensor based on vertically aligned tin sulfide (SnS) nanoplates. X-ray diffraction (XRD), field-emission scanning electron microscopy (FESEM), and Brunauer–Emmett–Teller (BET) analysis have revealed the formation of orthorhombic, vertically aligned SnS nanoplates with high specific surface area. The sensor has been fabricated by depositing the SnS powder sample on ITO sheets using electrophoretic deposition (EPD), followed by the deposition of silver (Ag) electrodes using the thermal evaporation technique. The sensor obtained has exhibited a response value (<italic toggle=\"yes\">R</italic><sub>g</sub>/<italic toggle=\"yes\">R</italic><sub>a</sub>) of 17.4–400 ppm ethanol gas concentration, a quick response, and a recovery time of 12.4 s and 20.2 s at room temperature. The sensor has demonstrated long-term stability of 15 min, impressive selectivity, and remarkable repeatability across three successive test cycles of ethanol gas at 400 ppm. Based on the experimental sensing results, a plausible mechanism has been proposed for the sensor. The sensing response of SnS-based sensor at room temperature expands its potential for innovative applications across industries, marking a significant advancement in sensing technology.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-22DOI: 10.1088/1361-6641/ad6e15
Jeevan Battini, Sivani Kosaraju
Conventional carry select adders (CCSA) have two stages and are followed by multiplexers. CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry propagation. To choose the option between an excess-1 result and a normal result, the CCSA employs a multiplexer. The proposed single-stage carry select adder (SSCSA) has a single stage and uses a new block to generate a normal and excess-1 result based on the readily available inputs (A and B). A novel architecture is developed and specifically designed to improve power dissipation and latency. It relies on a single circuit that produces normal/excess-1 results dependent on input carry. Heterogeneous logic combining CMOS, Dual Value Logic, and Transmission Gate Logic with 22 nm Fin-FETs powers the 1-bit SSCSA circuit. Better circuit regularity is displayed by the 4-bit SSCSA, as it only uses one type of 1-bit SSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22 nm FinFET technology, all adders, including 4- and 8-bit adders, are designed, simulated, and examined. According to the resulting study, the 4-bit SSCSA outperforms the best adder among existing adders in terms of speed performance and power dissipation by 17.6% and 27.6%, respectively. By comparison with all other designs, SSCSAs outperform them at every corner.
{"title":"An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology","authors":"Jeevan Battini, Sivani Kosaraju","doi":"10.1088/1361-6641/ad6e15","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6e15","url":null,"abstract":"Conventional carry select adders (CCSA) have two stages and are followed by multiplexers. CCSAs use ripple carry adders at two stages, which will introduce much delay due to carry propagation. To choose the option between an excess-1 result and a normal result, the CCSA employs a multiplexer. The proposed single-stage carry select adder (SSCSA) has a single stage and uses a new block to generate a normal and excess-1 result based on the readily available inputs (A and B). A novel architecture is developed and specifically designed to improve power dissipation and latency. It relies on a single circuit that produces normal/excess-1 results dependent on input carry. Heterogeneous logic combining CMOS, Dual Value Logic, and Transmission Gate Logic with 22 nm Fin-FETs powers the 1-bit SSCSA circuit. Better circuit regularity is displayed by the 4-bit SSCSA, as it only uses one type of 1-bit SSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22 nm FinFET technology, all adders, including 4- and 8-bit adders, are designed, simulated, and examined. According to the resulting study, the 4-bit SSCSA outperforms the best adder among existing adders in terms of speed performance and power dissipation by 17.6% and 27.6%, respectively. By comparison with all other designs, SSCSAs outperform them at every corner.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The negative capacitance (NC) tunnel FET (NCTFET) emerges as a viable choice for the development of highly sensitive biosensors. A dual-gate (DG) structure and n+ doped pocket within the NCTFET is introduced in this study to boost biosensor performance and sensitivity. This research offers a comprehensive and comparative analysis of two biosensor designs: the DG-NCTFET and the n+ pocket-doped DG-NCTFET. Both biosensors feature nanogaps on either side of the fixed dielectric, augmenting their biomolecule capture areas. Sensitivity assessments are conducted considering charged and neutral biomolecules with a range of dielectric constants (k). The n+ pocket DG-NCTFET exhibits an ION sensitivity roughly 20 times greater than that of the sensor without a pocket (3.5 × 106 for n+ pocket DG-NCTFET and 1.8 × 105 for DG-NCTFET), primarily because it conducts current in both vertical and lateral directions. Furthermore, for fully filled nanocavity with neutral biomolecules, the maximum ION/IOFF sensitivities attained are 1.2 × 105 and 2.8 × 104 for the n+ pocket DG-NCTFET and conventional DG-NCTFET, respectively. Moreover, this research delves into the impact of steric hindrance and the irregular placement of probes, aiming to grasp the non-ideal traits exhibited by the sensors. Significantly, sensitivity experiences a minimal increase of approximately 6%–11% when the fill factor escalates from 40% to 66%. In order to set a standard of comparison, the proposed biosensors are benchmarked against existing literature in terms of sensitivity, affirming their efficacy. The findings indicate that the proposed biosensors represent a promising alternative for detecting a wide range of both charged and neutral biomolecules.
{"title":"A novel dual-gate negative capacitance TFET for highly sensitive label free biosensing","authors":"Ravindra Kumar Maurya, Radhe Gobinda Debnath, Ajeet Kumar Yadav, Brinda Bhowmick","doi":"10.1088/1361-6641/ad6eb0","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6eb0","url":null,"abstract":"The negative capacitance (NC) tunnel FET (NCTFET) emerges as a viable choice for the development of highly sensitive biosensors. A dual-gate (DG) structure and n+ doped pocket within the NCTFET is introduced in this study to boost biosensor performance and sensitivity. This research offers a comprehensive and comparative analysis of two biosensor designs: the DG-NCTFET and the n+ pocket-doped DG-NCTFET. Both biosensors feature nanogaps on either side of the fixed dielectric, augmenting their biomolecule capture areas. Sensitivity assessments are conducted considering charged and neutral biomolecules with a range of dielectric constants (<italic toggle=\"yes\">k</italic>). The n+ pocket DG-NCTFET exhibits an <italic toggle=\"yes\">I</italic><sub>ON</sub> sensitivity roughly 20 times greater than that of the sensor without a pocket (3.5 × 10<sup>6</sup> for n+ pocket DG-NCTFET and 1.8 × 10<sup>5</sup> for DG-NCTFET), primarily because it conducts current in both vertical and lateral directions. Furthermore, for fully filled nanocavity with neutral biomolecules, the maximum <italic toggle=\"yes\">I</italic><sub>ON</sub>/<italic toggle=\"yes\">I</italic><sub>OFF</sub> sensitivities attained are 1.2 × 10<sup>5</sup> and 2.8 × 10<sup>4</sup> for the n+ pocket DG-NCTFET and conventional DG-NCTFET, respectively. Moreover, this research delves into the impact of steric hindrance and the irregular placement of probes, aiming to grasp the non-ideal traits exhibited by the sensors. Significantly, sensitivity experiences a minimal increase of approximately 6<bold>%–</bold>11% when the fill factor escalates from 40% to 66%. In order to set a standard of comparison, the proposed biosensors are benchmarked against existing literature in terms of sensitivity, affirming their efficacy. The findings indicate that the proposed biosensors represent a promising alternative for detecting a wide range of both charged and neutral biomolecules.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study provides an insight into the impact of thin purely undoped GaN channel thickness (tch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing tch of the undoped GaN channel. We show that by decreasing tch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing tch. Large-signal simulations revealed an increase by 3 W mm−1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN tch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.
本研究深入探讨了纯粹未掺杂氮化镓沟道薄厚度（tch）对氮化镓/氮化镓高电子迁移率晶体管中表面相关捕获效应的影响。我们的 TCAD 研究表明，在寄生栅极漏电是促进电子从肖特基栅极接触注入表面态的驱动捕获机制的情况下，可以通过减小未掺杂 GaN 沟道的 tch 来缓解这种效应。我们的研究表明，在特定的 B 类射频工作偏置条件下，通过将 tch 从 130 纳米减小到 10 纳米，器件与栅极相关的电流塌缩有所减小，这是因为随着 tch 的减小，离态栅极漏电流大幅减小。大信号模拟显示，由于栅极相关塌陷的减少，输出功率和功率附加效率分别提高了 3 W mm-1、约 12%。这项研究首次强调了在设计基于氮化镓的微波功率放大器时，正确选择纯非掺杂氮化镓的栅极弛豫时间对减轻栅极相关表面陷波的作用。
{"title":"A computational analysis of the impact of thin undoped channels in surface-related current collapse of AlGaN/GaN HEMTs","authors":"Christos Zervos, Petros Beleniotis, Matthias Rudolph","doi":"10.1088/1361-6641/ad689c","DOIUrl":"https://doi.org/10.1088/1361-6641/ad689c","url":null,"abstract":"This study provides an insight into the impact of thin purely undoped GaN channel thickness (<italic toggle=\"yes\">t</italic><sub>ch</sub>) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing <italic toggle=\"yes\">t</italic><sub>ch</sub> of the undoped GaN channel. We show that by decreasing <italic toggle=\"yes\">t</italic><sub>ch</sub> from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing <italic toggle=\"yes\">t</italic><sub>ch</sub>. Large-signal simulations revealed an increase by 3 W mm<sup>−1</sup> and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN <italic toggle=\"yes\">t</italic><sub>ch</sub> selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1088/1361-6641/ad689f
Zhaohui Qin, Lan Chen, Renjie Lu, Yali Wang, Xiaoran Hao, Rong Chen, Yan Sun, Qin Du
This work investigates the innovative design of a 14 nm bulk 3D non-rectangular structure fin field-effect transistor (FinFET). By incorporating a cylindrical trapezoidal structure into the upper portion of the FinFET, it transcend the limitations posed by the self-heating (SH) effect observed in traditional rectangular fins.Through the density gradient model and thermal conduction model, the changes in the electron carrier temperature and lattice temperature of the channel are studied, and the relationship between electrical properties and thermal resistance was further analyzed, revealing the effect of SH on the threshold voltage and switching speed of the device. In addition, the SH effect of the doping of source and drain extension regions was also explored, and the effects of electron mobility changes at different ambient temperatures were also studied to clarify their impact on the electrical properties. Ultimately, this work offers novel insights into the design, optimization, and reliability studies of device structures affected by SH effects.
这项研究探讨了 14 纳米大块三维非矩形结构鳍式场效应晶体管（FinFET）的创新设计。通过密度梯度模型和热传导模型，研究了电子载流子温度和沟道晶格温度的变化，并进一步分析了电性能和热阻之间的关系，揭示了 SH 对器件阈值电压和开关速度的影响。此外，还探讨了源极和漏极扩展区掺杂的 SH 效应，并研究了不同环境温度下电子迁移率变化的影响，以明确其对电学特性的影响。最终，这项工作为受 SH 效应影响的器件结构的设计、优化和可靠性研究提供了新的见解。
{"title":"Study on the regulation factors and mechanism of self-heating effects in non-rectangular 14 nm bulk FinFET*","authors":"Zhaohui Qin, Lan Chen, Renjie Lu, Yali Wang, Xiaoran Hao, Rong Chen, Yan Sun, Qin Du","doi":"10.1088/1361-6641/ad689f","DOIUrl":"https://doi.org/10.1088/1361-6641/ad689f","url":null,"abstract":"This work investigates the innovative design of a 14 nm bulk 3D non-rectangular structure fin field-effect transistor (FinFET). By incorporating a cylindrical trapezoidal structure into the upper portion of the FinFET, it transcend the limitations posed by the self-heating (SH) effect observed in traditional rectangular fins.Through the density gradient model and thermal conduction model, the changes in the electron carrier temperature and lattice temperature of the channel are studied, and the relationship between electrical properties and thermal resistance was further analyzed, revealing the effect of SH on the threshold voltage and switching speed of the device. In addition, the SH effect of the doping of source and drain extension regions was also explored, and the effects of electron mobility changes at different ambient temperatures were also studied to clarify their impact on the electrical properties. Ultimately, this work offers novel insights into the design, optimization, and reliability studies of device structures affected by SH effects.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1088/1361-6641/ad6c79
A Cristina Carranza, E Rosendo, H Pérez Ladrón de Guevara, C Morales, R Romano, G García, A Coyopol, R Galeazzi, J Zepeda
Aluminum-doped zinc oxide (AZO) thin films were deposited on glass substrates at room temperature by RF sputtering technique. Power ramps between 125 and 105 W were applied with a step of 4 W by intervals of 15, 7.5 and 1.8 min, for 180 min at 1.60 Pa. In this study, we investigated the structural, morphological, electrical, and optical properties of AZO films. X-ray Diffraction analysis showed that the films have a wurtzite-type hexagonal crystalline structure with a preferential crystallographic orientation (002) normal to the c axis. The average transmittance is greater than 76% for the wavelength range in the visible spectrum. The bandgap values were found between 3.32 and 4.01 eV, and refractive index was 1.79–2.60. Atomic force microscope measurements show homogeneous films with a roughness between 17–22 nm. A minimum resistivity value of 2.0 × 10−3 Ω cm was obtained for the film by using a power ramp of 4 W/1.8 min.
采用射频溅射技术在室温下将掺铝氧化锌（AZO）薄膜沉积在玻璃基底上。在 1.60 Pa 的条件下，以 15、7.5 和 1.8 分钟为间隔，施加 125 至 105 W 的功率斜坡，步长为 4 W，持续 180 分钟。在这项研究中，我们研究了 AZO 薄膜的结构、形态、电学和光学特性。X 射线衍射分析表明，薄膜具有钨锆石型六方晶体结构，晶体学取向（002）优先于 c 轴。在可见光谱的波长范围内，平均透射率大于 76%。带隙值介于 3.32 和 4.01 eV 之间，折射率为 1.79-2.60。原子力显微镜测量显示，薄膜均匀，粗糙度在 17-22 纳米之间。使用 4 W/1.8 分钟的斜坡功率，薄膜的电阻率最小值为 2.0 × 10-3 Ω cm。
{"title":"Influence of power ramps on the physical properties of AZO thin films deposited at room temperature by RF magnetron sputtering technique","authors":"A Cristina Carranza, E Rosendo, H Pérez Ladrón de Guevara, C Morales, R Romano, G García, A Coyopol, R Galeazzi, J Zepeda","doi":"10.1088/1361-6641/ad6c79","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6c79","url":null,"abstract":"Aluminum-doped zinc oxide (AZO) thin films were deposited on glass substrates at room temperature by RF sputtering technique. Power ramps between 125 and 105 W were applied with a step of 4 W by intervals of 15, 7.5 and 1.8 min, for 180 min at 1.60 Pa. In this study, we investigated the structural, morphological, electrical, and optical properties of AZO films. X-ray Diffraction analysis showed that the films have a wurtzite-type hexagonal crystalline structure with a preferential crystallographic orientation (002) normal to the <italic toggle=\"yes\">c</italic> axis. The average transmittance is greater than 76% for the wavelength range in the visible spectrum. The bandgap values were found between 3.32 and 4.01 eV, and refractive index was 1.79–2.60. Atomic force microscope measurements show homogeneous films with a roughness between 17–22 nm. A minimum resistivity value of 2.0 × 10<sup>−3</sup> Ω cm was obtained for the film by using a power ramp of 4 W/1.8 min.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142200381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-09DOI: 10.1088/1361-6641/ad6d86
K. Simonyan, Hermine Gharagulyan, Henrik Parsamyan, Ashot Khachatryan, M. Yeranosyan
The operation of the metasurface based on silicon cylindrical rings coated by a gold as a terahertz (THz) bandpass filter/antireflection structure is studied. The decrease in the reflectance is conditioned by the destructive interference of electromagnetic waves reflected from structural layers of the metasurface. An efficient antireflection band with the reflectance below 10% is formed in the frequency spectrum of 0.71 to 0.92 THz with a relative bandwidth of 26%. It is shown that the operating spectrum of the suggested metasurface can be varied by changing the total radius of cylindrical rings, whereas the filter's performance is rather insensitive to the variations in cylinder height and inner radius. The dependence of the antireflection band on the polarization and incidence angle of the THz waves is also analyzed. The antireflection band is sensitive to changes in the surrounding medium, hence supporting the use of the structure as a refractive index sensor.
{"title":"Broadband THz metasurface bandpass filter/antireflection coating based on metalized Si cylindrical rings","authors":"K. Simonyan, Hermine Gharagulyan, Henrik Parsamyan, Ashot Khachatryan, M. Yeranosyan","doi":"10.1088/1361-6641/ad6d86","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6d86","url":null,"abstract":"\u0000 The operation of the metasurface based on silicon cylindrical rings coated by a gold as a terahertz (THz) bandpass filter/antireflection structure is studied. The decrease in the reflectance is conditioned by the destructive interference of electromagnetic waves reflected from structural layers of the metasurface. An efficient antireflection band with the reflectance below 10% is formed in the frequency spectrum of 0.71 to 0.92 THz with a relative bandwidth of 26%. It is shown that the operating spectrum of the suggested metasurface can be varied by changing the total radius of cylindrical rings, whereas the filter's performance is rather insensitive to the variations in cylinder height and inner radius. The dependence of the antireflection band on the polarization and incidence angle of the THz waves is also analyzed. The antireflection band is sensitive to changes in the surrounding medium, hence supporting the use of the structure as a refractive index sensor.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141922575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-06DOI: 10.1088/1361-6641/ad689d
Aadil Anam, S Intekhab Amin and Dinesh Prasad
In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and high thermal budgets and streamlines the fabrication. The implementation of III–V compound material, i.e. low bandgap compound GaSb, in the source region, combined with the larger area gate normal line tunneling, improves the ON current for our proposed III–V JF L GNLTFET device. Additionally, the utilization of large bandgap GaAs compounds on the drain and channel sides eliminates ambipolarity and further enhances the performance of our proposed device. Meaning that the proposed device simultaneously improves the ON current and suppresses the ambipolarity. Our proposed III–V JF L GNLTFET exhibits enhanced output performance with an ON current of 23.2 μA μm−1 and a minimum and average subthreshold swing of 3.7 mV dec−1 and 15.82 mV dec−1 respectively. Furthermore, the proposed III–V JF L GNLTFET also gives superior RF/analog performance with transconductance (168.65 μS), cut-off frequency (33.52 GHz), gain-bandwidth product (5.11 GHz), and transconductance-frequency product (243.7 GHz).
本文介绍了一种基于 III-V 复合材料的新型无结 (JF) L 形栅极法线隧道场效应晶体管（III-V JF L GNLTFET），可提高 0.5 V 工作电压下的输出性能。我们器件的关键设计指标，即 JF 或无结设计，消除了随机掺杂波动 (RDF) 和高热预算等问题，并简化了制造过程。在源区采用 III-V 复合材料（即低带隙化合物 GaSb），结合大面积栅极法线隧道，提高了我们提出的 III-V JF L GNLTFET 器件的导通电流。此外，在漏极和沟道侧使用大带隙砷化镓化合物消除了伏极性，进一步提高了我们提出的器件的性能。这意味着所提出的器件能同时改善导通电流和抑制伏极性。我们提出的 III-V JF L GNLTFET 具有更高的输出性能，导通电流为 23.2 μA μm-1，最小和平均阈下摆幅分别为 3.7 mV dec-1 和 15.82 mV dec-1。此外，所提出的 III-V JF L GNLTFET 还具有出色的射频/模拟性能，包括跨导（168.65 μS）、截止频率（33.52 GHz）、增益带宽乘积（5.11 GHz）和跨导频率乘积（243.7 GHz）。
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Pub Date : 2024-07-25DOI: 10.1088/1361-6641/ad6477
Taoufik Chargui, Fatima Lmai, Mohamed Al-Hattab and Khalid Rahmani
Copper zinc tin sulfide (CZTS) thin-film solar cells have garnered significant attention in the solar energy sector. This study aims to enhance the performance of CZTS solar cells by replacing the conventional, toxic CdS buffer layer with (ZTO) for x = 0.2. Utilizing the one-dimensional solar cell capacitance simulator (SCAPS-1D) and informed by experimental data on the physical properties of the solar cell layers, we investigated the effects of thickness, doping density, and defect density of the CZTS absorber layer on the cell’s performance. Initially, an efficiency of 14.76% was achieved. To improve this efficiency, an inorganic back surface field (BSF) layer was incorporated to mitigate charge carrier recombination at the absorber/back contact metal interface. Various materials, including CuO, , Mo and Mo , were evaluated as potential BSF layers. Comparative analysis indicated that the inclusion of the BSF layer significantly enhances the solar cell efficiency, achieving up to 27% with as the BSF material. Furthermore, the study included an analysis of temperature effects and parasitic resistances to comprehensively assess the solar cell’s performance.
{"title":"Improving CZTS/ZTO solar cell efficiency with inorganic BSF layers","authors":"Taoufik Chargui, Fatima Lmai, Mohamed Al-Hattab and Khalid Rahmani","doi":"10.1088/1361-6641/ad6477","DOIUrl":"https://doi.org/10.1088/1361-6641/ad6477","url":null,"abstract":"Copper zinc tin sulfide (CZTS) thin-film solar cells have garnered significant attention in the solar energy sector. This study aims to enhance the performance of CZTS solar cells by replacing the conventional, toxic CdS buffer layer with (ZTO) for x = 0.2. Utilizing the one-dimensional solar cell capacitance simulator (SCAPS-1D) and informed by experimental data on the physical properties of the solar cell layers, we investigated the effects of thickness, doping density, and defect density of the CZTS absorber layer on the cell’s performance. Initially, an efficiency of 14.76% was achieved. To improve this efficiency, an inorganic back surface field (BSF) layer was incorporated to mitigate charge carrier recombination at the absorber/back contact metal interface. Various materials, including CuO, , Mo and Mo , were evaluated as potential BSF layers. Comparative analysis indicated that the inclusion of the BSF layer significantly enhances the solar cell efficiency, achieving up to 27% with as the BSF material. Furthermore, the study included an analysis of temperature effects and parasitic resistances to comprehensively assess the solar cell’s performance.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141770785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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