Pub Date : 2024-01-04DOI: 10.1088/1361-6641/ad1b15
Hyunjin Kim, Beom Jung Kim, Jungyeop Oh, Sung-Yool Choi, Hamin Park
Amorphous InGaZnO (a-IGZO) has attracted a lot of attention as a high-mobility channel material for thin film transistors (TFTs). However, the instability mechanism involving threshold voltage and subthreshold swing in a-IGZO TFTs still requires further investigation. In this study, we investigated the electrical instability of amorphous InGaZnO thin film transistors subjected to alternating positive and negative bias stresses. Based on the respective mechanisms under positive and negative bias stresses, including ionization and spatial movement of oxygen vacancies, bi-directional threshold voltage shifts were observed under alternating bias stress. The subthreshold swing values vary with the bias stress polarity, reflecting the presence and distribution of oxygen vacancies. Our findings reveal a complementary mechanism based on oxygen vacancies, elucidating the behavior under complex bias stress schemes and extending our understanding of instability mechanisms beyond monotonous bias stress.
{"title":"Bi-directional threshold voltage shift of amorphous InGaZnO thin film transistors under alternating bias stress","authors":"Hyunjin Kim, Beom Jung Kim, Jungyeop Oh, Sung-Yool Choi, Hamin Park","doi":"10.1088/1361-6641/ad1b15","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b15","url":null,"abstract":"\u0000 Amorphous InGaZnO (a-IGZO) has attracted a lot of attention as a high-mobility channel material for thin film transistors (TFTs). However, the instability mechanism involving threshold voltage and subthreshold swing in a-IGZO TFTs still requires further investigation. In this study, we investigated the electrical instability of amorphous InGaZnO thin film transistors subjected to alternating positive and negative bias stresses. Based on the respective mechanisms under positive and negative bias stresses, including ionization and spatial movement of oxygen vacancies, bi-directional threshold voltage shifts were observed under alternating bias stress. The subthreshold swing values vary with the bias stress polarity, reflecting the presence and distribution of oxygen vacancies. Our findings reveal a complementary mechanism based on oxygen vacancies, elucidating the behavior under complex bias stress schemes and extending our understanding of instability mechanisms beyond monotonous bias stress.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139384510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-04DOI: 10.1088/1361-6641/ad1b16
Hossein Yazdani, Andreas Thies, Paul Stützle, O. Bengtsson, Oliver Hilt, Wolfgang Heinrich, Joachim Wuerfl
This paper presents a novel approach for reducing the gate resistance (Rg) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH's Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μm to approximately 1.0 μm for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency (PAE) at 20 GHz and Vds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.
本文介绍了一种通过新型栅极金属化技术降低栅极长度为 150 nm 的 K 和 Ka 波段氮化镓高频晶体管栅极电阻 (Rg) 的新方法。该方法采用 FBH 的 Ir-sputter 栅极技术，通过电镀金属化增加栅极横截面，从而将所研究晶体管的栅极金属厚度从目前的 0.4 μm 增加到约 1.0 μm。这一优化使栅极串联电阻大幅降低了 50%，从而显著提高了射频性能。栅极电阻的减小为设计提供了新的自由度，如更长的栅极指和/或更短的栅极长度，从而实现在此频率范围内更高效的功率电池。
{"title":"Low-resistive gate module for RF GaN-HFETs by electroplating","authors":"Hossein Yazdani, Andreas Thies, Paul Stützle, O. Bengtsson, Oliver Hilt, Wolfgang Heinrich, Joachim Wuerfl","doi":"10.1088/1361-6641/ad1b16","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b16","url":null,"abstract":"\u0000 This paper presents a novel approach for reducing the gate resistance (Rg) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH's Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μm to approximately 1.0 μm for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency (PAE) at 20 GHz and Vds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139384456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-04DOI: 10.1088/1361-6641/ad1b14
Jizhi Liu, FEILONG YANG, YILIN LIU
Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 ℃ is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.
{"title":"A novel low trigger voltage low leakage SCR for low-voltage ESD protection","authors":"Jizhi Liu, FEILONG YANG, YILIN LIU","doi":"10.1088/1361-6641/ad1b14","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b14","url":null,"abstract":"\u0000 Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 ℃ is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-04DOI: 10.1088/1361-6641/ad1b18
Yujie Liu, Yang Wang, Jian Yang, Xiangliang Jin
The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic PNP transistors for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1), a 96.1% improvement in holding voltage (Vh), and achieves an equivalent Human Body Model (HBM) protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.
{"title":"Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip","authors":"Yujie Liu, Yang Wang, Jian Yang, Xiangliang Jin","doi":"10.1088/1361-6641/ad1b18","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b18","url":null,"abstract":"\u0000 The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic PNP transistors for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1), a 96.1% improvement in holding voltage (Vh), and achieves an equivalent Human Body Model (HBM) protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the physical vapor transport (PVT) growth of AlN, re-oxidation of aluminum nitride (AlN) source powder happening in the process of setting seed crystal into crucible seems to be unavoidable. This process introduces oxygen just before AlN growth and has a significant impact on the crystal quality. In this paper, a high and low-temperature alternative sintering method (HLAS) is proposed based on the idea of specific surface area control to reduce the re-oxidation of AlN source powder. This method introduces cyclic sintering between 1500°C and 1900°C to the conventional three-step treatment repeatedly, which utilizes possible phase-transition along with the processes of powder sintering back and forth to increase the particle size and decrease the specific surface area significantly. The SEM (Scanning electron microscope) and BET (Brunauer, Emmett, and Teller) results showed that the specific surface area of AlN powder treated with the HLAS method can be reduced to one-third of that with the conventional method. Thus, the SIMS (secondary ion mass spectrometry) confirmed the reduction of oxygen impurity in AlN single-crystals to a good level of 1.5×1017cm-3. It is clear that this HLAS process is an effective way of controlling the specific surface area of AlN source powder, which contributes to the suppression of oxygen influence on PVT-AlN growth.
{"title":"Oxygen reduction through specific surface area control of AlN powder for AlN single-crystal growth by physical vapor transport","authors":"ZeRen Wang, Xing-Yu Zhu, Qi-Yue Zhao, Jie-Jun Wu, Tongjun Yu","doi":"10.1088/1361-6641/ad1b13","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b13","url":null,"abstract":"\u0000 In the physical vapor transport (PVT) growth of AlN, re-oxidation of aluminum nitride (AlN) source powder happening in the process of setting seed crystal into crucible seems to be unavoidable. This process introduces oxygen just before AlN growth and has a significant impact on the crystal quality. In this paper, a high and low-temperature alternative sintering method (HLAS) is proposed based on the idea of specific surface area control to reduce the re-oxidation of AlN source powder. This method introduces cyclic sintering between 1500°C and 1900°C to the conventional three-step treatment repeatedly, which utilizes possible phase-transition along with the processes of powder sintering back and forth to increase the particle size and decrease the specific surface area significantly. The SEM (Scanning electron microscope) and BET (Brunauer, Emmett, and Teller) results showed that the specific surface area of AlN powder treated with the HLAS method can be reduced to one-third of that with the conventional method. Thus, the SIMS (secondary ion mass spectrometry) confirmed the reduction of oxygen impurity in AlN single-crystals to a good level of 1.5×1017cm-3. It is clear that this HLAS process is an effective way of controlling the specific surface area of AlN source powder, which contributes to the suppression of oxygen influence on PVT-AlN growth.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139385438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, electrical measurements on ferroelectric random-access memory by prior x-ray irradiation are conducted. Compared with an unirradiated device, parameters such as current leakage and remnant polarization of the irradiated device were unexpectedly improved. Besides, better reliabilities including the number of endurance times and retention time have also been demonstrated. To clarify the underlying physical mechanism, the electrical properties are analyzed. The current–voltage curve (I–V) implies a change in the grain size in the ferroelectric layer (FL), and the capacitance–voltage curve (C–V) profile indicates that the FL undergoes a phase change during irradiation. Finally, according to the electrical results, a physical model is proposed as an explanation.
本研究对铁电随机存取存储器进行了预先 X 射线辐照的电学测量。与未经过辐照的器件相比，经过辐照的器件的漏电流和残余极化等参数得到了意想不到的改善。此外，耐久次数和保持时间等可靠性也得到了改善。为了弄清潜在的物理机制，我们对其电气特性进行了分析。电流-电压曲线（I-V）表明铁电层（FL）的晶粒尺寸发生了变化，而电容-电压曲线（C-V）则表明 FL 在辐照过程中发生了相变。最后，根据电学结果，提出了一个物理模型作为解释。
{"title":"Phase transformation on HZO ferroelectric layer in ferroelectric random-access memory induced by x-ray irradiation","authors":"Chung-Wei Wu, Po-Hsun Chen, Ting-Chang Chang, Yung-Fang Tan, Shih-Kai Lin, Yu-Hsuan Yeh, Yong-Ci Zhang, Hsin-Ni Lin, Kai-Chun Chang, Chien-Hung Yeh, Simon Sze","doi":"10.1088/1361-6641/ad1130","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1130","url":null,"abstract":"In this study, electrical measurements on ferroelectric random-access memory by prior x-ray irradiation are conducted. Compared with an unirradiated device, parameters such as current leakage and remnant polarization of the irradiated device were unexpectedly improved. Besides, better reliabilities including the number of endurance times and retention time have also been demonstrated. To clarify the underlying physical mechanism, the electrical properties are analyzed. The current–voltage curve (<italic toggle=\"yes\">I–V</italic>) implies a change in the grain size in the ferroelectric layer (FL), and the capacitance–voltage curve (<italic toggle=\"yes\">C</italic>–<italic toggle=\"yes\">V</italic>) profile indicates that the FL undergoes a phase change during irradiation. Finally, according to the electrical results, a physical model is proposed as an explanation.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139102141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-04DOI: 10.1088/1361-6641/ad1b17
Jun Wang, R. Houdré
Suspended epitaxial gallium nitride (GaN) on silicon (Si) photonic crystal (PhC) devices suffer from large residual tensile strain, especially for long waveguides, because fine structures tend to crack due to large stress. By introducing spring-like tethers, designed by the combination of a spring network model and finite element method (FEM) simulations, the stress at critical locations was mitigated and the cracking issue was solved. Meanwhile, the tethered-beam structure was found to be potentially a powerful method for high-precision strain measurement in tensile thin films, and in this case, a strain of $2.27(pm0.01)times10^{-3}$ was measured in 350 nm epitaxial GaN-on-Si.
{"title":"Strain engineering and strain measurement by spring tethers on suspended epitaxial GaN-on-Si photonic crystal devices","authors":"Jun Wang, R. Houdré","doi":"10.1088/1361-6641/ad1b17","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1b17","url":null,"abstract":"\u0000 Suspended epitaxial gallium nitride (GaN) on silicon (Si) photonic crystal (PhC) devices suffer from large residual tensile strain, especially for long waveguides, because fine structures tend to crack due to large stress. By introducing spring-like tethers, designed by the combination of a spring network model and finite element method (FEM) simulations, the stress at critical locations was mitigated and the cracking issue was solved. Meanwhile, the tethered-beam structure was found to be potentially a powerful method for high-precision strain measurement in tensile thin films, and in this case, a strain of $2.27(pm0.01)times10^{-3}$ was measured in 350 nm epitaxial GaN-on-Si.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel 650 V Snapback-free Reverse-conducting Super-junction (SJ) insulated gate bipolar transistor (RC-SJBT) with low switching and reverse recovery loss is proposed and investigated in paper. In where, SJ pillar acts as the drift region, meanwhile PMOS and Schottky are combined on the cathode side. Under the action of SJ pillar, the snapback is effectively suppressed and Von−Eoff trade-off of IGBT is also improved. The PMOS and Schottky combined structure enhances on-state carriers of IGBT meanwhile reduces hole injection efficiency during reverse recovery of freewheel diode, thus the reverse recovery switching loss (Erec) of PMOS-RC-SJBT is reduced without sacrificing IGBT’s performance. Investigated by the TCAD tools, the total switching loss of PMOS-RC-SJBT is reduced by 51.2% from Con. RC-IGBT and 40.6% than the latest commercial RC-IGBT IKWH30N65WR6 of Infineon. Besides that, tsc is increased by 35.3% than RC-SJBT. Additionally, the snapback-free P-collector width is reduced from 340 µm of Con.RC-IGBT to 40 µm of PMOS-RC-SJBT, where the current uniformity is substantially improved.
{"title":"A novel 650 V snapback-free PMOS-RC-SJBT with low switching and reverse recovery losses","authors":"Yuanzhen Yang, Luping Li, Zehong Li, Qianshen Rao, Peng Chen, Min Ren","doi":"10.1088/1361-6641/ad112f","DOIUrl":"https://doi.org/10.1088/1361-6641/ad112f","url":null,"abstract":"A novel 650 V Snapback-free Reverse-conducting Super-junction (SJ) insulated gate bipolar transistor (RC-SJBT) with low switching and reverse recovery loss is proposed and investigated in paper. In where, SJ pillar acts as the drift region, meanwhile PMOS and Schottky are combined on the cathode side. Under the action of SJ pillar, the snapback is effectively suppressed and <inline-formula>\u0000<tex-math><?CDATA $V_{mathrm{on}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>V</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">o</mml:mi><mml:mi mathvariant=\"normal\">n</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn1.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula>−<inline-formula>\u0000<tex-math><?CDATA $E_{mathrm{off}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">o</mml:mi><mml:mi mathvariant=\"normal\">f</mml:mi><mml:mi mathvariant=\"normal\">f</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn2.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula> trade-off of IGBT is also improved. The PMOS and Schottky combined structure enhances on-state carriers of IGBT meanwhile reduces hole injection efficiency during reverse recovery of freewheel diode, thus the reverse recovery switching loss (<inline-formula>\u0000<tex-math><?CDATA $E_{mathrm{rec}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">r</mml:mi><mml:mi mathvariant=\"normal\">e</mml:mi><mml:mi mathvariant=\"normal\">c</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn3.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula>) of PMOS-RC-SJBT is reduced without sacrificing IGBT’s performance. Investigated by the TCAD tools, the total switching loss of PMOS-RC-SJBT is reduced by 51.2% from Con. RC-IGBT and 40.6% than the latest commercial RC-IGBT IKWH30N65WR6 of Infineon. Besides that, <inline-formula>\u0000<tex-math><?CDATA $t_{mathrm{sc}}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:msub><mml:mi>t</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant=\"normal\">s</mml:mi><mml:mi mathvariant=\"normal\">c</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad112fieqn4.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula> is increased by 35.3% than RC-SJBT. Additionally, the snapback-free P-collector width is reduced from 340 <italic toggle=\"yes\">µ</italic>m of Con.RC-IGBT to 40 <italic toggle=\"yes\">µ</italic>m of PMOS-RC-SJBT, where the current uniformity is substantially improved.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139053840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-15DOI: 10.1088/1361-6641/ad160d
Yingqiang Wei, Jinghe Wei, Wei Zhao, Suzhen Wu, Yidan Wei, Meijie Liu, Zhiyuan Sui, Ying Zhou, Yuqi Li, Hong Chang, Fei Ji, Weibin Wang, Lijun Yang, Guozhu Liu
We fabricated enhancement-mode p-GaN gate GaN HEMT with multiple field plates (MFPs) and analyzed the reliability of devices by means of simulation and experiment in this paper. The simulation of electric-field distribution indicates that the MFPs effectively weaken the electric field peak near gate to below theoretical breakdown value and smooth the electric field between the gate edge and drain-side field plate edge. The simulated electric field peak leading to the breakdown of device with MFPs at high drain voltage is located on drain edge, which is validated by experimental results. The GaN HEMTs with MFPs exhibit excellent long-term reliability under high temperature and high drain voltage, while deviations of threshold voltage and on-resistance were observed in the device subjected to drain stress. We attribute the deviations to electron accumulation and high field-assisted detrapping process in the p-GaN layer. This investigation will provide some new insight into understanding the mechanism of variations in threshold voltage and on-resistance under off-state drain stress.
本文制作了带有多场板（MFP）的增强型 p-GaN 栅极 GaN HEMT，并通过仿真和实验分析了器件的可靠性。电场分布仿真表明，多场板有效地削弱了栅极附近的电场峰值，使其低于理论击穿值，并使栅极边缘和漏极侧场板边缘之间的电场变得平滑。在高漏极电压下，导致带有 MFP 的器件击穿的模拟电场峰值位于漏极边缘，这也得到了实验结果的验证。带有 MFP 的 GaN HEMT 在高温和高漏极电压条件下表现出出色的长期可靠性，而在漏极应力作用下，器件的阈值电压和导通电阻出现了偏差。我们将这些偏差归因于 p-GaN 层中的电子积累和高场辅助脱离过程。这项研究将为理解离态漏极应力下阈值电压和导通电阻的变化机制提供一些新的见解。
{"title":"Reliability of enhancement-mode p-GaN gate GaN HEMT with multiple field plates","authors":"Yingqiang Wei, Jinghe Wei, Wei Zhao, Suzhen Wu, Yidan Wei, Meijie Liu, Zhiyuan Sui, Ying Zhou, Yuqi Li, Hong Chang, Fei Ji, Weibin Wang, Lijun Yang, Guozhu Liu","doi":"10.1088/1361-6641/ad160d","DOIUrl":"https://doi.org/10.1088/1361-6641/ad160d","url":null,"abstract":"\u0000 We fabricated enhancement-mode p-GaN gate GaN HEMT with multiple field plates (MFPs) and analyzed the reliability of devices by means of simulation and experiment in this paper. The simulation of electric-field distribution indicates that the MFPs effectively weaken the electric field peak near gate to below theoretical breakdown value and smooth the electric field between the gate edge and drain-side field plate edge. The simulated electric field peak leading to the breakdown of device with MFPs at high drain voltage is located on drain edge, which is validated by experimental results. The GaN HEMTs with MFPs exhibit excellent long-term reliability under high temperature and high drain voltage, while deviations of threshold voltage and on-resistance were observed in the device subjected to drain stress. We attribute the deviations to electron accumulation and high field-assisted detrapping process in the p-GaN layer. This investigation will provide some new insight into understanding the mechanism of variations in threshold voltage and on-resistance under off-state drain stress.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2023-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139000115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-12DOI: 10.1088/1361-6641/ad14ed
Yanji Wang, Yu Wang, Yi Liu, Yanzhong Zhang, Yu Yan, Youde Hu, Xinpeng Wang, Hao Zhang, Rongqing Xu, Yi Tong
In the context of sixth-generation (6G) wireless communications technology, advanced radio-frequency (RF) switches are required to accommodate high-frequency terahertz range and complex modulation techniques. This paper proposes a flexible charge-controlled memristor model specifically designed for ultra-high-frequency applications. It describes in detail the derivation of the behavior model of the proposed memristor circuit. The memristor circuit model is built around four inverters, two multipliers, one integrator, one adder, and one differentiator. Through PSPICE simulation, the typical hysteresis loop of the memristor is thoroughly analyzed, demonstrating its suitability for use in wireless communication systems. The model exhibits a good typical hysteresis loop that operates over a wide frequency range from 100 kHz to 20 THz, meeting the specific requirements of terahertz applications. Compared to existing memristor designs, it operates at a much higher frequency. However, the zero crossing of the typical hysteresis loop deviates when the operating frequency exceeds 20 THz. Furthermore, the proposed memristor model can be customized in terms of set/reset voltage, operating frequency and R_off⁄R_on , and has been verified for use in high speed switches with switching speeds of 19.5 ps. Furthermore, this research fills the gap in ultra-high-frequency memristor modeling, offering valuable insights and guidance for the utilization of memristors in the 6G technology and ultra-high frequency fields.
{"title":"An ultra-high-frequency memristor circuit model","authors":"Yanji Wang, Yu Wang, Yi Liu, Yanzhong Zhang, Yu Yan, Youde Hu, Xinpeng Wang, Hao Zhang, Rongqing Xu, Yi Tong","doi":"10.1088/1361-6641/ad14ed","DOIUrl":"https://doi.org/10.1088/1361-6641/ad14ed","url":null,"abstract":"\u0000 In the context of sixth-generation (6G) wireless communications technology, advanced radio-frequency (RF) switches are required to accommodate high-frequency terahertz range and complex modulation techniques. This paper proposes a flexible charge-controlled memristor model specifically designed for ultra-high-frequency applications. It describes in detail the derivation of the behavior model of the proposed memristor circuit. The memristor circuit model is built around four inverters, two multipliers, one integrator, one adder, and one differentiator. Through PSPICE simulation, the typical hysteresis loop of the memristor is thoroughly analyzed, demonstrating its suitability for use in wireless communication systems. The model exhibits a good typical hysteresis loop that operates over a wide frequency range from 100 kHz to 20 THz, meeting the specific requirements of terahertz applications. Compared to existing memristor designs, it operates at a much higher frequency. However, the zero crossing of the typical hysteresis loop deviates when the operating frequency exceeds 20 THz. Furthermore, the proposed memristor model can be customized in terms of set/reset voltage, operating frequency and R_off⁄R_on , and has been verified for use in high speed switches with switching speeds of 19.5 ps. Furthermore, this research fills the gap in ultra-high-frequency memristor modeling, offering valuable insights and guidance for the utilization of memristors in the 6G technology and ultra-high frequency fields.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139008660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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