In this study, we fabricated 76 × 127 µm2 green GaN-based micro-light-emitting-diodes (micro-LEDs) with atomic-layer-deposited (ALD) SiO2 passivation layers whose thicknesses were 0, 15, and 100 nm. The optoelectrical and communication performances of these devices were measured and analysed. The current-voltage results showed that ALD technology reduced the leakage current and enhanced the forward current of micro-LEDs. Compared with those of micro-LEDs without the passivation layer, the external quantum efficiency of micro-LEDs with 15 and 100 nm-thick SiO2 passivation layers increased by 23.64% and 19.47%, respectively. Furthermore, analysis of the EQE of the samples at room temperature using the ABC + f(n) model revealed the differences in the physical mechanisms of green micro-LEDs. Moreover, the communication performance indicated that ALD sidewall passivation reduced the carrier lifetime and improved the communication performance of green micro-LEDs.
在这项研究中，我们制作了 76 × 127 µm2 绿色氮化镓基微型发光二极管（micro-LED），其原子层沉积（ALD）二氧化硅钝化层的厚度分别为 0、15 和 100 nm。对这些器件的光电和通信性能进行了测量和分析。电流-电压结果表明，ALD 技术降低了微型 LED 的漏电流，提高了正向电流。与没有钝化层的微型 LED 相比，具有 15 nm 和 100 nm 厚 SiO2 钝化层的微型 LED 的外部量子效率分别提高了 23.64% 和 19.47%。此外，利用 ABC + f(n) 模型分析了样品在室温下的 EQE，揭示了绿色微型 LED 物理机制的差异。此外，通信性能表明，ALD 侧壁钝化降低了绿色微型 LED 的载流子寿命，提高了其通信性能。
{"title":"The impacts of SiO2 atomic-layer-deposited passivation layer thickness on GaN-based green micro-LEDs","authors":"Youcai Deng, Jinlan Chen, Saijun Li, He Huang, Zhong Liu, Zijun Yan, Shouqiang Lai, Lijie Zheng, Tianzhi Yang, Zhong Chen, Tingzhu Wu","doi":"10.1088/1361-6641/ad2b0a","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2b0a","url":null,"abstract":"In this study, we fabricated 76 × 127 <italic toggle=\"yes\">µ</italic>m<sup>2</sup> green GaN-based micro-light-emitting-diodes (micro-LEDs) with atomic-layer-deposited (ALD) SiO<sub>2</sub> passivation layers whose thicknesses were 0, 15, and 100 nm. The optoelectrical and communication performances of these devices were measured and analysed. The current-voltage results showed that ALD technology reduced the leakage current and enhanced the forward current of micro-LEDs. Compared with those of micro-LEDs without the passivation layer, the external quantum efficiency of micro-LEDs with 15 and 100 nm-thick SiO<sub>2</sub> passivation layers increased by 23.64% and 19.47%, respectively. Furthermore, analysis of the EQE of the samples at room temperature using the ABC + <italic toggle=\"yes\">f</italic>(n) model revealed the differences in the physical mechanisms of green micro-LEDs. Moreover, the communication performance indicated that ALD sidewall passivation reduced the carrier lifetime and improved the communication performance of green micro-LEDs.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"17 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140005779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-28DOI: 10.1088/1361-6641/ad2b09
I Blessing Meshach Dason, N Kasthuri, D Nirmal
Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP2S6 at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS2 with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS2 vdW NCFET has a high transconductance of 2.36 µS µm−1. A steep slope of 28.54 mV dec−1 is seen in MoS2 vdW NCFET which promises the performance of logic applications at a reduced supply voltage.
{"title":"TMD material investigation for a low hysteresis vdW NCFET logic transistor","authors":"I Blessing Meshach Dason, N Kasthuri, D Nirmal","doi":"10.1088/1361-6641/ad2b09","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2b09","url":null,"abstract":"Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP<sub>2</sub>S<sub>6</sub> at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS<sub>2</sub> with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS<sub>2</sub> vdW NCFET has a high transconductance of 2.36 <italic toggle=\"yes\">µ</italic>S <italic toggle=\"yes\">µ</italic>m<sup>−1</sup>. A steep slope of 28.54 mV dec<sup>−1</sup> is seen in MoS<sub>2</sub> vdW NCFET which promises the performance of logic applications at a reduced supply voltage.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"124 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140011074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work demonstrated a deep-ultraviolet (DUV) LED with an Al-graded p-AlGaN contact layer above the electron blocking layer to alleviate p-type contact resistance, the asymmetry of carriers transport, and the polarization effect. The fitting results from the ABC + f(n) model revealed that the LED has a higher radiative recombination coefficient than the conventional structures ever reported, which contributes to a lower carrier lifetime. The light output power of the LED at 350 mA is 44.71 mW, the peak external quantum efficiency (EQE) at 22.5 mA is 5.12%, the wall-plug efficiency at 9 mA is 4.40%. The 3 dB electrical-to-optical modulation bandwidth of the graded p-AlGaN contact layer LED is 390 MHz after impedance matching. In short, this study provides an in-depth analysis of the physical mechanism of the enhanced EQE and decreased carrier lifetime of DUV LEDs with Al-graded AlGaN as a p-type contact layer.
这项研究展示了一种深紫外（DUV）发光二极管，该发光二极管在电子阻挡层上方采用了铝级p-AlGaN接触层，以减轻p型接触电阻、载流子传输的不对称性和极化效应。ABC + f(n) 模型的拟合结果表明，该 LED 的辐射重组系数比以往报道的传统结构更高，从而导致载流子寿命更短。该 LED 在 350 mA 时的光输出功率为 44.71 mW，22.5 mA 时的峰值外部量子效率 (EQE) 为 5.12%，9 mA 时的壁插效率为 4.40%。阻抗匹配后，渐变 pAlGaN 接触层 LED 的 3 dB 电-光调制带宽为 390 MHz。总之，本研究深入分析了采用铝分级 AlGaN 作为 p 型接触层的 DUV LED 的 EQE 增强和载流子寿命降低的物理机制。
{"title":"Deep-ultraviolet LEDs with an Al-graded p-AlGaN layer exhibiting high wall-plug efficiency and high modulation bandwidth simultaneously","authors":"Bingyue Cui, Jie Yang, Xingfa Gao, Jiaheng He, Zhe Liu, Zhe Cheng, Yun Zhang","doi":"10.1088/1361-6641/ad238b","DOIUrl":"https://doi.org/10.1088/1361-6641/ad238b","url":null,"abstract":"This work demonstrated a deep-ultraviolet (DUV) LED with an Al-graded p-AlGaN contact layer above the electron blocking layer to alleviate p-type contact resistance, the asymmetry of carriers transport, and the polarization effect. The fitting results from the ABC + f(n) model revealed that the LED has a higher radiative recombination coefficient than the conventional structures ever reported, which contributes to a lower carrier lifetime. The light output power of the LED at 350 mA is 44.71 mW, the peak external quantum efficiency (EQE) at 22.5 mA is 5.12%, the wall-plug efficiency at 9 mA is 4.40%. The 3 dB electrical-to-optical modulation bandwidth of the graded p-AlGaN contact layer LED is 390 MHz after impedance matching. In short, this study provides an in-depth analysis of the physical mechanism of the enhanced EQE and decreased carrier lifetime of DUV LEDs with Al-graded AlGaN as a p-type contact layer.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"25 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140005448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-08DOI: 10.1088/1361-6641/ad2427
Zhengji Zhu, Chunshuang Chu, Kangkai Tian, Zhan Xuan, Zhiwei Xie, Ke Jiang, Yonghui Zhang, Xiaojuan Sun, Zi-Hui Zhang, Dabing Li
In this report, we propose a polarization-doped n-p-i-p-n GaN-based parallel phototransistor with thick GaN absorption layer. We employ an Al-composition-graded AlxGa1–xN layer for achieving p-type doping feature. We have studied the light propagation in the unintentionally doped GaN (i-GaN) absorption layer with different thicknesses, and the optimized thickness is 2 μm. As a result, the photo current of 10−2 A cm−2 and the responsivity of 2.12 A W−1 can be obtained at the applied bias of 5 V. In our fabricated device, during the current transport process, the photo-generated carriers are not along the device surface. Therefore, the photoconductive effect will be absent, and hence our device achieves a response speed with a rise time of 43.3 ms and a fall time of 86.4 ms.
{"title":"Polarization-doped n-p-i-p-n GaN-based parallel phototransistor with thick GaN absorption layer for achieving high responsivity","authors":"Zhengji Zhu, Chunshuang Chu, Kangkai Tian, Zhan Xuan, Zhiwei Xie, Ke Jiang, Yonghui Zhang, Xiaojuan Sun, Zi-Hui Zhang, Dabing Li","doi":"10.1088/1361-6641/ad2427","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2427","url":null,"abstract":"In this report, we propose a polarization-doped n-p-i-p-n GaN-based parallel phototransistor with thick GaN absorption layer. We employ an Al-composition-graded Al<sub>x</sub>Ga<sub>1–x</sub>N layer for achieving p-type doping feature. We have studied the light propagation in the unintentionally doped GaN (i-GaN) absorption layer with different thicknesses, and the optimized thickness is 2 <italic toggle=\"yes\">μ</italic>m. As a result, the photo current of 10<sup>−2</sup> A cm<sup>−2</sup> and the responsivity of 2.12 A W<sup>−1</sup> can be obtained at the applied bias of 5 V. In our fabricated device, during the current transport process, the photo-generated carriers are not along the device surface. Therefore, the photoconductive effect will be absent, and hence our device achieves a response speed with a rise time of 43.3 ms and a fall time of 86.4 ms.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"8 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139753607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 2T1C pixel driver circuit for mini-LED direct display has been proposed, which separates the switching transistor and the driver transistor from the same display substrate, replaces the driver transistor with n-metal oxide semiconductor (NMOS), and combines printed circuit board substrate and thin-film transistor (TFT) substrate to improve the driving capability of the circuit. The NMOS was soldered with mini-LEDs simultaneously onto a substrate which connects to the a-Si TFT array. Two driving modes for a 32-level gray-scale display panel were investigated to compare the voltage-current and optical characteristics. The results demonstrated that the drain-driving mode is better suited for high brightness and high-power display application scenarios as it supports higher-driven currents, but the source-driving mode is more appropriate for precision gray-scale applications due to the higher current linearity of the mode.
提出了用于微型 LED 直接显示的 2T1C 像素驱动电路，该电路将开关晶体管和驱动晶体管从同一个显示基板上分离出来，用正金属氧化物半导体（NMOS）取代驱动晶体管，并将印刷电路板基板和薄膜晶体管（TFT）基板结合起来，以提高电路的驱动能力。NMOS 与微型 LED 同时焊接在连接到非晶硅 TFT 阵列的基板上。研究了 32 级灰度显示面板的两种驱动模式，以比较电压-电流和光学特性。结果表明，漏极驱动模式更适合高亮度和高功率显示应用场景，因为它支持更高的驱动电流，但源极驱动模式更适合精密灰度应用，因为该模式的电流线性度更高。
{"title":"Integrated 2T1C pixel circuit with a-Si TFT and NMOS for active matrix mini-LED displays","authors":"Chenming Zhong, Guangyao Li, Xi Zheng, Lihong Zhu, Jianbang Zhuang, Yijun Lu, Zhong Chen, Weijie Guo","doi":"10.1088/1361-6641/ad238c","DOIUrl":"https://doi.org/10.1088/1361-6641/ad238c","url":null,"abstract":"The 2T1C pixel driver circuit for mini-LED direct display has been proposed, which separates the switching transistor and the driver transistor from the same display substrate, replaces the driver transistor with n-metal oxide semiconductor (NMOS), and combines printed circuit board substrate and thin-film transistor (TFT) substrate to improve the driving capability of the circuit. The NMOS was soldered with mini-LEDs simultaneously onto a substrate which connects to the a-Si TFT array. Two driving modes for a 32-level gray-scale display panel were investigated to compare the voltage-current and optical characteristics. The results demonstrated that the drain-driving mode is better suited for high brightness and high-power display application scenarios as it supports higher-driven currents, but the source-driving mode is more appropriate for precision gray-scale applications due to the higher current linearity of the mode.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"22 4 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139753555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-18DOI: 10.1088/1361-6641/ad1ccb
Zhenghua Wang, Lei Yuan, Bo Peng, Xinming Xie, Yuming Zhang, Renxu Jia
In this work, a β-Ga2O3 super barrier rectifier with a current blocking layer (CSBR) is proposed. Its static characteristics, dynamic characteristics and surge capability are investigated by TCAD simulation. The Baliga’s figure of merit (BFOM) can reach 1.62 GW cm−2 with the on-resistance of 3.68 mΩ cm−2 and the breakdown voltage of 2447 V, exhibiting excellent performance. Foremost, the turn-on and turn-off of the device is controlled by metal-oxide-semiconductor (MOS) structure. The reverse recovery time is 11.2 ns, which is compatible with that of a Schottky diode. Simulation results show that the dimensions of the cells and the proportion of the ohmic contact region in the cells are the key parameters affecting the reverse recovery time. In addition, the CSBR with double-side cooling configuration demonstrates high surge capability. It can sustain a peak surge current density of 5000 A cm−2, which is more than 10 times its forward current (VForward = 3.0 V). Overall, the proposed structure has a high BFOM, excellent reverse characteristics and high reliability, demonstrating its potential in high voltage applications. Moreover, CSBR can be embedded into Ga2O3-MOSFET as a free-wheeling diode.
{"title":"Design and simulation of high performance β-Ga2O3 super barrier rectifier with a current blocking layer","authors":"Zhenghua Wang, Lei Yuan, Bo Peng, Xinming Xie, Yuming Zhang, Renxu Jia","doi":"10.1088/1361-6641/ad1ccb","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1ccb","url":null,"abstract":"In this work, a <italic toggle=\"yes\">β</italic>-Ga<sub>2</sub>O<sub>3</sub> super barrier rectifier with a current blocking layer (CSBR) is proposed. Its static characteristics, dynamic characteristics and surge capability are investigated by TCAD simulation. The Baliga’s figure of merit (BFOM) can reach 1.62 GW cm<sup>−2</sup> with the on-resistance of 3.68 mΩ cm<sup>−2</sup> and the breakdown voltage of 2447 V, exhibiting excellent performance. Foremost, the turn-on and turn-off of the device is controlled by metal-oxide-semiconductor (MOS) structure. The reverse recovery time is 11.2 ns, which is compatible with that of a Schottky diode. Simulation results show that the dimensions of the cells and the proportion of the ohmic contact region in the cells are the key parameters affecting the reverse recovery time. In addition, the CSBR with double-side cooling configuration demonstrates high surge capability. It can sustain a peak surge current density of 5000 A cm<sup>−2</sup>, which is more than 10 times its forward current (<italic toggle=\"yes\">V</italic>\u0000<sub>Forward</sub> = 3.0 V). Overall, the proposed structure has a high BFOM, excellent reverse characteristics and high reliability, demonstrating its potential in high voltage applications. Moreover, CSBR can be embedded into Ga<sub>2</sub>O<sub>3</sub>-MOSFET as a free-wheeling diode.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"26 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139510086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-09DOI: 10.1088/1361-6641/ad1cca
Ashish Khandelwal, L. S. Sharath Chandra, Shilpam Sharma, A. Sagdeo, Ram Janay Choudhary, M. K. Chattopadhyay
Fe3O4 is considered to be a promising material for terahertz spintronic applications as well as for stealth technology. However, the optical properties of Fe3O4 in the thin film form at terahertz frequencies are not reported in literature. In this article, we present the frequency and temperature dependence of dielectric permittivity (ε1) and optical conductivity (σ1) of Fe3O4 films deposited on Si substrate. The σ1 of these films show absorption peaks related to charge localization and shallow impurities. It is also observed that the Fe2O3/Fe3O4 composite films have large σ1 and ε1 indicating their potential use for stealth technology applications. The overall optical properties are found to depend strongly on the microstructure and defects, such as, the grain size and the presence of grain boundaries, anti-phase boundaries, strain disorder due to lattice mismatch and/or the Fe+2/Fe+3 ratio.
{"title":"Terahertz dielectric properties of Fe3O4 thin films deposited on Si (100) substrate","authors":"Ashish Khandelwal, L. S. Sharath Chandra, Shilpam Sharma, A. Sagdeo, Ram Janay Choudhary, M. K. Chattopadhyay","doi":"10.1088/1361-6641/ad1cca","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1cca","url":null,"abstract":"\u0000 Fe3O4 is considered to be a promising material for terahertz spintronic applications as well as for stealth technology. However, the optical properties of Fe3O4 in the thin film form at terahertz frequencies are not reported in literature. In this article, we present the frequency and temperature dependence of dielectric permittivity (ε1) and optical conductivity (σ1) of Fe3O4 films deposited on Si substrate. The σ1 of these films show absorption peaks related to charge localization and shallow impurities. It is also observed that the Fe2O3/Fe3O4 composite films have large σ1 and ε1 indicating their potential use for stealth technology applications. The overall optical properties are found to depend strongly on the microstructure and defects, such as, the grain size and the presence of grain boundaries, anti-phase boundaries, strain disorder due to lattice mismatch and/or the Fe+2/Fe+3 ratio.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"15 4","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139443203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-09DOI: 10.1088/1361-6641/ad1c62
Li Huang, Xiaojin Li, Yabin Sun, Yanling Shi
In this study, a novel split gate trench MOSFET with a high-k pillar (HKP SGT-MOS) embedded is proposed. Lots of electric displacement lines are allowed to enter into high-k pillar introduced beneath split gate, thus relieving the crowding of electric field at bottom corner. Therefore, the HKP SGT-MOS can achieve a higher breakdown voltage(BV) without sacrificing its forward conduction. Various dielectrics for the high-k pillar, including SiO2, Si3N4, Al2O3 and HfO2, are investigated and the results reveal that HfO2 has the largest FOM and BV. The characteristics of HKP SGT-MOS have also been validated by TCAD simulation, and it is shown that the BV and figure of merit (FOM=BV2/Ron,sp) are 258.3V and 37.46 MW/cm2, achieving 36.7% and 87.02% improvement compared to the conventional SGT-MOS, 18.4% and 38.59% improvement compared to the SGT-MOS with short split-gate. Moreover, the influences of drift doping concentration, mesa width, length and width of split gate/high-k pillar are also studied to optimize the HKP SGT-MOS.
{"title":"A novel split gate trench MOSFET with high-k pillar embedded for higher breakdown voltage","authors":"Li Huang, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1088/1361-6641/ad1c62","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1c62","url":null,"abstract":"\u0000 In this study, a novel split gate trench MOSFET with a high-k pillar (HKP SGT-MOS) embedded is proposed. Lots of electric displacement lines are allowed to enter into high-k pillar introduced beneath split gate, thus relieving the crowding of electric field at bottom corner. Therefore, the HKP SGT-MOS can achieve a higher breakdown voltage(BV) without sacrificing its forward conduction. Various dielectrics for the high-k pillar, including SiO2, Si3N4, Al2O3 and HfO2, are investigated and the results reveal that HfO2 has the largest FOM and BV. The characteristics of HKP SGT-MOS have also been validated by TCAD simulation, and it is shown that the BV and figure of merit (FOM=BV2/Ron,sp) are 258.3V and 37.46 MW/cm2, achieving 36.7% and 87.02% improvement compared to the conventional SGT-MOS, 18.4% and 38.59% improvement compared to the SGT-MOS with short split-gate. Moreover, the influences of drift doping concentration, mesa width, length and width of split gate/high-k pillar are also studied to optimize the HKP SGT-MOS.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"61 4","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139445211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-08DOI: 10.1088/1361-6641/ad1c4d
A. Çiriş, Y. Atasoy, M. Tomakin, Abdullah Karaca, T. Küçükömeroğlu, E. Bacaksız
In this study, the effect of depositing CdSeTe and CdTe layers at different substrate temperatures by evaporation in vacuum on the properties of the CdSeTe/CdTe stacks was investigated. First, CdSeTe layers in stack structure were grown at substrate temperatures of 150, 200 and 250°C and then CdTe layers on the CdSeTe produced with the optimum temperature were coated at substrate temperatures of 150, 200 and 250°C. The employing of substrate temperatures up to 150°C on both CdSeTe and CdTe films in CdSeTe/CdTe stacks demonstrated the presence of Te and/or oxide phases as well as the alloying, while more stable phase structures at higher temperatures. In the CdSeTe/CdTe stack, the increase in substrate temperature of CdSeTe promoted the alloying, while it weakened the alloy in which was applied in CdTe. It was concluded that under the applied experimental conditions, substrate temperatures of 250°C and 200°C with the graded alloying structure, suitable absorption sites, more homogeneous surface morphology for potential solar cell applications would be more suitable for CdSeTe and CdTe, respectively. As a result, the application of substrate temperature to CdSeTe or CdTe in the stacks can be used as a tool to control the properties of the stack structure.
{"title":"Impact of CdSeTe and CdSe film deposition parameter on the properties of CdSeTe/CdTe absorber structure for solar cell applications","authors":"A. Çiriş, Y. Atasoy, M. Tomakin, Abdullah Karaca, T. Küçükömeroğlu, E. Bacaksız","doi":"10.1088/1361-6641/ad1c4d","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1c4d","url":null,"abstract":"\u0000 In this study, the effect of depositing CdSeTe and CdTe layers at different substrate temperatures by evaporation in vacuum on the properties of the CdSeTe/CdTe stacks was investigated. First, CdSeTe layers in stack structure were grown at substrate temperatures of 150, 200 and 250°C and then CdTe layers on the CdSeTe produced with the optimum temperature were coated at substrate temperatures of 150, 200 and 250°C. The employing of substrate temperatures up to 150°C on both CdSeTe and CdTe films in CdSeTe/CdTe stacks demonstrated the presence of Te and/or oxide phases as well as the alloying, while more stable phase structures at higher temperatures. In the CdSeTe/CdTe stack, the increase in substrate temperature of CdSeTe promoted the alloying, while it weakened the alloy in which was applied in CdTe. It was concluded that under the applied experimental conditions, substrate temperatures of 250°C and 200°C with the graded alloying structure, suitable absorption sites, more homogeneous surface morphology for potential solar cell applications would be more suitable for CdSeTe and CdTe, respectively. As a result, the application of substrate temperature to CdSeTe or CdTe in the stacks can be used as a tool to control the properties of the stack structure.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"50 14","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139447189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-05DOI: 10.1088/1361-6641/ad1ba8
Hai-Ze Cao, Y. G. Xiao, Ning-Jie Ma, Li-Sha Yang, Yong Jiang, K. Xiong, Gang Li, Jun OuYang, Minghua Tang
The negative capacitance (NC) of ferroelectric materials can effectively break the “Boltzmann tyranny” and drive the continuation scaling of Moore’s law. In this work, to find a novel way of amplifying the transient NC, a series network of external resistors and PbZr(1-x)Ti(x)O3 (PZT) ferroelectric capacitors were constructed. Uniform modeling and simulation were performed using Kirchhoff’s current law, electrostatics equations, and Landau-Khalatnikov equations. The derived results revealed that the mismatch of switching rate between free charge and polarization during ferroelectric domain switching is responsible for the transient NC generation. Some interesting results were obtained for the regulation of the transient NC by various factors such as the strain between the ferroelectric film and substrate, the viscosity coefficient, the ratio of Ti components, the external resistance magnitude, and the operating temperature. This work provides considerable insight into the control of ferroelectric transient NC, and offers guidance for obtaining larger and longer transient NC in the widely used PZT thin films.
{"title":"Multiple factors of regulation for transient negative capacitance in PbZr(1-x)Ti(x)O3 ferroelectric thin films","authors":"Hai-Ze Cao, Y. G. Xiao, Ning-Jie Ma, Li-Sha Yang, Yong Jiang, K. Xiong, Gang Li, Jun OuYang, Minghua Tang","doi":"10.1088/1361-6641/ad1ba8","DOIUrl":"https://doi.org/10.1088/1361-6641/ad1ba8","url":null,"abstract":"\u0000 The negative capacitance (NC) of ferroelectric materials can effectively break the “Boltzmann tyranny” and drive the continuation scaling of Moore’s law. In this work, to find a novel way of amplifying the transient NC, a series network of external resistors and PbZr(1-x)Ti(x)O3 (PZT) ferroelectric capacitors were constructed. Uniform modeling and simulation were performed using Kirchhoff’s current law, electrostatics equations, and Landau-Khalatnikov equations. The derived results revealed that the mismatch of switching rate between free charge and polarization during ferroelectric domain switching is responsible for the transient NC generation. Some interesting results were obtained for the regulation of the transient NC by various factors such as the strain between the ferroelectric film and substrate, the viscosity coefficient, the ratio of Ti components, the external resistance magnitude, and the operating temperature. This work provides considerable insight into the control of ferroelectric transient NC, and offers guidance for obtaining larger and longer transient NC in the widely used PZT thin films.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"19 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2024-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139383708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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