Pub Date : 2024-05-03DOI: 10.1088/1361-6641/ad4739
Tae Young Yoon, Dongho Shin, Hyunwoo Kim, J. Kim
The Insulated Gate Bipolar Transistor (IGBT) is crucial in high-voltage applications due to its characteristics like breakdown voltage (BV) and on-state voltage VCE(sat). However, its slower turn-off time, attributed to hole mobility, restricts its frequency range. Techniques such as the carrier storage layer (CSL) and super-junction (SJ) structures aim to optimize BV and VCE(sat) through hole density and field distribution. Combining CSL and SJ offers advantages, yet challenges remain regarding E-field concentration. In this work, the split CSL concept introduces a solution by optimizing BV and Eoff through effective field distribution and hole extraction acceleration respectively while maintaining VCE(sat). Split CSL, which is divided into a high doping layer and a low doping layer, reduces the burden on the gate oxide by distributing the E-field evenly when in the off-state due to the difference in doping concentration. And during turn-off, hole current is concentrated on LDL, which has relatively low resistance, thereby accelerating hole extraction. Simulation-based results showcase improvements in the proposed structure's properties. The further optimization of high doping layer (HDL) and low doping layer (LDL) concentrations enhances the structure's performance. It is clear that the split CSL structure presents potential for advancing IGBT capabilities. The application of the split CSL structure resulted in significant improvements: the turn-off time was reduced by 32.4% and the breakdown voltage increased by 32.5 V compared to conventional CSL-SJ structures. These enhancements highlight the effectiveness of the split CSL design in optimizing the IGBT’s performance attribute.
{"title":"Superjunction IGBT with split carrier storage layer","authors":"Tae Young Yoon, Dongho Shin, Hyunwoo Kim, J. Kim","doi":"10.1088/1361-6641/ad4739","DOIUrl":"https://doi.org/10.1088/1361-6641/ad4739","url":null,"abstract":"\u0000 The Insulated Gate Bipolar Transistor (IGBT) is crucial in high-voltage applications due to its characteristics like breakdown voltage (BV) and on-state voltage VCE(sat). However, its slower turn-off time, attributed to hole mobility, restricts its frequency range. Techniques such as the carrier storage layer (CSL) and super-junction (SJ) structures aim to optimize BV and VCE(sat) through hole density and field distribution. Combining CSL and SJ offers advantages, yet challenges remain regarding E-field concentration. In this work, the split CSL concept introduces a solution by optimizing BV and Eoff through effective field distribution and hole extraction acceleration respectively while maintaining VCE(sat). Split CSL, which is divided into a high doping layer and a low doping layer, reduces the burden on the gate oxide by distributing the E-field evenly when in the off-state due to the difference in doping concentration. And during turn-off, hole current is concentrated on LDL, which has relatively low resistance, thereby accelerating hole extraction. Simulation-based results showcase improvements in the proposed structure's properties. The further optimization of high doping layer (HDL) and low doping layer (LDL) concentrations enhances the structure's performance. It is clear that the split CSL structure presents potential for advancing IGBT capabilities. The application of the split CSL structure resulted in significant improvements: the turn-off time was reduced by 32.4% and the breakdown voltage increased by 32.5 V compared to conventional CSL-SJ structures. These enhancements highlight the effectiveness of the split CSL design in optimizing the IGBT’s performance attribute.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141016917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-01DOI: 10.1088/1361-6641/ad462a
Zengfa Chen, Wen Yue, Renqiang Zhu, Ming Wang, Xi Zhu, Jinpei Lin, Shuangwu Huang, Xinke Liu
In this work, a normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) was demonstrated. The device shows a current on/off ratio of 3.6×10^10, a threshold voltage (VTH) of 1.64 V and a specific on-resistance (RON,SP) of 1.87 mΩ·cm^2. Drain induced channel effects were proposed to explain the change of gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by the effects. Technology computer aided design (TCAD) was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of new structures. The characteristics at different temperatures were demonstrated to show the stability of threshold voltage and specific on-resistance, which indicates the great potential of application in switching power circuit of vertical GaN JFETs.
{"title":"Study of drain induced channel effects in vertical GaN junction field-effect transistors","authors":"Zengfa Chen, Wen Yue, Renqiang Zhu, Ming Wang, Xi Zhu, Jinpei Lin, Shuangwu Huang, Xinke Liu","doi":"10.1088/1361-6641/ad462a","DOIUrl":"https://doi.org/10.1088/1361-6641/ad462a","url":null,"abstract":"\u0000 In this work, a normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) was demonstrated. The device shows a current on/off ratio of 3.6×10^10, a threshold voltage (VTH) of 1.64 V and a specific on-resistance (RON,SP) of 1.87 mΩ·cm^2. Drain induced channel effects were proposed to explain the change of gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by the effects. Technology computer aided design (TCAD) was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of new structures. The characteristics at different temperatures were demonstrated to show the stability of threshold voltage and specific on-resistance, which indicates the great potential of application in switching power circuit of vertical GaN JFETs.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141036734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-24DOI: 10.1088/1361-6641/ad3d7c
Nguyen Hong Quang, Nguyen Thi Kim Thanh and Nguyen Que Huong
We theoretically study biexcitons and quadrons in quantum dots with parabolic confinement and give a complete comparison between the two excitations. The calculation of quadron and biexciton binding energies as functions of electron-to-hole confinement potentials and mass ratios, using the unrestricted Hartree–Fock method, shows the essential differences between biexcitons and quadrons. The crossover between the negative and positive binding energies is indicated. The effect of an external magnetic field on the quadron and biexciton binding energies has also been investigated. In addition, the crossover between anti-binding and binding of both excited quadron and biexciton states in a certain range of the electron-to-hole oscillator length ratios has been found.
{"title":"Biexcitons and quadrons in self-assembled quantum dots","authors":"Nguyen Hong Quang, Nguyen Thi Kim Thanh and Nguyen Que Huong","doi":"10.1088/1361-6641/ad3d7c","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3d7c","url":null,"abstract":"We theoretically study biexcitons and quadrons in quantum dots with parabolic confinement and give a complete comparison between the two excitations. The calculation of quadron and biexciton binding energies as functions of electron-to-hole confinement potentials and mass ratios, using the unrestricted Hartree–Fock method, shows the essential differences between biexcitons and quadrons. The crossover between the negative and positive binding energies is indicated. The effect of an external magnetic field on the quadron and biexciton binding energies has also been investigated. In addition, the crossover between anti-binding and binding of both excited quadron and biexciton states in a certain range of the electron-to-hole oscillator length ratios has been found.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140805387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-15DOI: 10.1088/1361-6641/ad3a93
Yujie Gao, Xun Hu, Lingli Zhu, Na Gao, Rui Zhou, Yaping Wu, Kai Huang, Shuping Li, Junyong Kang, Rong Zhang
High-efficiency deep-ultraviolet (DUV) micro light-emitting diodes (LEDs) are explored for inspiring development in numerous fields, such as non-line-of-sight solar-blind communication, optical pumping, and maskless lithography. In this study, we performed FDTD and SimuLED calculations to investigate the optimized DUV micro-LED structure geometry for high light extraction efficiency (LEE) by designing different mesa structures, including square, hexagonal, and circular geometries of micro-LEDs emitted at a wavelength of 275 nm. The results showed that a circular mesa of 5 μm diameter achieved a LEE of 27% from the bottom and sidewall emissions of as-prepared DUV micro-LED. And both the near- and far-field transverse magnetic polarized light intensities were enhanced by a factor of 1.5 over the square and hexagonal mesas. Meanwhile, the transverse electric (TE) polarized light of the circular mesa structure was enhanced and concentrated along the normal direction. Moreover, the internal quantum efficiency (IQE) of circular mesas with varied sizes was comprehensively investigated in the interactions of the thermal and electric fields. An AlGaN-based DUV micro-LED with a diameter of 5 μm was found to obtain the highest IQE owing to a high current-density distribution and its self-heating properties, thereby achieving a sufficiently high external quantum efficiency of 26.75%. This study provides a comprehensive technical report, including electrical, thermal, and optical analyses, and a new perspective for developing high-efficiency, high-performance DUV micro-LEDs in practical applications.
高效深紫外（DUV）微型发光二极管（LED）在许多领域都得到了令人鼓舞的发展，例如非视线太阳盲通信、光泵浦和无掩模光刻。在这项研究中，我们进行了 FDTD 和 SimuLED 计算，通过设计不同的网格结构（包括在 275 nm 波长处发射的微型 LED 的正方形、六边形和圆形几何结构）来研究优化的 DUV 微型 LED 结构几何形状，以实现高光萃取效率（LEE）。结果表明，直径为 5 μm 的圆形网格从制备好的 DUV 微型 LED 的底部和侧壁发射的萃取效率达到了 27%。近场和远场横向磁偏振光强度都比正方形和六边形网格增强了 1.5 倍。同时，圆形网格结构的横向电（TE）偏振光沿法线方向增强并集中。此外，在热场和电场的相互作用下，还全面研究了不同尺寸圆网格的内部量子效率（IQE）。研究发现，直径为 5 μm 的 AlGaN 基 DUV 微型 LED 因其高电流密度分布和自加热特性而获得了最高的 IQE，从而实现了 26.75% 的足够高的外部量子效率。这项研究提供了一份全面的技术报告，包括电学、热学和光学分析，为在实际应用中开发高效率、高性能的紫外微型 LED 提供了新的视角。
{"title":"Enhancing external quantum efficiency of deep ultraviolet micro-leds through geometry design and multi-physics field coupling analysis","authors":"Yujie Gao, Xun Hu, Lingli Zhu, Na Gao, Rui Zhou, Yaping Wu, Kai Huang, Shuping Li, Junyong Kang, Rong Zhang","doi":"10.1088/1361-6641/ad3a93","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3a93","url":null,"abstract":"High-efficiency deep-ultraviolet (DUV) micro light-emitting diodes (LEDs) are explored for inspiring development in numerous fields, such as non-line-of-sight solar-blind communication, optical pumping, and maskless lithography. In this study, we performed FDTD and SimuLED calculations to investigate the optimized DUV micro-LED structure geometry for high light extraction efficiency (LEE) by designing different mesa structures, including square, hexagonal, and circular geometries of micro-LEDs emitted at a wavelength of 275 nm. The results showed that a circular mesa of 5 <italic toggle=\"yes\">μ</italic>m diameter achieved a LEE of 27% from the bottom and sidewall emissions of as-prepared DUV micro-LED. And both the near- and far-field transverse magnetic polarized light intensities were enhanced by a factor of 1.5 over the square and hexagonal mesas. Meanwhile, the transverse electric (TE) polarized light of the circular mesa structure was enhanced and concentrated along the normal direction. Moreover, the internal quantum efficiency (IQE) of circular mesas with varied sizes was comprehensively investigated in the interactions of the thermal and electric fields. An AlGaN-based DUV micro-LED with a diameter of 5 <italic toggle=\"yes\">μ</italic>m was found to obtain the highest IQE owing to a high current-density distribution and its self-heating properties, thereby achieving a sufficiently high external quantum efficiency of 26.75%. This study provides a comprehensive technical report, including electrical, thermal, and optical analyses, and a new perspective for developing high-efficiency, high-performance DUV micro-LEDs in practical applications.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140608869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-11DOI: 10.1088/1361-6641/ad3a92
Zhenxing Lv, Zhefu Liao, Shengjun Zhou
Increasing the reflection of p-side is an effective way to improve the optoelectronic performance of flip-chip light-emitting diodes (FCLEDs). Here, we propose a full-coverage Al reflector (FAR) and a highly reflective Ni/Rh p-electrode to enhance the performance of deep ultraviolet (DUV) FCLEDs. The physical mechanism for the impact of the FAR and Ni/Rh electrode on the light extraction efficiency (LEE) is discussed theoretically. Simulations demonstrate that the combination of the FAR and Ni/Rh electrode improves the LEEs of transverse electric- and transverse magnetic-polarized light by 13.62% and 27.08%, respectively. At an injection current of 100 mA, the fabricated DUV FCLEDs with FAR and Ni/Rh electrode exhibits an external quantum efficiency of 4.01% and a wall plugging efficiency of 2.92%, which are 16.85% and 13.18% higher than those of conventional DUV FCLEDs, respectively. These results support the promise of the FAR and Ni/Rh electrode for high-power DUV LED applications.
提高 p 面的反射率是改善倒装芯片发光二极管（FCLED）光电性能的有效方法。在此，我们提出了一种全覆盖铝反射器（FAR）和一种高反射镍/铑对电极，以提高深紫外（DUV）FCLED 的性能。理论上讨论了 FAR 和 Ni/Rh 电极对光萃取效率（LEE）影响的物理机制。模拟结果表明，结合使用 FAR 和 Ni/Rh 电极，横向电偏振光和横向磁偏振光的萃取效率分别提高了 13.62% 和 27.08%。在注入电流为 100 mA 时，使用 FAR 和 Ni/Rh 电极制造的 DUV FCLED 的外部量子效率为 4.01%，堵壁效率为 2.92%，分别比传统 DUV FCLED 高出 16.85% 和 13.18%。这些结果支持了 FAR 和 Ni/Rh 电极在高功率 DUV LED 应用中的前景。
{"title":"Enhanced efficiency of deep ultraviolet light-emitting diodes utilizing full-coverage Al reflector and highly reflective Ni/Rh p-electrode","authors":"Zhenxing Lv, Zhefu Liao, Shengjun Zhou","doi":"10.1088/1361-6641/ad3a92","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3a92","url":null,"abstract":"Increasing the reflection of p-side is an effective way to improve the optoelectronic performance of flip-chip light-emitting diodes (FCLEDs). Here, we propose a full-coverage Al reflector (FAR) and a highly reflective Ni/Rh p-electrode to enhance the performance of deep ultraviolet (DUV) FCLEDs. The physical mechanism for the impact of the FAR and Ni/Rh electrode on the light extraction efficiency (LEE) is discussed theoretically. Simulations demonstrate that the combination of the FAR and Ni/Rh electrode improves the LEEs of transverse electric- and transverse magnetic-polarized light by 13.62% and 27.08%, respectively. At an injection current of 100 mA, the fabricated DUV FCLEDs with FAR and Ni/Rh electrode exhibits an external quantum efficiency of 4.01% and a wall plugging efficiency of 2.92%, which are 16.85% and 13.18% higher than those of conventional DUV FCLEDs, respectively. These results support the promise of the FAR and Ni/Rh electrode for high-power DUV LED applications.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140608629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1088/1361-6641/ad3844
Lakshumanan Chandrasekar, R. Shaik, V. Rajakumari, K. P. Pradhan
This paper is primarily focused on developing an analytical model to mimic the synaptic behavior with non-zero bandgap of boron (B)/nitrogen (N) substitution doped graphene field effect transistors (GFET). The trap charges at the channel and gate-insulator interface are utilized to induce the hysteresis conduction mechanism, which further is exploited to accomplish the synaptic plasticity. The proposed recurrence i.e., time dependent trap states drain current model is well capturing the physical insights of trap charges through an equivalent MIG (metal-insulator-graphene) model. The interesting fact of the proposed model is that it is compatible with both the doped (B/N) as well as with the undoped GFET. The model is also explored to generate the hysteresis characteristics of the GFET that is further utilized for mimicking the synaptic behavior. Another fact needs to be noticed is the existence of complete off regions for doped B/N GFET unlike the undoped case that manifests the undesirable ambipolar behaviour. As a result, the synapse made up of B/N doped GFET is predicting an optimistic learning and memory mechanism, termed as spike time dependent plasticity (STDP). The STDP characteristics of B/N doped synaptic GFET has been enhanced by more than 18$times$ when compared against the artificial synapse made by undoped GFET. Hence, the hysteresis behaviour along with non-zero bandgap of B/N substitution doped GFETs make it highly favourable in dynamic mimicking of synaptic plasticity with efficient biologically plausible.
{"title":"A recurrence model capturing interface traps for non-zero bandgap GFETs towards dynamic mimicking of synaptic plasticity","authors":"Lakshumanan Chandrasekar, R. Shaik, V. Rajakumari, K. P. Pradhan","doi":"10.1088/1361-6641/ad3844","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3844","url":null,"abstract":"\u0000 This paper is primarily focused on developing an analytical model to mimic the synaptic behavior with non-zero bandgap of boron (B)/nitrogen (N) substitution doped graphene field effect transistors (GFET). The trap charges at the channel and gate-insulator interface are utilized to induce the hysteresis conduction mechanism, which further is exploited to accomplish the synaptic plasticity. The proposed recurrence i.e., time dependent trap states drain current model is well capturing the physical insights of trap charges through an equivalent MIG (metal-insulator-graphene) model. The interesting fact of the proposed model is that it is compatible with both the doped (B/N) as well as with the undoped GFET. The model is also explored to generate the hysteresis characteristics of the GFET that is further utilized for mimicking the synaptic behavior. Another fact needs to be noticed is the existence of complete off regions for doped B/N GFET unlike the undoped case that manifests the undesirable ambipolar behaviour. As a result, the synapse made up of B/N doped GFET is predicting an optimistic learning and memory mechanism, termed as spike time dependent plasticity (STDP). The STDP characteristics of B/N doped synaptic GFET has been enhanced by more than 18$times$ when compared against the artificial synapse made by undoped GFET. Hence, the hysteresis behaviour along with non-zero bandgap of B/N substitution doped GFETs make it highly favourable in dynamic mimicking of synaptic plasticity with efficient biologically plausible.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140374849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1088/1361-6641/ad3845
Tongyang Wang, Zehong Li, Lu Li, Yang Yang, Yishang Zhao, Ziming Xia, Yige Zheng, Jun Ye, Xuan Xiao
A novel MOSFET with lateral-vertical charge coupling (LVCC-MOSFET) is proposed in this paper. Lateral charge coupling is enabled by metal field plate, lightly doped drain (LDD) and P-Epi layer to reduce Cgd. Vertical charge coupling is enabled by shield gate, sinker and P-Epi layer to support high breakdown voltage (BV) and further reduce Cgd. By combining both lateral charge coupling and vertical charge coupling, which is first proposed in low-voltage power MOSFETs, tradeoff relationship between BV, Ron and Cgd can be significantly improved. It is verified by both small-signal analysis and transient capacitance simulation that gate-to-drain capacitance of the proposed LVCC-MOSFET can be reduced by more than 99% without deterioration of BV and Ron. LVCC-MOSFET achieves 93.7% reduction in Qgd and Ron×Qgd is only 0.81 mΩꞏnC, which is reduced by 93.9%. Furthermore, Eon and Eoff can be reduced by 73.6% and 53.8%, respectively. Hot carrier injection (HCI) reliability can be enhanced by reducing electric field and impact ionization generation rate near drain-side gate oxide. Besides, the LVCC-MOSFET can be feasibly manufactured with compatible fabrication process flow and only three extra steps are needed.
{"title":"A novel MOSFET with lateral-vertical charge coupling for extremely low C\u0000 gd","authors":"Tongyang Wang, Zehong Li, Lu Li, Yang Yang, Yishang Zhao, Ziming Xia, Yige Zheng, Jun Ye, Xuan Xiao","doi":"10.1088/1361-6641/ad3845","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3845","url":null,"abstract":"\u0000 A novel MOSFET with lateral-vertical charge coupling (LVCC-MOSFET) is proposed in this paper. Lateral charge coupling is enabled by metal field plate, lightly doped drain (LDD) and P-Epi layer to reduce Cgd. Vertical charge coupling is enabled by shield gate, sinker and P-Epi layer to support high breakdown voltage (BV) and further reduce Cgd. By combining both lateral charge coupling and vertical charge coupling, which is first proposed in low-voltage power MOSFETs, tradeoff relationship between BV, Ron and Cgd can be significantly improved. It is verified by both small-signal analysis and transient capacitance simulation that gate-to-drain capacitance of the proposed LVCC-MOSFET can be reduced by more than 99% without deterioration of BV and Ron. LVCC-MOSFET achieves 93.7% reduction in Qgd and Ron×Qgd is only 0.81 mΩꞏnC, which is reduced by 93.9%. Furthermore, Eon and Eoff can be reduced by 73.6% and 53.8%, respectively. Hot carrier injection (HCI) reliability can be enhanced by reducing electric field and impact ionization generation rate near drain-side gate oxide. Besides, the LVCC-MOSFET can be feasibly manufactured with compatible fabrication process flow and only three extra steps are needed.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140374319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (Vth) and breakdown voltage (BV) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a Vth of 3.4 V, a low on-state resistance (Ron) of 0.64 mΩ cm2, and a BV of 1245 V, while the PVG-HEMT device exhibits a Vth of 3.7 V, an Ron of 0.65 mΩ cm2, and a BV of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm−2, respectively, much higher than that for the VG-HEMT control group (1.0 GW cm−2). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.
{"title":"Performance improvement of enhancement-mode GaN-based HEMT power devices by employing a vertical gate structure and composite interlayers*","authors":"Zhonghao Sun, Jianxun Dai, Huolin Huang, Nan Sun, Jiayu Zhang, Yun Lei, Dawei Li, Kaiming Ma, Huimin Yu, Yanhong Liu, Hui Huang, Yung C Liang","doi":"10.1088/1361-6641/ad31c5","DOIUrl":"https://doi.org/10.1088/1361-6641/ad31c5","url":null,"abstract":"In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (<italic toggle=\"yes\">V</italic>\u0000<sub>th</sub>) and breakdown voltage (<italic toggle=\"yes\">BV</italic>) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a <italic toggle=\"yes\">V</italic>\u0000<sub>th</sub> of 3.4 V, a low on-state resistance (<italic toggle=\"yes\">R</italic>\u0000<sub>on</sub>) of 0.64 mΩ cm<sup>2</sup>, and a <italic toggle=\"yes\">BV</italic> of 1245 V, while the PVG-HEMT device exhibits a <italic toggle=\"yes\">V</italic>\u0000<sub>th</sub> of 3.7 V, an <italic toggle=\"yes\">R</italic>\u0000<sub>on</sub> of 0.65 mΩ cm<sup>2</sup>, and a <italic toggle=\"yes\">BV</italic> of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm<sup>−2</sup>, respectively, much higher than that for the VG-HEMT control group (1.0 GW cm<sup>−2</sup>). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140314611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-14DOI: 10.1088/1361-6641/ad2ec6
M Derya Alyörük
The electronic transport characteristics of tungsten disulfide (WS2) sheets are studied using the ensemble Monte Carlo technique in the presence of intrinsic scattering mechanisms only. The transport properties of the material are obtained in a two-valley model where intra- and inter-valley scatterings are considered in K and Q valleys. The velocity overshoot effect is observed for some applied field values. Negative differential phenomena are seen for some values of the energy difference between K and Q valleys (ΔEKQ), therefore ΔEKQ and the effective mass of carriers in the Q valley has a critical role in the transport and mobility characteristics of WS2. The mobility of carriers is calculated as a function of temperature and the results are compatible with some existing theoretical and experimental predictions.
在仅存在内在散射机制的情况下，使用集合蒙特卡罗技术研究了二硫化钨（WS2）薄片的电子传输特性。材料的输运特性是在双谷模型中获得的，其中考虑了 K 谷和 Q 谷中的谷内和谷间散射。在某些外加磁场值中观察到了速度过冲效应。在 K 谷和 Q 谷之间能量差（ΔEKQ）的某些值上会出现负差分现象，因此ΔEKQ 和 Q 谷中载流子的有效质量对 WS2 的传输和迁移率特性起着至关重要的作用。我们计算了载流子的迁移率与温度的函数关系，结果与现有的一些理论和实验预测相符。
{"title":"Electronic transport properties of WS2 using ensemble Monte Carlo method","authors":"M Derya Alyörük","doi":"10.1088/1361-6641/ad2ec6","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2ec6","url":null,"abstract":"The electronic transport characteristics of tungsten disulfide (WS<sub>2</sub>) sheets are studied using the ensemble Monte Carlo technique in the presence of intrinsic scattering mechanisms only. The transport properties of the material are obtained in a two-valley model where intra- and inter-valley scatterings are considered in K and Q valleys. The velocity overshoot effect is observed for some applied field values. Negative differential phenomena are seen for some values of the energy difference between K and Q valleys (<inline-formula>\u0000<tex-math><?CDATA $Delta E_mathrm{KQ}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:mi mathvariant=\"normal\">Δ</mml:mi><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:mi mathvariant=\"normal\">K</mml:mi><mml:mi mathvariant=\"normal\">Q</mml:mi></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad2ec6ieqn1.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula>), therefore <inline-formula>\u0000<tex-math><?CDATA $Delta E_mathrm{KQ}$?></tex-math>\u0000<mml:math overflow=\"scroll\"><mml:mi mathvariant=\"normal\">Δ</mml:mi><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:mi mathvariant=\"normal\">K</mml:mi><mml:mi mathvariant=\"normal\">Q</mml:mi></mml:mrow></mml:msub></mml:math>\u0000<inline-graphic xlink:href=\"sstad2ec6ieqn2.gif\" xlink:type=\"simple\"></inline-graphic>\u0000</inline-formula> and the effective mass of carriers in the Q valley has a critical role in the transport and mobility characteristics of WS<sub>2</sub>. The mobility of carriers is calculated as a function of temperature and the results are compatible with some existing theoretical and experimental predictions.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140314459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-12DOI: 10.1088/1361-6641/ad2bac
Alexander K Sten, Kevin M Roccapriore, Brian Squires, Chris Littler, A J Syllaios, Usha Philipose
The present work highlights the role of halogen compounds in modifying the shape of the InSb nanostructures, while maintaining a high crystalline quality of the nanostructures. One-dimensional (1D) nanowires (NWs) and two-dimensional (2D) nanoplatelets (NPLs) were synthesized by ambient pressure chemical vapor deposition. Our experimental results suggest that at a critical growth temperature of 512 ∘C, InSb NWs grow by the traditional vapor–liquid–solid growth mechanism when gold (Au) nanoparticles are used to initiate growth on an InSb film. The resulting NWs were found to have a cylindrical or tapered shape, were of high crystalline quality, and had stoichiometric composition. In the presence of halogen precursors, a change in morphology was observed and the resulting nanostructures were 2D NPLs and faceted NWs. Using existing models of crystal growth and concepts of volume, surface and edge energies, the experimental results are explained on the basis of chlorine atoms adsorbed on the wide or narrow facets of a nanocrystal, initiating nucleation and facilitating NPL or faceted NW formation. The incorporation of the chlorine atoms add a new degree of freedom to CVD synthesis of nanostructures and the results are promising for the controlled growth of novel 1D and 2D nanostructures for nano-electronic devices.
{"title":"Influence of halogen precursors on the growth of InSb nanostructures","authors":"Alexander K Sten, Kevin M Roccapriore, Brian Squires, Chris Littler, A J Syllaios, Usha Philipose","doi":"10.1088/1361-6641/ad2bac","DOIUrl":"https://doi.org/10.1088/1361-6641/ad2bac","url":null,"abstract":"The present work highlights the role of halogen compounds in modifying the shape of the InSb nanostructures, while maintaining a high crystalline quality of the nanostructures. One-dimensional (1D) nanowires (NWs) and two-dimensional (2D) nanoplatelets (NPLs) were synthesized by ambient pressure chemical vapor deposition. Our experimental results suggest that at a critical growth temperature of 512 <sup>∘</sup>C, InSb NWs grow by the traditional vapor–liquid–solid growth mechanism when gold (Au) nanoparticles are used to initiate growth on an InSb film. The resulting NWs were found to have a cylindrical or tapered shape, were of high crystalline quality, and had stoichiometric composition. In the presence of halogen precursors, a change in morphology was observed and the resulting nanostructures were 2D NPLs and faceted NWs. Using existing models of crystal growth and concepts of volume, surface and edge energies, the experimental results are explained on the basis of chlorine atoms adsorbed on the wide or narrow facets of a nanocrystal, initiating nucleation and facilitating NPL or faceted NW formation. The incorporation of the chlorine atoms add a new degree of freedom to CVD synthesis of nanostructures and the results are promising for the controlled growth of novel 1D and 2D nanostructures for nano-electronic devices.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140316803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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