Pub Date : 2024-03-11DOI: 10.1088/1361-6641/ad3275
C. Deng, Zhizhong Chen, Yifan Chen, Qian Sun, J. Nie, Z. Pan, Haodong Zhang, Boyan Dong, Yian Chen, Daqi Wang, Yuchen Li, Weihua Chen, Xiangning Kang, Qi Wang, Guoyi Zhang, B. Shen, Huijuan Wang, Fei Wang, Wei Wang, Zhongxiao Li
Quantum dots (QDs) have been paid much attention on the color conversion for light-emitting diode (LED) in micro-display recently. However, it is hard to achieve high color conversion efficiency in a thin QD layer. In this paper, we fabricated silver nanoparticles (Ag NPs) with radii ranging mostly from 25 to 35 nm on a blue LED with a peak wavelength of 450 nm, then spin-coated QDs with a peak wavelength of 565 nm. Scanning electron microscopy (SEM), cathodoluminescence (CL), photoluminescence (PL), and time-resolved PL (TRPL) measurements were performed. The PL emissions from quantum wells (QWs) of blue LED and QDs were enhanced by 10% and 32%, respectively, when the Ag NPs were included. The PL lifetimes of QWs and QDs were reduced by 10 and 6 times, respectively, compared to their initial states. Finite Difference Time Domain (FDTD) software and the perturbation method were used to simulate the PL measurements and variable separation. It was concluded that the coupling of QDs and QWs with localized surface plasmon (LSP) improves the external quantum efficiency (EQE) and enhances the spontaneous emission rate in both QWs and QDs. This paper provides a new idea for designing high-efficiency color conversion micro-LED.
{"title":"Simultaneous enhancements on emissions from quantum dot and quantum well by Ag nanoparticles for color conversion","authors":"C. Deng, Zhizhong Chen, Yifan Chen, Qian Sun, J. Nie, Z. Pan, Haodong Zhang, Boyan Dong, Yian Chen, Daqi Wang, Yuchen Li, Weihua Chen, Xiangning Kang, Qi Wang, Guoyi Zhang, B. Shen, Huijuan Wang, Fei Wang, Wei Wang, Zhongxiao Li","doi":"10.1088/1361-6641/ad3275","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3275","url":null,"abstract":"\u0000 Quantum dots (QDs) have been paid much attention on the color conversion for light-emitting diode (LED) in micro-display recently. However, it is hard to achieve high color conversion efficiency in a thin QD layer. In this paper, we fabricated silver nanoparticles (Ag NPs) with radii ranging mostly from 25 to 35 nm on a blue LED with a peak wavelength of 450 nm, then spin-coated QDs with a peak wavelength of 565 nm. Scanning electron microscopy (SEM), cathodoluminescence (CL), photoluminescence (PL), and time-resolved PL (TRPL) measurements were performed. The PL emissions from quantum wells (QWs) of blue LED and QDs were enhanced by 10% and 32%, respectively, when the Ag NPs were included. The PL lifetimes of QWs and QDs were reduced by 10 and 6 times, respectively, compared to their initial states. Finite Difference Time Domain (FDTD) software and the perturbation method were used to simulate the PL measurements and variable separation. It was concluded that the coupling of QDs and QWs with localized surface plasmon (LSP) improves the external quantum efficiency (EQE) and enhances the spontaneous emission rate in both QWs and QDs. This paper provides a new idea for designing high-efficiency color conversion micro-LED.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140253842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a Negative Capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, Tfe of 3nm, the energy consumption of the proposed accurate NCFET based CiM design is ~82.48% lower in comparison to the conventional/Non CiM full adder design and ~ 85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at VDD = 0.5V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ~4.19x lower energy consumption and ~4.47x lower energy consumption in approximation mode when compared to the baseline 40nm CMOS design at VDD=0.5V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.
{"title":"Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices","authors":"Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Sivasankar Yellampalli, Ramesh Vaddi","doi":"10.1088/1361-6641/ad3273","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3273","url":null,"abstract":"\u0000 Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a Negative Capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, Tfe of 3nm, the energy consumption of the proposed accurate NCFET based CiM design is ~82.48% lower in comparison to the conventional/Non CiM full adder design and ~ 85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at VDD = 0.5V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ~4.19x lower energy consumption and ~4.47x lower energy consumption in approximation mode when compared to the baseline 40nm CMOS design at VDD=0.5V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140253620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-11DOI: 10.1088/1361-6641/ad3274
Yihang Qiu, Li Wei
A novel GaN trench gate vertical MOSFET (PSGT-MOSFET) with a double-shield structure composed of a separated gate (SG) and a p-type shielding layer (P_shield) is proposed and investigated. The p-type shielding layer (P_shield) is positioned within the drift region, which can suppress the electric field peak at the bottom of the trench during the off state. This helps to prevent premature breakdown of the gate oxide layer. Additionally, the presence of P_shield enables the device to have adaptive voltage withstand characteristics. The separated gate (SG) can convert a portion of gate to- -drain capacitance (Cgd) into drain-to-source capacitance (Cds), significantly reducing the gate-to-drain charge of the device. This improvement in charge distribution helps enhance the switching characteristics of the device. Later, the impact of the position and length of the p-type shielding layer (P_shield) on the breakdown voltage (BV) and specific on-resistance (Ron_sp) was studied. The influence of the position and length of the separated gate (SG) on gate charge (Qgd) and breakdown voltage was also investigated. Through TCAD simulations, the parameters of P_shield and SG were optimized. Compared to conventional GaN TG-MOSFET with the same structural parameters, the gate charge was reduced by 88%. In addition, this paper also discusses the principle of adaptive voltage withstand in PSGT-MOSFET.
本文提出并研究了一种新型氮化镓沟槽栅垂直 MOSFET(PSGT-MOSFET),它具有由分离栅极(SG)和 p 型屏蔽层(P_shield)组成的双屏蔽结构。p 型屏蔽层 (P_shield) 位于漂移区内,可以抑制关断状态下沟槽底部的电场峰值。这有助于防止栅极氧化层过早击穿。此外,P_shield 的存在还能使器件具有自适应耐压特性。分离栅极 (SG) 可以将部分栅极-漏极电容 (Cgd) 转换为漏极-源极电容 (Cds),从而显著降低器件的栅极-漏极电荷。电荷分布的改善有助于提高器件的开关特性。随后,研究了 p 型屏蔽层(P_shield)的位置和长度对击穿电压(BV)和比导通电阻(Ron_sp)的影响。此外,还研究了分离栅极(SG)的位置和长度对栅极电荷(Qgd)和击穿电压的影响。通过 TCAD 仿真,对 P_shield 和 SG 的参数进行了优化。与具有相同结构参数的传统 GaN TG-MOSFET 相比,栅极电荷减少了 88%。此外,本文还讨论了 PSGT-MOSFET 的自适应电压承受原理。
{"title":"The GaN trench MOSFET with adaptive voltage tolerance achieved through a dual-shielding structure","authors":"Yihang Qiu, Li Wei","doi":"10.1088/1361-6641/ad3274","DOIUrl":"https://doi.org/10.1088/1361-6641/ad3274","url":null,"abstract":"\u0000 A novel GaN trench gate vertical MOSFET (PSGT-MOSFET) with a double-shield structure composed of a separated gate (SG) and a p-type shielding layer (P_shield) is proposed and investigated. The p-type shielding layer (P_shield) is positioned within the drift region, which can suppress the electric field peak at the bottom of the trench during the off state. This helps to prevent premature breakdown of the gate oxide layer. Additionally, the presence of P_shield enables the device to have adaptive voltage withstand characteristics. The separated gate (SG) can convert a portion of gate to- -drain capacitance (Cgd) into drain-to-source capacitance (Cds), significantly reducing the gate-to-drain charge of the device. This improvement in charge distribution helps enhance the switching characteristics of the device. Later, the impact of the position and length of the p-type shielding layer (P_shield) on the breakdown voltage (BV) and specific on-resistance (Ron_sp) was studied. The influence of the position and length of the separated gate (SG) on gate charge (Qgd) and breakdown voltage was also investigated. Through TCAD simulations, the parameters of P_shield and SG were optimized. Compared to conventional GaN TG-MOSFET with the same structural parameters, the gate charge was reduced by 88%. In addition, this paper also discusses the principle of adaptive voltage withstand in PSGT-MOSFET.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140251387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1088/1361-6641/ad2b07
Kihwan Choi, James Jungho Pak
In this study, a solution-processed bilayer structure ZrO2/SnO2 resistive switching (RS) random access memory (RRAM) is presented for the first time. The precursors of SnO2 and ZrO2 are Tin(Ⅱ) acetylacetonate (Sn(AcAc)2) and zirconium acetylacetonate (Zr(C5H7O2)4), respectively. The top electrode was deposited with Ti using an E-beam evaporator, and the bottom electrode used an indium–tin–oxide glass wafer. We created three devices: SnO2 single-layer, ZrO2 single-layer, and ZrO2/SnO2 bilayer devices, to compare RS characteristics such as the I–V curve and endurance properties. The SnO2 and ZrO2 single-layer devices showed on/off ratios of approximately 2 and 51, respectively, along with endurance switching cycles exceeding 50 and 100 DC cycles. The bilayer device attained stable RS characteristics over 120 DC endurance switching cycles and increased on/off ratio ∼2.97 × 102. Additionally, the ZrO2/SnO2 bilayer bipolar switching mechanism was explained by considering the Gibbs free energy (ΔG