Epitaxial growth of Ge films on Si(100) substrates has been studied under ultra-high vacuum chemical vapor deposition (CVD) conditions by using digermane (Ge2H6) as the precursor. It was found out that high quality layers with thicknesses beyond 500 nm could be produced at complementary metal–oxide–semiconductor compatible conditions, demonstrating low defect density, sharp and narrow x-ray diffraction peaks, as well as room temperature photoluminescence around 1550 nm. The surface roughness values are comparable to prior reduced pressure CVD results at similar growth temperatures. By employing higher growth temperatures, growth rates are significantly enhanced, resulting in much thicker layers beyond 2000 nm. Smoother sample surface could also be obtained, yielding a state-of-the-art surface root-mean-square roughness value of 0.34 nm for the as-grown sample. At the same time, after being annealed at 750 °C for 20 min, the full width at half maximum (FWHM) of x-ray diffraction 004 rocking curve spectrum of the Ge layer is as low as 88 arcseconds, which stands the best among all Ge/Si samples. The current work has provided important reference for Ge/Si growth with Ge2H6 in low pressure regime and solidified material grounding for Ge-based optoelectronics and Si photonics.
在超高真空化学气相沉积(CVD)条件下,研究人员使用地锗(Ge2H6)作为前驱体,在硅(100)基底上外延生长 Ge 薄膜。研究发现,在互补金属-氧化物-半导体兼容的条件下,可以制备出厚度超过 500 nm 的高质量薄膜层,这些薄膜层具有较低的缺陷密度、尖锐而狭窄的 X 射线衍射峰以及 1550 nm 左右的室温光致发光。表面粗糙度值与之前在类似生长温度下的减压 CVD 结果相当。通过采用更高的生长温度,生长速度得到显著提高,从而得到厚度超过 2000 nm 的薄膜层。样品表面也变得更加光滑,生长后的样品表面均方根粗糙度值为 0.34 nm。同时,在 750 °C 下退火 20 分钟后,Ge 层的 X 射线衍射 004 摇摆曲线光谱的半最大全宽(FWHM)低至 88 弧秒,在所有 Ge/Si 样品中名列前茅。目前的研究工作为在低压条件下利用 Ge2H6 生长 Ge/Si 提供了重要参考,并为 Ge 基光电子学和硅光子学奠定了坚实的材料基础。
{"title":"Epitaxial growth of high-quality Ge layers on Si with Ge2H6 under UHV-CVD conditions","authors":"Changjiang Xie, Yue Li, Chi Xu, Yixin Wang, Hui Cong, Chunlai Xue","doi":"10.1088/1361-6641/ad14ee","DOIUrl":"https://doi.org/10.1088/1361-6641/ad14ee","url":null,"abstract":"Epitaxial growth of Ge films on Si(100) substrates has been studied under ultra-high vacuum chemical vapor deposition (CVD) conditions by using digermane (Ge2H6) as the precursor. It was found out that high quality layers with thicknesses beyond 500 nm could be produced at complementary metal–oxide–semiconductor compatible conditions, demonstrating low defect density, sharp and narrow x-ray diffraction peaks, as well as room temperature photoluminescence around 1550 nm. The surface roughness values are comparable to prior reduced pressure CVD results at similar growth temperatures. By employing higher growth temperatures, growth rates are significantly enhanced, resulting in much thicker layers beyond 2000 nm. Smoother sample surface could also be obtained, yielding a state-of-the-art surface root-mean-square roughness value of 0.34 nm for the as-grown sample. At the same time, after being annealed at 750 °C for 20 min, the full width at half maximum (FWHM) of x-ray diffraction 004 rocking curve spectrum of the Ge layer is as low as 88 arcseconds, which stands the best among all Ge/Si samples. The current work has provided important reference for Ge/Si growth with Ge2H6 in low pressure regime and solidified material grounding for Ge-based optoelectronics and Si photonics.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"17 7","pages":""},"PeriodicalIF":1.9,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138977069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-12DOI: 10.1088/1361-6641/ad10c4
Do Gyun An, Garam Kim, Hyunwoo Kim, Sangwan Kim, Jang Hyun Kim
Artificial intelligence computing requires hardware like central processing units and graphic processing units for data processing. However, excessive heat generated during computations remains a challenge. The paper focuses on the heat issue in logic devices caused by transistor structures. To address the problem, the operational mechanism of the Junctionless Field-Effect Transistor (JLFET) is investigated. JLFET shows potential in mitigating heat-related issues and is compared to other nanosheet (ns) FETs. In the case of JL-nsFET, the change in mobility with increasing temperature is smaller compared to Con-nsFET, resulting in less susceptibility to lattice scattering and thermal resistance (Rth) in self-heating effect situation is 0.43 [K µW−1] for Con-nsFET and 0.414 [K µW−1] for JL-nsFET. The reason why the Rth of JL-nsFET is smaller than that of Con-nsFET is that JL-nsFET uses a source heat injection conduction mechanism and a large heat transfer area by using a bulk channel.
{"title":"Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation","authors":"Do Gyun An, Garam Kim, Hyunwoo Kim, Sangwan Kim, Jang Hyun Kim","doi":"10.1088/1361-6641/ad10c4","DOIUrl":"https://doi.org/10.1088/1361-6641/ad10c4","url":null,"abstract":"Artificial intelligence computing requires hardware like central processing units and graphic processing units for data processing. However, excessive heat generated during computations remains a challenge. The paper focuses on the heat issue in logic devices caused by transistor structures. To address the problem, the operational mechanism of the Junctionless Field-Effect Transistor (JLFET) is investigated. JLFET shows potential in mitigating heat-related issues and is compared to other nanosheet (ns) FETs. In the case of JL-nsFET, the change in mobility with increasing temperature is smaller compared to Con-nsFET, resulting in less susceptibility to lattice scattering and thermal resistance (<italic toggle=\"yes\">R</italic>th) in self-heating effect situation is 0.43 [K <italic toggle=\"yes\">µ</italic>W<sup>−1</sup>] for Con-nsFET and 0.414 [K <italic toggle=\"yes\">µ</italic>W<sup>−1</sup>] for JL-nsFET. The reason why the <italic toggle=\"yes\">R</italic>th of JL-nsFET is smaller than that of Con-nsFET is that JL-nsFET uses a source heat injection conduction mechanism and a large heat transfer area by using a bulk channel.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"56 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138691427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-12DOI: 10.1088/1361-6641/ad14ec
Hideto Onishi, Hajime Shirai
We investigated the reduction in the reverse-biased leakage current of Si ultrafast recovery diodes via a combined lifetime process involving Au diffusion and bulk electron-beam irradiation. The leakage current of the combined-processed diode was significantly reduced to less than one-third of that of the diode processed solely with Au diffusion, maintaining a similar switching time of 32 ns. This reduction was not achievable with the sole use of electron-beam irradiation. Deep-level transient spectroscopy revealed that the reduction in the leakage current was due to the coexistence of the deep trap level of Au (Ec-0.51 eV) and the shallow trap level of the defects (Ec-0.39 eV) generated via electron-beam irradiation as lifetime killers. By combining the deep and shallow trap levels, the lifetime of the carriers generated in the depletion layer of the reverse-biased p-n junction becomes long and consequently, the leakage current is reduced. By maintaining the trap density ratio of defects to diffused Au above 0.28, the leakage current was reduced to less than one-third of that in the solely Au-diffused diode, while maintaining a similar switching time.
{"title":"Silicon ultrafast recovery diode with leakage current reduced via the combined lifetime process of gold diffusion and electron-beam irradiation","authors":"Hideto Onishi, Hajime Shirai","doi":"10.1088/1361-6641/ad14ec","DOIUrl":"https://doi.org/10.1088/1361-6641/ad14ec","url":null,"abstract":"\u0000 We investigated the reduction in the reverse-biased leakage current of Si ultrafast recovery diodes via a combined lifetime process involving Au diffusion and bulk electron-beam irradiation. The leakage current of the combined-processed diode was significantly reduced to less than one-third of that of the diode processed solely with Au diffusion, maintaining a similar switching time of 32 ns. This reduction was not achievable with the sole use of electron-beam irradiation. Deep-level transient spectroscopy revealed that the reduction in the leakage current was due to the coexistence of the deep trap level of Au (Ec-0.51 eV) and the shallow trap level of the defects (Ec-0.39 eV) generated via electron-beam irradiation as lifetime killers. By combining the deep and shallow trap levels, the lifetime of the carriers generated in the depletion layer of the reverse-biased p-n junction becomes long and consequently, the leakage current is reduced. By maintaining the trap density ratio of defects to diffused Au above 0.28, the leakage current was reduced to less than one-third of that in the solely Au-diffused diode, while maintaining a similar switching time.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"45 6","pages":""},"PeriodicalIF":1.9,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139009815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-11DOI: 10.1088/1361-6641/ad0eea
Garima Rana, Pooja Dhiman, Amit Kumar, Elmuez A Dawi, Gaurav Sharma
Photocatalytic H2 evolution and CO2 reduction are promising technologies for addressing environmental and energy issues. g-C3N4 is one of most promising materials to form improved catalysts because of its exceptional electrical structure, physical and chemical characteristics, and distinctive metal-free feature. This article provides a summary of current advancements in g-C3N4-based catalysts from innovative design approaches and their applications. Hydrogen evolution has reached 6305.18 µmol g−1 h−1 and >9 h of stability using the SnS2/g-C3N4 heterojunction. Additionally, the ZnO/Au/g-C3N4 maintains a constant CO generation rate of 689.7 mol m−2 during the 8 h reaction. To fully understand the interior relationship of theory–structure performance on g-C3N4-based materials, modifications are studied simultaneously. Furthermore, the synthesis of g-C3N4 and g-C3N4-based materials, as well as their respective instances, have been reported. The reduction of CO2 and H2 generation is summarized. Lastly, a short overview of the present issues and potential alternatives for g-C3N4-based materials is provided.
{"title":"Recent progress in modifications of g-C3N4 for photocatalytic hydrogen evolution and CO2 reduction","authors":"Garima Rana, Pooja Dhiman, Amit Kumar, Elmuez A Dawi, Gaurav Sharma","doi":"10.1088/1361-6641/ad0eea","DOIUrl":"https://doi.org/10.1088/1361-6641/ad0eea","url":null,"abstract":"Photocatalytic H<sub>2</sub> evolution and CO<sub>2</sub> reduction are promising technologies for addressing environmental and energy issues. g-C<sub>3</sub>N<sub>4</sub> is one of most promising materials to form improved catalysts because of its exceptional electrical structure, physical and chemical characteristics, and distinctive metal-free feature. This article provides a summary of current advancements in g-C<sub>3</sub>N<sub>4</sub>-based catalysts from innovative design approaches and their applications. Hydrogen evolution has reached 6305.18 <italic toggle=\"yes\">µ</italic>mol g<sup>−1</sup> h<sup>−1</sup> and >9 h of stability using the SnS<sub>2</sub>/g-C<sub>3</sub>N<sub>4</sub> heterojunction. Additionally, the ZnO/Au/g-C<sub>3</sub>N<sub>4</sub> maintains a constant CO generation rate of 689.7 mol m<sup>−2</sup> during the 8 h reaction. To fully understand the interior relationship of theory–structure performance on g-C<sub>3</sub>N<sub>4</sub>-based materials, modifications are studied simultaneously. Furthermore, the synthesis of g-C<sub>3</sub>N<sub>4</sub> and g-C<sub>3</sub>N<sub>4</sub>-based materials, as well as their respective instances, have been reported. The reduction of CO<sub>2</sub> and H<sub>2</sub> generation is summarized. Lastly, a short overview of the present issues and potential alternatives for g-C<sub>3</sub>N<sub>4</sub>-based materials is provided.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"6 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2023-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138691425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-07DOI: 10.1088/1361-6641/ad10c3
Nahid Sultan Al-Mamun, James Gallagher, Alan G Jacobs, Karl D Hobart, Travis J Anderson, Brendan P Gunning, Robert J Kaplar, Douglas E Wolfe, Aman Haque
Defect mitigation of electronic devices is conventionally achieved using thermal annealing. To mobilize the defects, very high temperatures are necessary. Since thermal diffusion is random in nature, the process may take a prolonged period of time. In contrast, we demonstrate a room temperature annealing technique that takes only a few seconds. The fundamental mechanism is defect mobilization by atomic scale mechanical force originating from very high current density but low duty cycle electrical pulses. The high-energy electrons lose their momentum upon collision with the defects, yet the low duty cycle suppresses any heat accumulation to keep the temperature ambient. For a 7 × 105 A cm−2 pulsed current, we report an approximately 26% reduction in specific on-resistance, a 50% increase of the rectification ratio with a lower ideality factor, and reverse leakage current for as-fabricated vertical geometry GaN p–n diodes. We characterize the microscopic defect density of the devices before and after the room temperature processing to explain the improvement in the electrical characteristics. Raman analysis reveals an improvement in the crystallinity of the GaN layer and an approximately 40% relaxation of any post-fabrication residual strain compared to the as-received sample. Cross-sectional transmission electron microscopy (TEM) images and geometric phase analysis results of high-resolution TEM images further confirm the effectiveness of the proposed room temperature annealing technique to mitigate defects in the device. No detrimental effect, such as diffusion and/or segregation of elements, is observed as a result of applying a high-density pulsed current, as confirmed by energy dispersive x-ray spectroscopy mapping.
电子器件的缺陷缓解通常是通过热退火来实现的。要使缺陷移动,需要非常高的温度。由于热扩散具有随机性,因此这一过程可能需要很长时间。相比之下,我们展示的室温退火技术只需几秒钟。其基本机制是由高电流密度但低占空比的电脉冲产生的原子级机械力导致的缺陷移动。高能电子在与缺陷碰撞时会失去动量,而低占空比会抑制热量积累,从而保持室温。对于 7 × 105 A cm-2 的脉冲电流,我们的报告显示,比导通电阻降低了约 26%,整流比提高了 50%,ideality 因子和反向漏电流也降低了。我们对室温处理前后器件的微观缺陷密度进行了表征,以解释电气特性的改善。拉曼分析表明,GaN 层的结晶度有所提高,与接收样品相比,制造后的残余应变松弛了约 40%。横截面透射电子显微镜(TEM)图像和高分辨率 TEM 图像的几何相位分析结果进一步证实了室温退火技术在减少器件缺陷方面的有效性。能量色散 X 射线光谱图证实,应用高密度脉冲电流不会产生有害影响,如元素扩散和/或偏析。
{"title":"Improving vertical GaN p–n diode performance with room temperature defect mitigation","authors":"Nahid Sultan Al-Mamun, James Gallagher, Alan G Jacobs, Karl D Hobart, Travis J Anderson, Brendan P Gunning, Robert J Kaplar, Douglas E Wolfe, Aman Haque","doi":"10.1088/1361-6641/ad10c3","DOIUrl":"https://doi.org/10.1088/1361-6641/ad10c3","url":null,"abstract":"Defect mitigation of electronic devices is conventionally achieved using thermal annealing. To mobilize the defects, very high temperatures are necessary. Since thermal diffusion is random in nature, the process may take a prolonged period of time. In contrast, we demonstrate a room temperature annealing technique that takes only a few seconds. The fundamental mechanism is defect mobilization by atomic scale mechanical force originating from very high current density but low duty cycle electrical pulses. The high-energy electrons lose their momentum upon collision with the defects, yet the low duty cycle suppresses any heat accumulation to keep the temperature ambient. For a 7 × 10<sup>5</sup> A cm<sup>−2</sup> pulsed current, we report an approximately 26% reduction in specific on-resistance, a 50% increase of the rectification ratio with a lower ideality factor, and reverse leakage current for as-fabricated vertical geometry GaN p–n diodes. We characterize the microscopic defect density of the devices before and after the room temperature processing to explain the improvement in the electrical characteristics. Raman analysis reveals an improvement in the crystallinity of the GaN layer and an approximately 40% relaxation of any post-fabrication residual strain compared to the as-received sample. Cross-sectional transmission electron microscopy (TEM) images and geometric phase analysis results of high-resolution TEM images further confirm the effectiveness of the proposed room temperature annealing technique to mitigate defects in the device. No detrimental effect, such as diffusion and/or segregation of elements, is observed as a result of applying a high-density pulsed current, as confirmed by energy dispersive x-ray spectroscopy mapping.","PeriodicalId":21585,"journal":{"name":"Semiconductor Science and Technology","volume":"1 1","pages":""},"PeriodicalIF":1.9,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138691572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}