Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246337
O. Pulkkinen, K. Kronlöf
A study of Specification and Description Language (SDL) and VHSIC hardware description language (VHDL) that their semantics differ considerably in several essential areas. The languages can be used to provide descriptions of systems from different and complementary viewpoints. It is shown that these viewpoints can be usefully integrated by defining them as specific views of a more general system model which defines the essentials of the system functionality and architecture. A simple class of dataflow models is selected as the general domain of system descriptions. The SDL and VHDL representations of this domain as well as the meaning of their equivalence to it are defined. These representations outline corresponding subsets of the languages to be used in describing the system model.<>
{"title":"Integration of SDL and VHDL for high-level digital design","authors":"O. Pulkkinen, K. Kronlöf","doi":"10.1109/EURDAC.1992.246337","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246337","url":null,"abstract":"A study of Specification and Description Language (SDL) and VHSIC hardware description language (VHDL) that their semantics differ considerably in several essential areas. The languages can be used to provide descriptions of systems from different and complementary viewpoints. It is shown that these viewpoints can be usefully integrated by defining them as specific views of a more general system model which defines the essentials of the system functionality and architecture. A simple class of dataflow models is selected as the general domain of system descriptions. The SDL and VHDL representations of this domain as well as the meaning of their equivalence to it are defined. These representations outline corresponding subsets of the languages to be used in describing the system model.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114634610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246178
Mark W. Brown
The activity involved in developing a standard intermediate form for the IEEE VHSIC hardware description language (VHDL) is presented. The purpose of this intermediate form is to provide a common computer-aided design (CAD) tool interface for systems described by the VHDL. The IEEE group responsible for developing the standard is introduced, followed by a description of the four-step process used by the group in developing the standard. The current status of the effort is discussed as well as the future plans for converging on the goal of developing a standard intermediate form for VHDL.<>
{"title":"VHDL intermediate form standardization: process, issues and status","authors":"Mark W. Brown","doi":"10.1109/EURDAC.1992.246178","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246178","url":null,"abstract":"The activity involved in developing a standard intermediate form for the IEEE VHSIC hardware description language (VHDL) is presented. The purpose of this intermediate form is to provide a common computer-aided design (CAD) tool interface for systems described by the VHDL. The IEEE group responsible for developing the standard is introduced, followed by a description of the four-step process used by the group in developing the standard. The current status of the effort is discussed as well as the future plans for converging on the goal of developing a standard intermediate form for VHDL.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129607589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246308
J. C. López, M. Jacome, S. W. Director
Decision-making support based on prediction and advice is a fundamental resource that can be used to reduce search in the design space. The authors discuss the advantages of providing CAD frameworks with a general design assistance facility and the basic methodology that should underlay the implementation of such a facility. A general purpose design assistance metal-tool that successfully realizes the proposed methodology is described. This tool has been integrated into the Odyssey CAD Framework.<>
{"title":"Design assistance for CAD frameworks","authors":"J. C. López, M. Jacome, S. W. Director","doi":"10.1109/EURDAC.1992.246308","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246308","url":null,"abstract":"Decision-making support based on prediction and advice is a fundamental resource that can be used to reduce search in the design space. The authors discuss the advantages of providing CAD frameworks with a general design assistance facility and the basic methodology that should underlay the implementation of such a facility. A general purpose design assistance metal-tool that successfully realizes the proposed methodology is described. This tool has been integrated into the Odyssey CAD Framework.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125395943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246243
P. Windirsch, H. Herpel, A. Laudenbach, M. Glesner
A methodology for the design of microelectronic subsystems in a mechatronic environment is presented, and its application to various problems is described. Several strategies from hardware-in-the-loop simulation over rapid prototyping of ASIC-based systems with field programmable gate arrays to the design of application-specific integrated processors are offered. The efficiency of the design system is demonstrated for three mechatronic applications: a self-controlled clutch, ignition control of a combustion engine, and a turbine compressor unit state estimator.<>
{"title":"Application-specific microelectronics for mechatronic systems","authors":"P. Windirsch, H. Herpel, A. Laudenbach, M. Glesner","doi":"10.1109/EURDAC.1992.246243","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246243","url":null,"abstract":"A methodology for the design of microelectronic subsystems in a mechatronic environment is presented, and its application to various problems is described. Several strategies from hardware-in-the-loop simulation over rapid prototyping of ASIC-based systems with field programmable gate arrays to the design of application-specific integrated processors are offered. The efficiency of the design system is demonstrated for three mechatronic applications: a self-controlled clutch, ignition control of a combustion engine, and a turbine compressor unit state estimator.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122215439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246317
M. Pabst, T. Villa, A. Newton
Synthesis of testable sequential circuits has been proposed as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies (CRs) and sequential redundancies (SRs). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault testability of finite state machines (FSMs) implemented with different synthesis tools have been carried out. The benchmark suite included MCNC and ISCAS circuits as well as industrial examples from Siemens. The experiments showed that SRs requiring intensive CPU time and memory space to be detected occur very seldom. Single-stuck fault coverage obtained by state-of-the-art synthesis and test generation algorithms is >99% for non-scan FSMs with up to about 100 states.<>
{"title":"Experiments on the synthesis and testability of non-scan finite state machines","authors":"M. Pabst, T. Villa, A. Newton","doi":"10.1109/EURDAC.1992.246317","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246317","url":null,"abstract":"Synthesis of testable sequential circuits has been proposed as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies (CRs) and sequential redundancies (SRs). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault testability of finite state machines (FSMs) implemented with different synthesis tools have been carried out. The benchmark suite included MCNC and ISCAS circuits as well as industrial examples from Siemens. The experiments showed that SRs requiring intensive CPU time and memory space to be detected occur very seldom. Single-stuck fault coverage obtained by state-of-the-art synthesis and test generation algorithms is >99% for non-scan FSMs with up to about 100 states.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246221
M. Nourani, C. Papachristou, Yoshiyasu Takefuji
A new scheduling approach for high-level synthesis based on a deterministic modified Hopfield model is presented. The model uses a four-dimensional neural network architecture to schedule the operations of a data flow graph (DFG), and maps them to specific functional units. Neural network-based scheduling (NNS) is achieved by formulating the scheduling problem in terms of an energy function, and by using the motion equation corresponding to the variation of energy. The algorithm searches the scheduling space in parallel and finds the optimal schedule. This yields an efficient parallel scheduling algorithm under time and resource constraints appropriate for implementing on a parallel machine. The algorithm is based on moves in the scheduling space, which correspond to moves towards the equilibrium point (lowest energy state) in the dynamic system space.<>
{"title":"A neural network based algorithm for the scheduling problem in high-level synthesis","authors":"M. Nourani, C. Papachristou, Yoshiyasu Takefuji","doi":"10.1109/EURDAC.1992.246221","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246221","url":null,"abstract":"A new scheduling approach for high-level synthesis based on a deterministic modified Hopfield model is presented. The model uses a four-dimensional neural network architecture to schedule the operations of a data flow graph (DFG), and maps them to specific functional units. Neural network-based scheduling (NNS) is achieved by formulating the scheduling problem in terms of an energy function, and by using the motion equation corresponding to the variation of energy. The algorithm searches the scheduling space in parallel and finds the optimal schedule. This yields an efficient parallel scheduling algorithm under time and resource constraints appropriate for implementing on a parallel machine. The algorithm is based on moves in the scheduling space, which correspond to moves towards the equilibrium point (lowest energy state) in the dynamic system space.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124462297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246204
Christoph Hübel, D. Ruland, E. Siepmann
The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4) design object model; and (5) design subject model. The design structure model is introduced for modeling on a higher level of abstraction exactly those aspects of design objects which are necessary for design methodology management. The applied concept is called design object abstraction.<>
{"title":"On modeling integrated design environments","authors":"Christoph Hübel, D. Ruland, E. Siepmann","doi":"10.1109/EURDAC.1992.246204","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246204","url":null,"abstract":"The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4) design object model; and (5) design subject model. The design structure model is introduced for modeling on a higher level of abstraction exactly those aspects of design objects which are necessary for design methodology management. The applied concept is called design object abstraction.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126296932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246190
Christel Oczko, Michael W. Nitsche
Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<>
{"title":"Multi-kernel simulation description within VHDL","authors":"Christel Oczko, Michael W. Nitsche","doi":"10.1109/EURDAC.1992.246190","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246190","url":null,"abstract":"Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132287929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246213
Haigeng Wang, N. Dutt, A. Nicolau
Linear difference equations involving recurrences are fundamental equations that describe many important signal processing applications. For many high sample rate digital filter applications, it is necessary to effectively parallelize the linear difference equations used to describe digital filters. This is difficult because of the recurrences inherent in the data dependences. The authors present a novel approach, harmonic scheduling, that exploits parallelism in these recurrences beyond loop-carried dependencies, and which generates optimal schedules for parallel evaluation of linear difference equations with resource constraints. This approach also enables the derivation of a parallel schedule with minimum control overhead, given an execution time with resource constraints. A harmonic scheduling algorithm is presented to generate optimal schedules for digital filters described by second-order difference equations with resource constraints.<>
{"title":"Harmonic scheduling of linear recurrences for digital filter design","authors":"Haigeng Wang, N. Dutt, A. Nicolau","doi":"10.1109/EURDAC.1992.246213","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246213","url":null,"abstract":"Linear difference equations involving recurrences are fundamental equations that describe many important signal processing applications. For many high sample rate digital filter applications, it is necessary to effectively parallelize the linear difference equations used to describe digital filters. This is difficult because of the recurrences inherent in the data dependences. The authors present a novel approach, harmonic scheduling, that exploits parallelism in these recurrences beyond loop-carried dependencies, and which generates optimal schedules for parallel evaluation of linear difference equations with resource constraints. This approach also enables the derivation of a parallel schedule with minimum control overhead, given an execution time with resource constraints. A harmonic scheduling algorithm is presented to generate optimal schedules for digital filters described by second-order difference equations with resource constraints.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123018342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246240
Klaus Glasmacher, G. Zimmermann
Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard cell block layout is used to demonstrate a new strategy. Instead of generating the layouts of blocks in the same floorplan independently, layout proceeds in parallel and constraints like pin positions, shape and position of the blocks in the floorplan are exchanged dynamically. This method results in excellent adjustment of pin positions between cells and reduction of channel widths. Independent of the cell synthesis strategy is cell assembly, viewed as a topological compaction problem to refine the floorplans. A genetic algorithm is shown to solve this problem. Initial experimental results show the advantages of the new strategies.<>
{"title":"Chip assembly in the PLAYOUT VLSI design system","authors":"Klaus Glasmacher, G. Zimmermann","doi":"10.1109/EURDAC.1992.246240","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246240","url":null,"abstract":"Chip assembly in PLAYOUT is designed for top-down chip planning. An example of a three-level hierarchy demonstrates the new design strategy. Three-phase chip planning and chip assembly have close interaction to guarantee an exchange of constraints between levels of the hierarchy. Chip assembly is composed of two different functions: cell synthesis, and cell assembly. For cell synthesis, standard cell block layout is used to demonstrate a new strategy. Instead of generating the layouts of blocks in the same floorplan independently, layout proceeds in parallel and constraints like pin positions, shape and position of the blocks in the floorplan are exchanged dynamically. This method results in excellent adjustment of pin positions between cells and reduction of channel widths. Independent of the cell synthesis strategy is cell assembly, viewed as a topological compaction problem to refine the floorplans. A genetic algorithm is shown to solve this problem. Initial experimental results show the advantages of the new strategies.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123672474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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