Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246243
P. Windirsch, H. Herpel, A. Laudenbach, M. Glesner
A methodology for the design of microelectronic subsystems in a mechatronic environment is presented, and its application to various problems is described. Several strategies from hardware-in-the-loop simulation over rapid prototyping of ASIC-based systems with field programmable gate arrays to the design of application-specific integrated processors are offered. The efficiency of the design system is demonstrated for three mechatronic applications: a self-controlled clutch, ignition control of a combustion engine, and a turbine compressor unit state estimator.<>
{"title":"Application-specific microelectronics for mechatronic systems","authors":"P. Windirsch, H. Herpel, A. Laudenbach, M. Glesner","doi":"10.1109/EURDAC.1992.246243","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246243","url":null,"abstract":"A methodology for the design of microelectronic subsystems in a mechatronic environment is presented, and its application to various problems is described. Several strategies from hardware-in-the-loop simulation over rapid prototyping of ASIC-based systems with field programmable gate arrays to the design of application-specific integrated processors are offered. The efficiency of the design system is demonstrated for three mechatronic applications: a self-controlled clutch, ignition control of a combustion engine, and a turbine compressor unit state estimator.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122215439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246204
Christoph Hübel, D. Ruland, E. Siepmann
The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4) design object model; and (5) design subject model. The design structure model is introduced for modeling on a higher level of abstraction exactly those aspects of design objects which are necessary for design methodology management. The applied concept is called design object abstraction.<>
{"title":"On modeling integrated design environments","authors":"Christoph Hübel, D. Ruland, E. Siepmann","doi":"10.1109/EURDAC.1992.246204","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246204","url":null,"abstract":"The authors describe an approach towards modeling the heterogeneous aspects of design environments which is based on a paradigm of separation and integration, yielding an adequate, well structured, non-redundant, and integrated design model for generic design environments. The design model consists of five partial models: (1) design flow model; (2) design tool model; (3) design structure model; (4) design object model; and (5) design subject model. The design structure model is introduced for modeling on a higher level of abstraction exactly those aspects of design objects which are necessary for design methodology management. The applied concept is called design object abstraction.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126296932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246308
J. C. López, M. Jacome, S. W. Director
Decision-making support based on prediction and advice is a fundamental resource that can be used to reduce search in the design space. The authors discuss the advantages of providing CAD frameworks with a general design assistance facility and the basic methodology that should underlay the implementation of such a facility. A general purpose design assistance metal-tool that successfully realizes the proposed methodology is described. This tool has been integrated into the Odyssey CAD Framework.<>
{"title":"Design assistance for CAD frameworks","authors":"J. C. López, M. Jacome, S. W. Director","doi":"10.1109/EURDAC.1992.246308","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246308","url":null,"abstract":"Decision-making support based on prediction and advice is a fundamental resource that can be used to reduce search in the design space. The authors discuss the advantages of providing CAD frameworks with a general design assistance facility and the basic methodology that should underlay the implementation of such a facility. A general purpose design assistance metal-tool that successfully realizes the proposed methodology is described. This tool has been integrated into the Odyssey CAD Framework.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125395943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246317
M. Pabst, T. Villa, A. Newton
Synthesis of testable sequential circuits has been proposed as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies (CRs) and sequential redundancies (SRs). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault testability of finite state machines (FSMs) implemented with different synthesis tools have been carried out. The benchmark suite included MCNC and ISCAS circuits as well as industrial examples from Siemens. The experiments showed that SRs requiring intensive CPU time and memory space to be detected occur very seldom. Single-stuck fault coverage obtained by state-of-the-art synthesis and test generation algorithms is >99% for non-scan FSMs with up to about 100 states.<>
{"title":"Experiments on the synthesis and testability of non-scan finite state machines","authors":"M. Pabst, T. Villa, A. Newton","doi":"10.1109/EURDAC.1992.246317","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246317","url":null,"abstract":"Synthesis of testable sequential circuits has been proposed as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies (CRs) and sequential redundancies (SRs). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault testability of finite state machines (FSMs) implemented with different synthesis tools have been carried out. The benchmark suite included MCNC and ISCAS circuits as well as industrial examples from Siemens. The experiments showed that SRs requiring intensive CPU time and memory space to be detected occur very seldom. Single-stuck fault coverage obtained by state-of-the-art synthesis and test generation algorithms is >99% for non-scan FSMs with up to about 100 states.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246178
Mark W. Brown
The activity involved in developing a standard intermediate form for the IEEE VHSIC hardware description language (VHDL) is presented. The purpose of this intermediate form is to provide a common computer-aided design (CAD) tool interface for systems described by the VHDL. The IEEE group responsible for developing the standard is introduced, followed by a description of the four-step process used by the group in developing the standard. The current status of the effort is discussed as well as the future plans for converging on the goal of developing a standard intermediate form for VHDL.<>
{"title":"VHDL intermediate form standardization: process, issues and status","authors":"Mark W. Brown","doi":"10.1109/EURDAC.1992.246178","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246178","url":null,"abstract":"The activity involved in developing a standard intermediate form for the IEEE VHSIC hardware description language (VHDL) is presented. The purpose of this intermediate form is to provide a common computer-aided design (CAD) tool interface for systems described by the VHDL. The IEEE group responsible for developing the standard is introduced, followed by a description of the four-step process used by the group in developing the standard. The current status of the effort is discussed as well as the future plans for converging on the goal of developing a standard intermediate form for VHDL.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129607589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246221
M. Nourani, C. Papachristou, Yoshiyasu Takefuji
A new scheduling approach for high-level synthesis based on a deterministic modified Hopfield model is presented. The model uses a four-dimensional neural network architecture to schedule the operations of a data flow graph (DFG), and maps them to specific functional units. Neural network-based scheduling (NNS) is achieved by formulating the scheduling problem in terms of an energy function, and by using the motion equation corresponding to the variation of energy. The algorithm searches the scheduling space in parallel and finds the optimal schedule. This yields an efficient parallel scheduling algorithm under time and resource constraints appropriate for implementing on a parallel machine. The algorithm is based on moves in the scheduling space, which correspond to moves towards the equilibrium point (lowest energy state) in the dynamic system space.<>
{"title":"A neural network based algorithm for the scheduling problem in high-level synthesis","authors":"M. Nourani, C. Papachristou, Yoshiyasu Takefuji","doi":"10.1109/EURDAC.1992.246221","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246221","url":null,"abstract":"A new scheduling approach for high-level synthesis based on a deterministic modified Hopfield model is presented. The model uses a four-dimensional neural network architecture to schedule the operations of a data flow graph (DFG), and maps them to specific functional units. Neural network-based scheduling (NNS) is achieved by formulating the scheduling problem in terms of an energy function, and by using the motion equation corresponding to the variation of energy. The algorithm searches the scheduling space in parallel and finds the optimal schedule. This yields an efficient parallel scheduling algorithm under time and resource constraints appropriate for implementing on a parallel machine. The algorithm is based on moves in the scheduling space, which correspond to moves towards the equilibrium point (lowest energy state) in the dynamic system space.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124462297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246273
Yogesh Mishra, S. Sherlekar, G. Venkatesh
The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns's and A.J. Martin's (1988) method.<>
{"title":"Path Breaker: a tool for the optimal design of speed independent asynchronous controllers","authors":"Yogesh Mishra, S. Sherlekar, G. Venkatesh","doi":"10.1109/EURDAC.1992.246273","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246273","url":null,"abstract":"The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns's and A.J. Martin's (1988) method.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115899144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246190
Christel Oczko, Michael W. Nitsche
Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<>
{"title":"Multi-kernel simulation description within VHDL","authors":"Christel Oczko, Michael W. Nitsche","doi":"10.1109/EURDAC.1992.246190","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246190","url":null,"abstract":"Summary form only given. The authors describe ongoing work on multikernel description facilities within VHSIC hardware description language (VHDL) which is performed in the scope of ECIP (European CAD Integration Project). The motivation, aims, and scope of the work are outlined.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132287929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246259
T. Kam, P. Subrahmanyam
The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo.cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are common starting points for various sequential synthesis and verification tools.<>
{"title":"State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis","authors":"T. Kam, P. Subrahmanyam","doi":"10.1109/EURDAC.1992.246259","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246259","url":null,"abstract":"The authors discuss a formal technique for abstracting a finite state machine (FSM) from a transistor netlist, given information relating to clock signals and clo.cking methodology. The abstracted FSM is represented as a transition relation using binary decision diagrams (BDDs) and then converted into a synchronous sequential network. Both the relational and network representations are common starting points for various sequential synthesis and verification tools.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130054900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246271
J. Sparsø, J. Staunstrup, Michael Dantzer-Sørensen
The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec.tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed.<>
{"title":"Design of delay insensitive circuits using multi-ring structures","authors":"J. Sparsø, J. Staunstrup, Michael Dantzer-Sørensen","doi":"10.1109/EURDAC.1992.246271","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246271","url":null,"abstract":"The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec.tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial functionality and reasonable performance are readily designed.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：