Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246187
G. Umbreit
When integrating formal methods into the design process, VHSIC hardware description language (VHDL) is unavoidable. A VHDL front end for the proof system LAMBDA is presented. The idea is to provide support for almost the full VHDL language and to generate executable ML descriptions that closely resemble the original VHDL programs. Choosing a purely functional approach has the benefit that the generated programs can be animated. This improves the testability of the translator.<>
{"title":"Providing a VHDL-interface for proof systems","authors":"G. Umbreit","doi":"10.1109/EURDAC.1992.246187","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246187","url":null,"abstract":"When integrating formal methods into the design process, VHSIC hardware description language (VHDL) is unavoidable. A VHDL front end for the proof system LAMBDA is presented. The idea is to provide support for almost the full VHDL language and to generate executable ML descriptions that closely resemble the original VHDL programs. Choosing a purely functional approach has the benefit that the generated programs can be animated. This improves the testability of the translator.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246238
W. Wan, M. Perkowski
An approach to the decomposition of incompletely specified Boolean functions is introduced, and its application to lookup-table-based field programmable gate array (FPGA) mapping is described. Three methods are developed: fast graph coloring to perform a quasi-optimum 'don't care' assignment; variable partitioning to quickly find the 'best' partitions; and local transformation to transform a nondecomposable function into several decomposable ones. The methods perform global optimization of the input function. A short description of a FPGA mapping program (TRADE) and an evaluation of its results are provided.<>
{"title":"A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping","authors":"W. Wan, M. Perkowski","doi":"10.1109/EURDAC.1992.246238","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246238","url":null,"abstract":"An approach to the decomposition of incompletely specified Boolean functions is introduced, and its application to lookup-table-based field programmable gate array (FPGA) mapping is described. Three methods are developed: fast graph coloring to perform a quasi-optimum 'don't care' assignment; variable partitioning to quickly find the 'best' partitions; and local transformation to transform a nondecomposable function into several decomposable ones. The methods perform global optimization of the input function. A short description of a FPGA mapping program (TRADE) and an evaluation of its results are provided.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128675316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246257
M. Imai, J. Sato, A. Alomary, N. Hikichi
A new algorithm for instruction implementation method selection problem (IMSP) in application specific integrated processors (ASIP) design automation is proposed. This problem is to be solved in the instruction set architecture and CPU core architecture designs. First, the IMSP is formalized as an integer programming problem, which is to maximize the performance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. This algorithm will automate the complex parts of the ASIP chip design.<>
{"title":"An integer programming approach to instruction implementation method selection problem","authors":"M. Imai, J. Sato, A. Alomary, N. Hikichi","doi":"10.1109/EURDAC.1992.246257","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246257","url":null,"abstract":"A new algorithm for instruction implementation method selection problem (IMSP) in application specific integrated processors (ASIP) design automation is proposed. This problem is to be solved in the instruction set architecture and CPU core architecture designs. First, the IMSP is formalized as an integer programming problem, which is to maximize the performance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. This algorithm will automate the complex parts of the ASIP chip design.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131019304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246261
M. Schaefer, W. Klein
An integrated design concept that focuses on the correctness of concurrent controllers is presented. This approach is based on the specification of concurrent tasks with the aid of structured flow charts. A new formal proceeding for the verification of the correct behavior is introduced. Algorithms reduce the verification process to a polynomial amount of computational effort. The method can be applied even for the design of large systems.<>
{"title":"Correctness verification of concurrent controller specifications","authors":"M. Schaefer, W. Klein","doi":"10.1109/EURDAC.1992.246261","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246261","url":null,"abstract":"An integrated design concept that focuses on the correctness of concurrent controllers is presented. This approach is based on the specification of concurrent tasks with the aid of structured flow charts. A new formal proceeding for the verification of the correct behavior is introduced. Algorithms reduce the verification process to a polynomial amount of computational effort. The method can be applied even for the design of large systems.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246263
Sanjiv Narayan, D. Gajski
When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis.<>
{"title":"System clock estimation based on clock slack minimization","authors":"Sanjiv Narayan, D. Gajski","doi":"10.1109/EURDAC.1992.246263","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246263","url":null,"abstract":"When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123200841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246309
M. Rumsey, C. Farquhar
Typically, modern design management is achieved through either a data management system or a flow sequence controller. Each is highly productive in specific parts of a design process, but becomes cumbersome in others. A design management approach which is generally applicable throughout the development of a product is presented. It offers flow control and automation to manage readily definable processes, while also being able to ensure data consistency where the task sequence is determined on-the-fly and a process flow cannot be predefined. The capability is part of the Texas Instruments Flagship Design System and is implemented using Falcon Framework technology.<>
{"title":"Unifying tool, data and process flow management","authors":"M. Rumsey, C. Farquhar","doi":"10.1109/EURDAC.1992.246309","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246309","url":null,"abstract":"Typically, modern design management is achieved through either a data management system or a flow sequence controller. Each is highly productive in specific parts of a design process, but becomes cumbersome in others. A design management approach which is generally applicable throughout the development of a product is presented. It offers flow control and automation to manage readily definable processes, while also being able to ensure data consistency where the task sequence is determined on-the-fly and a process flow cannot be predefined. The capability is part of the Texas Instruments Flagship Design System and is implemented using Falcon Framework technology.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127111165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246264
Viraphol Chaiyakul, A. Wu, D. Gajski
A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.<>
{"title":"Timing models for high-level synthesis","authors":"Viraphol Chaiyakul, A. Wu, D. Gajski","doi":"10.1109/EURDAC.1992.246264","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246264","url":null,"abstract":"A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"181 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123285893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246211
R. Llopis, H. Kerkhoff
A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<>
{"title":"A fast and accurate characterization method for full-CMOS circuits","authors":"R. Llopis, H. Kerkhoff","doi":"10.1109/EURDAC.1992.246211","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246211","url":null,"abstract":"A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246337
O. Pulkkinen, K. Kronlöf
A study of Specification and Description Language (SDL) and VHSIC hardware description language (VHDL) that their semantics differ considerably in several essential areas. The languages can be used to provide descriptions of systems from different and complementary viewpoints. It is shown that these viewpoints can be usefully integrated by defining them as specific views of a more general system model which defines the essentials of the system functionality and architecture. A simple class of dataflow models is selected as the general domain of system descriptions. The SDL and VHDL representations of this domain as well as the meaning of their equivalence to it are defined. These representations outline corresponding subsets of the languages to be used in describing the system model.<>
{"title":"Integration of SDL and VHDL for high-level digital design","authors":"O. Pulkkinen, K. Kronlöf","doi":"10.1109/EURDAC.1992.246337","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246337","url":null,"abstract":"A study of Specification and Description Language (SDL) and VHSIC hardware description language (VHDL) that their semantics differ considerably in several essential areas. The languages can be used to provide descriptions of systems from different and complementary viewpoints. It is shown that these viewpoints can be usefully integrated by defining them as specific views of a more general system model which defines the essentials of the system functionality and architecture. A simple class of dataflow models is selected as the general domain of system descriptions. The SDL and VHDL representations of this domain as well as the meaning of their equivalence to it are defined. These representations outline corresponding subsets of the languages to be used in describing the system model.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114634610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246181
David B. Bernstein, Rodney Farrow, David Charness
VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing their use.<>
{"title":"Challenges in the analysis of VHDL","authors":"David B. Bernstein, Rodney Farrow, David Charness","doi":"10.1109/EURDAC.1992.246181","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246181","url":null,"abstract":"VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing their use.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121222924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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