Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246260
H. Graeb, Claudia U. Wieser, K. Antreich
A new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding worst-case distances for all specifications separately. Automatic circuit quality analysis enables a detailed design verification and supports the circuit design process by planning aids for a design step. The various features of the method are illustrated using a small tutorial circuit example. A practical example of an integrated CMOS analog circuit proves the efficiency of the new approach.<>
{"title":"Design verification considering manufacturing tolerances by using worst-case distances","authors":"H. Graeb, Claudia U. Wieser, K. Antreich","doi":"10.1109/EURDAC.1992.246260","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246260","url":null,"abstract":"A new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding worst-case distances for all specifications separately. Automatic circuit quality analysis enables a detailed design verification and supports the circuit design process by planning aids for a design step. The various features of the method are illustrated using a small tutorial circuit example. A practical example of an integrated CMOS analog circuit proves the efficiency of the new approach.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125583027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246246
F. Buijs
The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as bit-slices, just as in manual designs. Comparisons with existing tools show significant improvement.<>
{"title":"ALU synthesis from HDL descriptions to optimized multi-level logic","authors":"F. Buijs","doi":"10.1109/EURDAC.1992.246246","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246246","url":null,"abstract":"The author presents a new tool for automatic ALU (arithmetic and logic unit) synthesis that combines the translation from an HDL to logic level and subsequent multi-level logic synthesis. The existing tools treat ALUs as random logic in that they neglect the regularity of ALUs. These tools do not achieve good results for ALUs. In contrast, the described tool partitions the ALU into blocks such as bit-slices, just as in manual designs. Comparisons with existing tools show significant improvement.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123047300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246261
M. Schaefer, W. Klein
An integrated design concept that focuses on the correctness of concurrent controllers is presented. This approach is based on the specification of concurrent tasks with the aid of structured flow charts. A new formal proceeding for the verification of the correct behavior is introduced. Algorithms reduce the verification process to a polynomial amount of computational effort. The method can be applied even for the design of large systems.<>
{"title":"Correctness verification of concurrent controller specifications","authors":"M. Schaefer, W. Klein","doi":"10.1109/EURDAC.1992.246261","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246261","url":null,"abstract":"An integrated design concept that focuses on the correctness of concurrent controllers is presented. This approach is based on the specification of concurrent tasks with the aid of structured flow charts. A new formal proceeding for the verification of the correct behavior is introduced. Algorithms reduce the verification process to a polynomial amount of computational effort. The method can be applied even for the design of large systems.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246257
M. Imai, J. Sato, A. Alomary, N. Hikichi
A new algorithm for instruction implementation method selection problem (IMSP) in application specific integrated processors (ASIP) design automation is proposed. This problem is to be solved in the instruction set architecture and CPU core architecture designs. First, the IMSP is formalized as an integer programming problem, which is to maximize the performance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. This algorithm will automate the complex parts of the ASIP chip design.<>
{"title":"An integer programming approach to instruction implementation method selection problem","authors":"M. Imai, J. Sato, A. Alomary, N. Hikichi","doi":"10.1109/EURDAC.1992.246257","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246257","url":null,"abstract":"A new algorithm for instruction implementation method selection problem (IMSP) in application specific integrated processors (ASIP) design automation is proposed. This problem is to be solved in the instruction set architecture and CPU core architecture designs. First, the IMSP is formalized as an integer programming problem, which is to maximize the performance of the CPU under the constraints of chip area and power consumption. Then, a branch-and-bound algorithm to solve IMSP is described. According to the experimental results, the proposed algorithm is quite effective and efficient in solving the IMSP. This algorithm will automate the complex parts of the ASIP chip design.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131019304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246263
Sanjiv Narayan, D. Gajski
When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis.<>
{"title":"System clock estimation based on clock slack minimization","authors":"Sanjiv Narayan, D. Gajski","doi":"10.1109/EURDAC.1992.246263","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246263","url":null,"abstract":"When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123200841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246264
Viraphol Chaiyakul, A. Wu, D. Gajski
A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.<>
{"title":"Timing models for high-level synthesis","authors":"Viraphol Chaiyakul, A. Wu, D. Gajski","doi":"10.1109/EURDAC.1992.246264","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246264","url":null,"abstract":"A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"181 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123285893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246211
R. Llopis, H. Kerkhoff
A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<>
{"title":"A fast and accurate characterization method for full-CMOS circuits","authors":"R. Llopis, H. Kerkhoff","doi":"10.1109/EURDAC.1992.246211","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246211","url":null,"abstract":"A fast and accurate method to determine delay, ramp (output rise/fall-time), power dissipation, and upper and lower noise margin values of full-CMOS circuits is presented. It is more than two orders of magnitude faster in comparison to conventional circuit simulations with an average error of 10% per logic cell. It can also deal with multiple time-overlapping inputs, a shortcoming of many current methods.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246309
M. Rumsey, C. Farquhar
Typically, modern design management is achieved through either a data management system or a flow sequence controller. Each is highly productive in specific parts of a design process, but becomes cumbersome in others. A design management approach which is generally applicable throughout the development of a product is presented. It offers flow control and automation to manage readily definable processes, while also being able to ensure data consistency where the task sequence is determined on-the-fly and a process flow cannot be predefined. The capability is part of the Texas Instruments Flagship Design System and is implemented using Falcon Framework technology.<>
{"title":"Unifying tool, data and process flow management","authors":"M. Rumsey, C. Farquhar","doi":"10.1109/EURDAC.1992.246309","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246309","url":null,"abstract":"Typically, modern design management is achieved through either a data management system or a flow sequence controller. Each is highly productive in specific parts of a design process, but becomes cumbersome in others. A design management approach which is generally applicable throughout the development of a product is presented. It offers flow control and automation to manage readily definable processes, while also being able to ensure data consistency where the task sequence is determined on-the-fly and a process flow cannot be predefined. The capability is part of the Texas Instruments Flagship Design System and is implemented using Falcon Framework technology.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127111165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246181
David B. Bernstein, Rodney Farrow, David Charness
VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing their use.<>
{"title":"Challenges in the analysis of VHDL","authors":"David B. Bernstein, Rodney Farrow, David Charness","doi":"10.1109/EURDAC.1992.246181","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246181","url":null,"abstract":"VHSIC hardware description language (VHDL) is a rich and complex formal language. Its many constructs allow for a wide description of hardware behavior. Many of the features, however, require semantics which are often difficult or expensive to properly analyze. The authors discuss several of these features, explaining why they exist, why they are hard to implement, and some strategies for easing their use.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121222924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-11-01DOI: 10.1109/EURDAC.1992.246273
Yogesh Mishra, S. Sherlekar, G. Venkatesh
The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns's and A.J. Martin's (1988) method.<>
{"title":"Path Breaker: a tool for the optimal design of speed independent asynchronous controllers","authors":"Yogesh Mishra, S. Sherlekar, G. Venkatesh","doi":"10.1109/EURDAC.1992.246273","DOIUrl":"https://doi.org/10.1109/EURDAC.1992.246273","url":null,"abstract":"The authors present a methodology for synthesizing speed independent asynchronous circuits from high-level continuous sampling plan (CSP)-like specifications. Instead of employing syntax-directed translation followed by local optimizing transformations on the resulting netlist, this method uses global dataflow analysis to directly produce an optimal controller. The method is shown to produce substantially smaller circuits than S.M. Burns's and A.J. Martin's (1988) method.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115899144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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