Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf0.5Zr0.5O2 (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm2 at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.
{"title":"CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit","authors":"Keerthana Shajil Nair , Muhammad Hamid Raza , Catherine Dubourdieu , Veeresh Deshpande","doi":"10.1016/j.sse.2025.109255","DOIUrl":"10.1016/j.sse.2025.109255","url":null,"abstract":"<div><div>Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm<sup>2</sup> at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109255"},"PeriodicalIF":1.4,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1016/j.sse.2025.109247
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
In this work, different Y-function methodologies for the extraction of the electrical MOSFET parameters permitting to model the current–voltage (I–V) transfer characteristics from weak to strong inversion in ohmic mode of operation are compared on ideal I–V characteristics analytically constructed. It is evidenced that even if important discrepancies between the values of the estimated parameters using these methodologies exist, the access resistances value may be predicted with good accuracy. It is demonstrated that if the inversion charge is calculated by combining its asymptotic laws in weak and in strong inversion, this approximation will lead to an about 20% model-induced error in the moderate inversion range.
It is proved that the Y-function strategy which permits the best agreement between the extracted parameter values and the reference ones may be a solution to foresee with lower error the inversion charge behavior from weak to strong inversion even without performing capacitance–voltage measurements.
{"title":"Model and parameter extraction strategy impact on the estimated values of MOSFET parameters in ohmic operation","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109247","DOIUrl":"10.1016/j.sse.2025.109247","url":null,"abstract":"<div><div>In this work, different Y-function methodologies for the extraction of the electrical MOSFET parameters permitting to model the current–voltage (I–V) transfer characteristics from weak to strong inversion in ohmic mode of operation are compared on ideal I–V characteristics analytically constructed. It is evidenced that even if important discrepancies between the values of the estimated parameters using these methodologies exist, the access resistances value may be predicted with good accuracy. It is demonstrated that if the inversion charge is calculated by combining its asymptotic laws in weak and in strong inversion, this approximation will lead to an about 20% model-induced error in the moderate inversion range.</div><div>It is proved that the Y-function strategy which permits the best agreement between the extracted parameter values and the reference ones may be a solution to foresee with lower error the inversion charge behavior from weak to strong inversion even without performing capacitance–voltage measurements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109247"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145327383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we investigate for the first time the variation of out-of-equilibrium body potential during the scan of the back-gate voltage in EZ-FET double-gate structures, built on silicon-on-insulator. This simplified MOSFET, with undoped source and drain is typically used for front and back interface characterization purposes. The out of equilibrium phenomenon, induced by the difficulty to inject instantaneously the carriers needed for the conducting layer creation, is influenced by the front-gate. Two different behaviors are observed, depending on the sign of the front-gate. TCAD simulations confirm the main experimental tendencies.
{"title":"Evidence of out-of-equilibrium body potential in undoped EZ-FET","authors":"Abbas Hamzeh , Maryline Bawedin , Nada Zerhouni Abdou , Miltiadis Alepidis , Pablo Acosta-Alba , Laurent Brunet , Irina Ionica","doi":"10.1016/j.sse.2025.109251","DOIUrl":"10.1016/j.sse.2025.109251","url":null,"abstract":"<div><div>In this paper, we investigate for the first time the variation of out-of-equilibrium body potential during the scan of the back-gate voltage in EZ-FET double-gate structures, built on silicon-on-insulator. This simplified MOSFET, with undoped source and drain is typically used for front and back interface characterization purposes. The out of equilibrium phenomenon, induced by the difficulty to inject instantaneously the carriers needed for the conducting layer creation, is influenced by the front-gate. Two different behaviors are observed, depending on the sign of the front-gate. TCAD simulations confirm the main experimental tendencies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109251"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145118393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1016/j.sse.2025.109250
Run-Song Dou , Jia-Min Li , Fan-Yu Liu , Hui-ping Zhu , Bo Li , Jiang-Jiang Li , Bao-Gang Sun , Yang Huang , Jing Wan , Yong Xu , Zheng-sheng Han , Sorin Cristoloveanu
In this research, we perform an in-depth analysis of the self-heating effect (SHE) and heat transfer characteristics of devices fabricated on silicon-on-insulator (SOI) and silicon-on-silicon carbide (SOS) substrates using technology computer-aided design (TCAD) numerical simulations. The results reveal that, under identical operating conditions, the maximum lattice temperature increase in SOI devices is approximately 3.9 times higher than that in SOS devices, highlighting the superior thermal management properties of SOS devices. When SHE is considered at a gate voltage of 1.8 V, the leakage current in SOS devices decreases by about 27 % compared to SOI devices, demonstrating enhanced resistance to SHE in SOS devices. Analysis of the thermal dissipation pathways reveals that for SOI devices, heat primarily dissipates through the source and drain regions within the device layer, while for SOS devices it predominantly dissipates through the silicon carbide substrate due to its high thermal conductivity, thereby significantly improving thermal dissipation efficiency. Additionally, our research uncovers a correlation between increasing device layer thickness and elevated lattice temperature for both SOI and SOS structures. This phenomenon is closely associated with thermal-electric coupling effects and changes in device thermal resistance.
{"title":"Comparison of Self-Heating effect between SOI and SOS MOSFETs","authors":"Run-Song Dou , Jia-Min Li , Fan-Yu Liu , Hui-ping Zhu , Bo Li , Jiang-Jiang Li , Bao-Gang Sun , Yang Huang , Jing Wan , Yong Xu , Zheng-sheng Han , Sorin Cristoloveanu","doi":"10.1016/j.sse.2025.109250","DOIUrl":"10.1016/j.sse.2025.109250","url":null,"abstract":"<div><div>In this research, we perform an in-depth analysis of the self-heating effect (SHE) and heat transfer characteristics of devices fabricated on silicon-on-insulator (SOI) and silicon-on-silicon carbide (SOS) substrates using technology computer-aided design (TCAD) numerical simulations. The results reveal that, under identical operating conditions, the maximum lattice temperature increase in SOI devices is approximately 3.9 times higher than that in SOS devices, highlighting the superior thermal management properties of SOS devices. When SHE is considered at a gate voltage of 1.8 V, the leakage current in SOS devices decreases by about 27 % compared to SOI devices, demonstrating enhanced resistance to SHE in SOS devices. Analysis of the thermal dissipation pathways reveals that for SOI devices, heat primarily dissipates through the source and drain regions within the device layer, while for SOS devices it predominantly dissipates through the silicon carbide substrate due to its high thermal conductivity, thereby significantly improving thermal dissipation efficiency. Additionally, our research uncovers a correlation between increasing device layer thickness and elevated lattice temperature for both SOI and SOS structures. This phenomenon is closely associated with thermal-electric coupling effects and changes in device thermal resistance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109250"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145096281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1016/j.sse.2025.109245
Toshiyuki Oishi , Ken Kudara , Yutaro Yamaguchi , Shintaro Shinjo , Koji Yamanaka , Saga University , Mitsubishi Electric Corporation
The drain bias dependence of low-frequency Y-parameters under on-state conditions in Gallium Nitride high electron mobility transistors (GaN HEMTs) is investigated using experimental results and device simulation. The Y-parameters for broadband frequencies from 10 Hz to 100 MHz were systematically measured using a vector network analyzer for drain voltage from 3 to 30 V at the gate voltage of 0 V from room temperature to 120 degrees Celsius. Six signals with the peaks were observed in the imaginary parts (Im) of Y22 and Y21. These peaks were categorized into two groups. One is that the peaks appeared around 5 MHz and have negative slopes in Arrhenius plots. Another is that the peaks appeared below 150 kHz and have an activation energy that can be estimated from Arrhenius plots. The second group was further divided into peaks appeared in both Im(Y22) and Im(Y21), and those that appeared only in Im(Y21). The device simulation including self-heating effects was performed using the trap parameters estimated from the experimental results. Both DC and Y-parameter characteristics for the simulation have good agreement with the experimental results. By the simulation for the individual effects, the peaks around 5 MHz result from the heat generation in GaN HEMTs. The peaks below 150 kHz are considered to originate from the traps in AlGaN and GaN layers. The traps in the GaN layer generate the peaks in both Im(Y22) and Im(Y21), while the traps in the AlGaN layer generate peaks in only Im(Y21).
{"title":"Study on drain bias dependence of Y-parameters under on-state condition in GaN HEMTs using low-frequency vector network analyzer and device simulation","authors":"Toshiyuki Oishi , Ken Kudara , Yutaro Yamaguchi , Shintaro Shinjo , Koji Yamanaka , Saga University , Mitsubishi Electric Corporation","doi":"10.1016/j.sse.2025.109245","DOIUrl":"10.1016/j.sse.2025.109245","url":null,"abstract":"<div><div>The drain bias dependence of low-frequency Y-parameters under on-state conditions in Gallium Nitride high electron mobility transistors (GaN HEMTs) is investigated using experimental results and device simulation. The Y-parameters for broadband frequencies from 10 Hz to 100 MHz were systematically measured using a vector network analyzer for drain voltage from 3 to 30 V at the gate voltage of 0 V from room temperature to 120 degrees Celsius. Six signals with the peaks were observed in the imaginary parts (Im) of Y<sub>22</sub> and Y<sub>21</sub>. These peaks were categorized into two groups. One is that the peaks appeared around 5 MHz and have negative slopes in Arrhenius plots. Another is that the peaks appeared below 150 kHz and have an activation energy that can be estimated from Arrhenius plots. The second group was further divided into peaks appeared in both Im(Y<sub>22</sub>) and Im(Y<sub>21</sub>), and those that appeared only in Im(Y<sub>21</sub>). The device simulation including self-heating effects was performed using the trap parameters estimated from the experimental results. Both DC and Y-parameter characteristics for the simulation have good agreement with the experimental results. By the simulation for the individual effects, the peaks around 5 MHz result from the heat generation in GaN HEMTs. The peaks below 150 kHz are considered to originate from the traps in AlGaN and GaN layers. The traps in the GaN layer generate the peaks in both Im(Y<sub>22</sub>) and Im(Y<sub>21</sub>), while the traps in the AlGaN layer generate peaks in only Im(Y<sub>21</sub>).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109245"},"PeriodicalIF":1.4,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145096282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1016/j.sse.2025.109249
Nargis Khatun , Sumona Sinha , A.K.M. Maidul Islam
This study investigates the influence of Indium Tin Oxide (ITO) electrode surface modification on the electrical properties of zinc phthalocyanine (ZnPc)– based Schottky diodes, using amorphous polymers, specifically polystyrene (Ps) and poly(butyl methacrylate) (PBMA). Devices with configurations of Al (Aluminum)/ZnPc/ITO, Al/ZnPc/Ps/ITO, and Al/ZnPc/PBMA/ITO were fabricated and analysed through current–voltage (I-V) characterisation. Devices modified with polymers showed significantly improved electrical performance, with the rectification ratio rising from 0.81 (pure ZnPc) to 4.24 for ITO modified with PBMA and 6.32 for ITO modified with Ps, along with optimised ideality factors and reduced series resistance. Space-charge-limited conduction (SCLC) became dominant, indicating enhanced charge mobility in the modified devices. UV–Vis analysis further confirmed this improvement, showing that PBMA modification enhances π–π* interactions and molecular aggregation within ZnPc thin films, reducing the optical bandgap from 3.05 eV to 2.75 eV (Ps) and 2.68 eV (PBMA), which indicates modified electronic properties due to polymer incorporation. Structural investigations employing XRR and AFM complement these findings, demonstrating improved crystallite size and a smoother surface, which lead to better charge transport. These results highlight the efficiency of polymer surface modification in enhancing ZnPc-based Schottky diodes, presenting intriguing possibilities for future optoelectronic applications.
本研究研究了铟锡氧化物（ITO）电极表面改性对酞菁锌（ZnPc）基肖特基二极管电性能的影响，采用非晶态聚合物，特别是聚苯乙烯（Ps）和聚甲基丙烯酸丁酯（PBMA）。制备了具有Al (Aluminum)/ZnPc/ITO、Al/ZnPc/Ps/ITO和Al/ZnPc/PBMA/ITO结构的器件，并通过电流-电压（I-V）表征对其进行了分析。用聚合物修饰的器件表现出显著改善的电性能，整流比从0.81（纯ZnPc）上升到PBMA修饰的ITO的4.24和Ps修饰的ITO的6.32，同时优化了理想因子和降低了串联电阻。空间电荷限制传导（SCLC）成为主导，表明改进后的器件中电荷迁移率增强。UV-Vis分析进一步证实了这一改进，表明PBMA修饰增强了ZnPc薄膜内π -π *相互作用和分子聚集，将光学带隙从3.05 eV减小到2.75 eV （Ps）和2.68 eV (PBMA)，这表明聚合物掺入修饰了电子性能。利用XRR和AFM的结构研究补充了这些发现，证明了改进的晶体尺寸和更光滑的表面，导致更好的电荷传输。这些结果突出了聚合物表面改性在增强znpc基肖特基二极管方面的效率，为未来光电应用提供了有趣的可能性。
{"title":"ZnPc-based schottky diodes: Effect of amorphous polymer interlayers on electrical and structural properties","authors":"Nargis Khatun , Sumona Sinha , A.K.M. Maidul Islam","doi":"10.1016/j.sse.2025.109249","DOIUrl":"10.1016/j.sse.2025.109249","url":null,"abstract":"<div><div>This study investigates the influence of Indium Tin Oxide (ITO) electrode surface modification on the electrical properties of zinc phthalocyanine (ZnPc)– based Schottky diodes, using amorphous polymers, specifically polystyrene (Ps) and poly(butyl methacrylate) (PBMA). Devices with configurations of Al (Aluminum)/ZnPc/ITO, Al/ZnPc/Ps/ITO, and Al/ZnPc/PBMA/ITO were fabricated and analysed through current–voltage (I-V) characterisation. Devices modified with polymers showed significantly improved electrical performance, with the rectification ratio rising from 0.81 (pure ZnPc) to 4.24 for ITO modified with PBMA and 6.32 for ITO modified with Ps, along with optimised ideality factors and reduced series resistance. Space-charge-limited conduction (SCLC) became dominant, indicating enhanced charge mobility in the modified devices. UV–Vis analysis further confirmed this improvement, showing that PBMA modification enhances π–π* interactions and molecular aggregation within ZnPc thin films, reducing the optical bandgap from 3.05 eV to 2.75 eV (Ps) and 2.68 eV (PBMA), which indicates modified electronic properties due to polymer incorporation. Structural investigations employing XRR and AFM complement these findings, demonstrating improved crystallite size and a smoother surface, which lead to better charge transport. These results highlight the efficiency of polymer surface modification in enhancing ZnPc-based Schottky diodes, presenting intriguing possibilities for future optoelectronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109249"},"PeriodicalIF":1.4,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145109137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1016/j.sse.2025.109246
Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee
We investigate the effects of plasma on SiO2 surfaces in various plasma environments, including Ar, O2, and N2, under identical plasma conditions for low-temperature annealing in SiO2/SiO2 wafer bonding. After plasma treatments, no damage is observed on the SiO2 surface, which is comparable to post-CMP SiO2. With the Ar and O2 plasma treatments and XPS analysis, the SiO2 surface shows a Si-OH-rich surface and changes to more hydrophilic properties. Although N2 plasma treatment results in a few isolated voids being observed compared to O2 plasma treatment, N2 plasma treatment will be a suitable choice for Cu/SiO2 hybrid bonding thanks to its highest bonding strength compared to other plasma treatments and the ability to avoid Cu oxidation. On the other hand, O2 plasma treatment on SiO2 surface is the most effective way for SiO2/SiO2 wafer bonding providing excellent hydrophilicity, strong bonding strength, and minimal bonding voids.
{"title":"Comparative effects of plasma treatments on SiO2 surface and bonding performance for wafer and hybrid bonding","authors":"Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee","doi":"10.1016/j.sse.2025.109246","DOIUrl":"10.1016/j.sse.2025.109246","url":null,"abstract":"<div><div>We investigate the effects of plasma on SiO<sub>2</sub> surfaces in various plasma environments, including Ar, O<sub>2</sub>, and N<sub>2</sub>, under identical plasma conditions for low-temperature annealing in SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding. After plasma treatments, no damage is observed on the SiO<sub>2</sub> surface, which is comparable to post-CMP SiO<sub>2</sub>. With the Ar and O<sub>2</sub> plasma treatments and XPS analysis, the SiO<sub>2</sub> surface shows a Si-OH-rich surface and changes to more hydrophilic properties. Although N<sub>2</sub> plasma treatment results in a few isolated voids being observed compared to O<sub>2</sub> plasma treatment, N<sub>2</sub> plasma treatment will be a suitable choice for Cu/SiO<sub>2</sub> hybrid bonding thanks to its highest bonding strength compared to other plasma treatments and the ability to avoid Cu oxidation. On the other hand, O<sub>2</sub> plasma treatment on SiO<sub>2</sub> surface is the most effective way for SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding providing excellent hydrophilicity, strong bonding strength, and minimal bonding voids.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109246"},"PeriodicalIF":1.4,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-12DOI: 10.1016/j.sse.2025.109248
Ruixue Mai , Xiaoli Tian , Xinyu Liu , Xinhua Wang , Yun Bai , Wei Wei , Yuhao Guo , Chengyue Yang , Chengzhan Li , Yidan Tang
A novel multizone floating field ring (M−FFR) edge termination structure with individually increasing ring spacing has been proposed, fabricated, and measured for 4H-silicon carbide (4H-SiC) p-channel insulated gate bipolar transistors (IGBTs). This M−FFR design effectively suppresses electric field crowding at the termination edge while maintaining a high tolerance to oxide charge accumulation. Numerical simulations indicate that the M−FFR achieves a 17.4 % higher blocking voltage compared to conventional equidistant floating field ring (Con-FFR) designs. Importantly, the proposed structure requires no complex fabrication steps or additional lithography processes, reducing manufacturing cost and complexity. To further enhance device performance, carrier lifetime enhancement techniques were applied to reduce the on-state voltage drop (Vf). Experimental measurements confirm that the fabricated p-channel SiC IGBTs are capable of sustaining blocking voltages exceeding 10 kV with leakage currents below 300nA. At a gate voltage of −20 V, a Vf of 5.77 V and a low differential specific on-resistance (Ron,sp,diff) of 17.5 mΩ·cm2 were achieved. These results suggest that the device is promising for applications in high-power electronic devices.
{"title":"High blocking voltage and low on-state voltage drop 4H-SiC p-channel IGBTs with optimized multizone floating field rings","authors":"Ruixue Mai , Xiaoli Tian , Xinyu Liu , Xinhua Wang , Yun Bai , Wei Wei , Yuhao Guo , Chengyue Yang , Chengzhan Li , Yidan Tang","doi":"10.1016/j.sse.2025.109248","DOIUrl":"10.1016/j.sse.2025.109248","url":null,"abstract":"<div><div>A novel multizone floating field ring (M−FFR) edge termination structure with individually increasing ring spacing has been proposed, fabricated, and measured for 4H-silicon carbide (4H-SiC) p-channel insulated gate bipolar transistors (IGBTs). This M−FFR design effectively suppresses electric field crowding at the termination edge while maintaining a high tolerance to oxide charge accumulation. Numerical simulations indicate that the M−FFR achieves a 17.4 % higher blocking voltage compared to conventional equidistant floating field ring (Con-FFR) designs. Importantly, the proposed structure requires no complex fabrication steps or additional lithography processes, reducing manufacturing cost and complexity. To further enhance device performance, carrier lifetime enhancement techniques were applied to reduce the on-state voltage drop (<em>V</em><sub>f</sub>). Experimental measurements confirm that the fabricated p-channel SiC IGBTs are capable of sustaining blocking voltages exceeding 10 kV with leakage currents below 300nA. At a gate voltage of −20 V, a <em>V</em><sub>f</sub> of 5.77 V and a low differential specific on-resistance (<em>R</em><sub>on,sp,diff</sub>) of 17.5 mΩ·cm<sup>2</sup> were achieved. These results suggest that the device is promising for applications in high-power electronic devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109248"},"PeriodicalIF":1.4,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-12DOI: 10.1016/j.sse.2025.109229
Lisa Tondelli , Andries J. Scholten , Thanh Viet Dinh , Luca Selmi
FinFET technology is widely used for advanced digital, RF, and analog applications due to its high performance and scalability. However, the non-planar architecture introduces increased electrical parasitics and self-heating effects (SHEs), which can degrade device reliability and performance.
We analyze, by simulation, the thermal behavior of four FinFET layouts designed with realistic process rules, focusing on transistor channels at the boundary of the large FinFET arrays required by RF applications. The findings highlight key thermal trade-offs of FinFET structures and suggest ways to balance static and dynamic self-heating for optimum performance and limited overtemperature.
{"title":"Layout effects on the thermal metrics of multichannel FinFETs","authors":"Lisa Tondelli , Andries J. Scholten , Thanh Viet Dinh , Luca Selmi","doi":"10.1016/j.sse.2025.109229","DOIUrl":"10.1016/j.sse.2025.109229","url":null,"abstract":"<div><div>FinFET technology is widely used for advanced digital, RF, and analog applications due to its high performance and scalability. However, the non-planar architecture introduces increased electrical parasitics and self-heating effects (SHEs), which can degrade device reliability and performance.</div><div>We analyze, by simulation, the thermal behavior of four FinFET layouts designed with realistic process rules, focusing on transistor channels at the boundary of the large FinFET arrays required by RF applications. The findings highlight key thermal trade-offs of FinFET structures and suggest ways to balance static and dynamic self-heating for optimum performance and limited overtemperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109229"},"PeriodicalIF":1.4,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145057261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-10DOI: 10.1016/j.sse.2025.109240
K. Blanco , F. Mazen , T. Salvetat , D. Landru , F. Rieutord
The layer transfer of InP with the Smart Cut™ technology shows an original behavior, with the existence of a transition temperature, above which fracture occurs rapidly and below which it never spontaneously happens. Using microcracks observation and measurement of the amount of H2 inside cracks, we show that the existence of the two regimes is due to a competition between a trapping of implanted hydrogen inside the cracks and its out-diffusion into the bonded structure.
{"title":"An understanding of fracture kinetics during the layer transfer of InP","authors":"K. Blanco , F. Mazen , T. Salvetat , D. Landru , F. Rieutord","doi":"10.1016/j.sse.2025.109240","DOIUrl":"10.1016/j.sse.2025.109240","url":null,"abstract":"<div><div>The layer transfer of InP with the Smart Cut™ technology shows an original behavior, with the existence of a transition temperature, above which fracture occurs rapidly and below which it never spontaneously happens. Using microcracks observation and measurement of the amount of H<sub>2</sub> inside cracks, we show that the existence of the two regimes is due to a competition between a trapping of implanted hydrogen inside the cracks and its out-diffusion into the bonded structure.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109240"},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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