Solid-state Electronics最新文献

In this study, a neural network (NN) was proposed for predicting the V_T characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The V_T distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate V_T distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the V_T distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the V_T distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects.

Despite the significant potential of ferroelectric devices in overcoming the challenges faced by conventional high-k-based CMOS devices owing to the scaling of CMOS processes, most ferroelectric devices are not implemented in practical circuits yet. For practical application, integrating them into a circuit is essential, and the development of a reliable etching process is crucial for the integration of individual devices into circuits. Therefore, this study proposes a process for etching hafnium zirconium oxide (HZO)-based gate stacks to fabricate a gate structure and integrate HZO-based devices into circuits. First, poly-Si/TiN/HZO/TiN/SiO₂ was deposited on a Si substrate and etched via Cl₂ and BCl₃/Cl₂ plasma etchings. Cl₂ plasma etching was found to be less effective, whereas BCl₃/Cl₂ plasma etching exhibited a higher etching rate. The optimal etching time for the BCl₃/Cl₂ plasma at which the entire stack was successfully removed was 50 s. Furthermore, the optimal ratio of Ar:Cl₂:BCl₃ that resulted in minimal damage to the Si surface was determined to be 1:1:3. These results led to the successful formation of an HZO-based gate structure and provided the potential to integrate ferroelectric devices into the circuit, thereby enabling their practical utilization.

The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.

In the process of mass-production of semiconductors, it has been continuously required to determine whether the process is normal or not, and for this, it must be premised that the measurement equipment can produce reliable and consistent measurement data. However, Due to the denaturation of Working Reference Material (WRM), which is the basis for judging the accuracy and precision of the equipment, it is difficult to maintain the consistency of the instrument. In this study, the effect of preventing WRM denaturation was analyzed through optical path control in Spectroscopic Ellipsometry (SE) equipment. Therefore, by applying it to actual equipment, It is suggested methods to improve measurement equipment reliability.

This paper proposes an experimental package type with a new structure and material that can evaluate the HBM reliability accurately by overcoming the limitations of the previous proxy package. This is based on the revision to the package type that reflects the actual user environment which was not applied in the previous type. First, side and top EMC were eliminated to enhance the consistency with SIP and the proxy package. Secondly, the Si interposer which is used to connect HBM to PCB was altered from wire bonding to TSV structure. Lastly, NCF is changed to Underfill between HBM and the Si Interposer to create an environment identical to that of SIP. Through using this new package type, the failure rate by temperature cycling during 1000 cycles in HBM2E showed 0% from the previous 13%, and that during 2000 cycles in HBM3 showed 0%, and as a result, the HBM memories are well in volume production.

We introduce an innovative approach that incorporates operator-based spike detection in wireless microsystems for neural signal processing. Through comparative analyses between simple thresholding and operator-based detection conducted on pre-recorded spike detection experiments, our research emphasizes the superiority of the operator-based spike detection approach. The operator-based spike detection emerges as a promising technique for miniaturized wireless neural signal devices, primarily due to its proficient noise-handling capabilities paired with reduced power consumption. Furthermore, its adaptability across various experimental conditions amplifies its versatility. Empirical tests underscored its low power requisites and compactness, emphasizing practical utility of the detection scheme in the neural microsystems. Collectively, our results mark a significant progression in wireless cerebral signal recording methodologies, paving the way for optimized wireless brain-machine interface (BMI) systems.

For a profound understanding of brain function and connectivity, there is an escalating need to cover expansive cortical areas. While external recording methods such as electroencephalography (EEG) are prevalent, direct bidirectional interaction with the neural network mandates implanted electrodes. Integrating all microimplant functionalities into a single integrated circuit (IC) increases design complexities. Thus, challenges in the intricacies of distributed system networking have frustrated the drive toward implant miniaturization. In this context, we introduce addressable microimplants equipped with gate oxide-based anti-fuse (AF) Chip-IDs activated by a photodiode (PD) array. This mechanism generates a binary ID code by selectively degrading the anti-fuse gate oxide, eliminating the need for I/O PADs. These ID-equipped wireless micro-implants are distributed over vast regions, enabling bidirectional neural interfacing through recording and stimulation. We successfully fabricated an 8-channel wireless microstimulator and a spike-sensor in 180 nm CMOS, demonstrating the efficacy of the 5-bit Chip-ID in real-time networking scenarios. The system draws power from RF electromagnetic waves, receiving 1.2 V and 1 mW, and employs amplitude modulation at a 900 MHz carrier frequency for data communication. The minimum amplitude detected for demodulation was 350 mV, regenerating a 1 MHz clock and 34-bit command data. When tested, the array of eight microstimulators responded distinctly based on sequential command parameters. This IC realized in TSMC 180 nm CMOS technology, occupies only a 1 mm² area.

Organic thin-film transistors (OTFTs) fabricated on Parylene-C substrates have the advantages of a simple process, low cost, and flexible characteristics. This study introduces the manufacturing method and electrical characteristics of an OTFT using organic materials as the substrate, gate dielectric, and channel material. PDPP2T-TT-OD(DPP-DTT) is used as the channel material, which is a highly mobile p-type polymer with good air stability. The proposed OTFT device has flexible characteristics because it is fabricated on a Parylene-C substrate and can be used even in a curved state. Furthermore, the manufacturing process was largely achieved via a simple, low-cost solution process using spin-coating and photolithography with a photo-curable material. Under flat conditions, the threshold voltage (V_TH) is approximately –3 V, the average I_ON/I_OFF ratio is approximately 10⁵, and the mobility is 0.84 cm²/Vs.

The transmission line method (TLM) is modified to analyze the contact resistance between the metal and zinc oxide semiconductor considering interface resistance. TCAD is used to simulate an ideal defect-less state and compare it with experimental result. It is found that the current transfer length can be overestimated in conventional TLM measurement. The importance of interface resistance is shown through interface trap and Schottky contact effect analysis: Resistance comparison between different metal used device, and the activation energy shift measurement after O₂ pre-annealing. Based on these, the conventional resistance equation for TLM is corrected by separating channel resistance and non-ideal contact resistance. The mobility and temperature coefficient of resistance (TCR) of ZnO channel are extracted using the suggested method. This shows the importance of metal/semiconductor interface resistance in devices using semiconductor channel.

In this work, we investigate the feasibility of cleaved-gate ferroelectric FET (CG-FeFET) as multi-level cell (MLC) memory devices, by conducting 3-dimensional quantum transport simulations based on time-dependent-Ginzburg–Landau equation, and the non-equilibrium Green’s function method. Our results indicate that CG-FeFET can achieve multi-level operations by utilizing different thicknesses of the ferroelectric layer. We analyze the influence of electron–phonon interaction and also verify that CG-FeFET is robust to noise. Furthermore, we identify the critical role of the spacing between two ferroelectric layers in determining the memory window, considering the effects of polarization cancellation and electrostatic coupling. These findings provide valuable insights into designing stable and reliable nonvolatile memory technologies, which could offer potential solutions for high-density memory requirements.