We explored the effects of gate work function variation (WFV) through device simulation on a fin-shaped silicon quantum dot device with a multi-gate configuration for a large-scale integrated array. The threshold voltage (Vth) of current–voltage characteristics is affected by WFV in both main and surrounding gates, indicating the existence of electrostatic coupling among these gates. The electrostatic coupling can be reduced by biasing on the surrounding gates. Furthermore, the concept of Vth, following conventional transistors, works as a reference of voltage and potential in the present multi-gate device. This knowledge contributes to establishing a practical method for the statistical analysis of qubit variability.
{"title":"Influence of gate work function variations on characteristics of fin-shaped silicon quantum dot device with multi-gate under existence of gate electrostatic coupling","authors":"Kimihiko Kato, Hidehiro Asai, Hiroshi Oka, Shota Iizuka, Hiroshi Fuketa, Takumi Inaba, Takahiro Mori","doi":"10.1016/j.sse.2024.109013","DOIUrl":"10.1016/j.sse.2024.109013","url":null,"abstract":"<div><div>We explored the effects of gate work function variation (WFV) through device simulation on a fin-shaped silicon quantum dot device with a multi-gate configuration for a large-scale integrated array. The threshold voltage (<em>V</em><sub>th</sub>) of current–voltage characteristics is affected by WFV in both main and surrounding gates, indicating the existence of electrostatic coupling among these gates. The electrostatic coupling can be reduced by biasing on the surrounding gates. Furthermore, the concept of <em>V</em><sub>th</sub>, following conventional transistors, works as a reference of voltage and potential in the present multi-gate device. This knowledge contributes to establishing a practical method for the statistical analysis of qubit variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109013"},"PeriodicalIF":1.4,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142533072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1016/j.sse.2024.109014
Zachary C. Adamson , Rotem Zilberberg , Iryna Polishchuk , Natalia Thomas , Kyumin Kim , Alexander Katsman , Boaz Pokroy , Alexander Zaslavsky , David C. Paine
This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO2 gate dielectric layer, and Al2O3 passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by VG = 4 V, with a field-effect channel hole mobility μh ∼ 1.5–2 cm2 V−1 s−1. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final Ion/Ioff current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al2O3 passivation, and HfO2. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.
{"title":"Sputter-Deposited copper iodide thin film transistors with low Operating voltage","authors":"Zachary C. Adamson , Rotem Zilberberg , Iryna Polishchuk , Natalia Thomas , Kyumin Kim , Alexander Katsman , Boaz Pokroy , Alexander Zaslavsky , David C. Paine","doi":"10.1016/j.sse.2024.109014","DOIUrl":"10.1016/j.sse.2024.109014","url":null,"abstract":"<div><div>This paper reports on a back-gated p-type thin film transistor (TFT) with copper iodide (CuI) as the channel material, a HfO<sub>2</sub> gate dielectric layer, and Al<sub>2</sub>O<sub>3</sub> passivation. The γ-CuI channel was deposited from a CuI target using DC magnetron sputtering at room temperature. Our TFT can be fully shut off by V<sub>G</sub> = 4 V, with a field-effect channel hole mobility μ<sub>h</sub> ∼ 1.5–2 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>. An anneal in forming gas was performed twice, once at 200 °C, then at 250 °C to improve gate control, yielding a final I<sub>on</sub>/I<sub>off</sub> current ratio of ∼ 250. The anneal served two purposes: to reduce the oxygen acceptor density in the CuI channel and reduce the concentration of interface states between the CuI, Al<sub>2</sub>O<sub>3</sub> passivation, and HfO<sub>2</sub>. A model of the device was built in an industrial TCAD simulator, which reproduces the measured characteristics and allows an estimation of interface state densities and channel doping.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109014"},"PeriodicalIF":1.4,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-15DOI: 10.1016/j.sse.2024.109011
Tao He , Huiyu Yan , Yixuan Wang
Set voltage is a key parameter for the application of Resistance Random Access Memory (RRAM). In this paper, based on TiN/AlOx/Pt RRAM synthesized by the magnetron sputtering method, we have studied the influence of I-V cycling at high temperatures on resistive switching performance. The results show that the treatment can significantly reduce the set voltage in resistive switching cycles. Moreover, the treatment can also enhance endurance effectively. Further studies indicated that a higher compliance current in treatment can induce a smaller and more uniform set voltage. We ascribe the improvements in resistive switching performance to the generation and accumulation of oxygen vacancies in the treatment. This research provides new ideas for synthesizing RRAM devices with low power consumption.
{"title":"Enhanced resistive switching performance in TiN/AlOx/Pt RRAM by high-temperature I-V cycling","authors":"Tao He , Huiyu Yan , Yixuan Wang","doi":"10.1016/j.sse.2024.109011","DOIUrl":"10.1016/j.sse.2024.109011","url":null,"abstract":"<div><div>Set voltage is a key parameter for the application of Resistance Random Access Memory (RRAM). In this paper, based on TiN/AlO<em><sub>x</sub></em>/Pt RRAM synthesized by the magnetron sputtering method, we have studied the influence of <em>I</em>-<em>V</em> cycling at high temperatures on resistive switching performance. The results show that the treatment can significantly reduce the set voltage in resistive switching cycles. Moreover, the treatment can also enhance endurance effectively. Further studies indicated that a higher compliance current in treatment can induce a smaller and more uniform set voltage. We ascribe the improvements in resistive switching performance to the generation and accumulation of oxygen vacancies in the treatment. This research provides new ideas for synthesizing RRAM devices with low power consumption.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109011"},"PeriodicalIF":1.4,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-10DOI: 10.1016/j.sse.2024.109010
Thomas Bédécarrats, Sébastien Martinie, Adrien Vaysset, Olivier Rozeau
This paper provides an improved surface potential equation for compact modeling of dynamically depleted silicon-on-insulator MOS device. It removes the non-physical front-gate capacitance prediction and the discontinuity at the flat-band condition present in previous works. It also includes for the first time the back gate effect observed at negative back gate voltage when the silicon film is partially depleted. It relies on, firstly, an approximated description of the front-depletion/back-accumulation mode of operation that has always been ignored by now, and secondly, an appropriate mathematical conditioning. The model is validated by 3D TCAD simulations.
本文为动态耗尽型硅绝缘体 MOS 器件的紧凑建模提供了一种改进的表面电势方程。它消除了之前工作中存在的非物理前栅极电容预测和平带条件下的不连续性。它还首次包含了硅薄膜部分耗尽时在负后栅电压下观察到的后栅效应。首先，它依赖于对迄今为止一直被忽视的前耗尽/后累积工作模式的近似描述；其次，它依赖于适当的数学条件。三维 TCAD 仿真验证了该模型。
{"title":"A well-conditioned surface potential equation for dynamically depleted SOI MOS devices accounting for the front-depletion/back-accumulation operation mode","authors":"Thomas Bédécarrats, Sébastien Martinie, Adrien Vaysset, Olivier Rozeau","doi":"10.1016/j.sse.2024.109010","DOIUrl":"10.1016/j.sse.2024.109010","url":null,"abstract":"<div><div>This paper provides an improved surface potential equation for compact modeling of dynamically depleted silicon-on-insulator MOS device. It removes the non-physical front-gate capacitance prediction and the discontinuity at the flat-band condition present in previous works. It also includes for the first time the back gate effect observed at negative back gate voltage when the silicon film is partially depleted. It relies on, firstly, an approximated description of the front-depletion/back-accumulation mode of operation that has always been ignored by now, and secondly, an appropriate mathematical conditioning. The model is validated by 3D TCAD simulations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109010"},"PeriodicalIF":1.4,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-04DOI: 10.1016/j.sse.2024.109009
Wei-Qi Huang , Yin-lian Li , Zhong-Mei Huang , Hao-Ze Wang , Xi Zhang , Qi-Bin Liu , Shi-Rong Liu
Emission efficiency of bulk-silicon is very low due to its indirect-gap of energy band. However, it is interesting that the enhanced emission has been observed in the micro-cavities array fabricated by using femtosecond (fs) pulsed laser, in which the stimulated emission characteristics occur after annealing for suitable time in the photo-luminescence (PL) measurement at room temperature. The results of experiment and calculation demonstrated that the enhanced emission may be originated from the Si quantum dots embedded in the micro-cavities prepared by fs pulsed laser. Here, the direct-gap of energy band appears after annealing due to the Heisenberg principle related to ⊿k–1/⊿x in quantum system of nanostructures. The PL intensity obviously increases on the Si quantum dots growing with annealing for better crystallization, in which the external quantum efficiency is higher than 40 % near 760 nm. A new kind of emission source of the micro-cavities array in visible wavelength has been built on silicon wafer, in which the Si quantum dots play a main role for enhancement of emission. It should have a good application in optical integrated chip based on silicon, such as emission cells built on Si chip.
{"title":"Emission cells with quantum dots on silicon chip prepared by using fs pulsed laser","authors":"Wei-Qi Huang , Yin-lian Li , Zhong-Mei Huang , Hao-Ze Wang , Xi Zhang , Qi-Bin Liu , Shi-Rong Liu","doi":"10.1016/j.sse.2024.109009","DOIUrl":"10.1016/j.sse.2024.109009","url":null,"abstract":"<div><div>Emission efficiency of bulk-silicon is very low due to its indirect-gap of energy band. However, it is interesting that the enhanced emission has been observed in the micro-cavities array fabricated by using femtosecond (fs) pulsed laser, in which the stimulated emission characteristics occur after annealing for suitable time in the photo-luminescence (PL) measurement at room temperature. The results of experiment and calculation demonstrated that the enhanced emission may be originated from the Si quantum dots embedded in the micro-cavities prepared by fs pulsed laser. Here, the direct-gap of energy band appears after annealing due to the Heisenberg principle related to ⊿k–1/⊿x in quantum system of nanostructures. The PL intensity obviously increases on the Si quantum dots growing with annealing for better crystallization, in which the external quantum efficiency is higher than 40 % near 760 nm. A new kind of emission source of the micro-cavities array in visible wavelength has been built on silicon wafer, in which the Si quantum dots play a main role for enhancement of emission. It should have a good application in optical integrated chip based on silicon, such as emission cells built on Si chip.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109009"},"PeriodicalIF":1.4,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-29DOI: 10.1016/j.sse.2024.109008
S.C. Lee
A nanophotonic approach to the signal-to-noise ratio (SNR) of an InAs-based quantum dot infrared photodetector (QDIP) with surface plasmonic excitation is reported. A 100 nm-thick Au film, perforated with a 3.1 μm-period, 2-dimensional square array of holes, referred to as a metal photonic crystal (MPC), is employed as a plasmonic coupler for it. Under the irradiance on the MPC integrated atop the QDIP, the fundamental surface plasma wave (SPW) is excited along their interface at ∼10.3 μm in wavelength. It carries the near-field that interacts with the quantum dots (QDs) under the interface. Depending on the presence of the coupler, the QDIP generates two different current–voltage (I-V) characteristics; one from the QDs normally working without MPC and the other from those coupled to the SPW near-field with it. The two I-V’s unfold the signal and noise current of each case with photoconductive gain. In their relation, generation-recombination and shot noises which are correlated with the detector signal current are directly affected by the plasmonic coupling but other sources including thermal noise are not relevant to it. Relying on these differences, the I-V analysis allows the SNR of each case and shows ∼20× enhancement by the plasmonic coupling. It reveals that most of the noise current is attributed to thermal fluctuations inherent to the quantum confinement of the QDIP. The SNR lower than the quantum efficiency in plasmonic enhancement is addressed.
{"title":"A nanophotonic approach to signal-to-noise ratio of quantum dot infrared photodetectors with surface plasmonic excitation","authors":"S.C. Lee","doi":"10.1016/j.sse.2024.109008","DOIUrl":"10.1016/j.sse.2024.109008","url":null,"abstract":"<div><div>A nanophotonic approach to the signal-to-noise ratio (SNR) of an InAs-based quantum dot infrared photodetector (QDIP) with surface plasmonic excitation is reported. A 100 nm-thick Au film, perforated with a 3.1 μm-period, 2-dimensional square array of holes, referred to as a metal photonic crystal (MPC), is employed as a plasmonic coupler for it. Under the irradiance on the MPC integrated atop the QDIP, the fundamental surface plasma wave (SPW) is excited along their interface at ∼10.3 μm in wavelength. It carries the near-field that interacts with the quantum dots (QDs) under the interface. Depending on the presence of the coupler, the QDIP generates two different current–voltage (I-V) characteristics; one from the QDs normally working without MPC and the other from those coupled to the SPW near-field with it. The two I-V’s unfold the signal and noise current of each case with photoconductive gain. In their relation, generation-recombination and shot noises which are correlated with the detector signal current are directly affected by the plasmonic coupling but other sources including thermal noise are not relevant to it. Relying on these differences, the I-V analysis allows the SNR of each case and shows ∼20× enhancement by the plasmonic coupling. It reveals that most of the noise current is attributed to thermal fluctuations inherent to the quantum confinement of the QDIP. The SNR lower than the quantum efficiency in plasmonic enhancement is addressed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109008"},"PeriodicalIF":1.4,"publicationDate":"2024-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142416685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-26DOI: 10.1016/j.sse.2024.109007
O.M. Grudanov , M.B. Grudanov
This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances , coupling capacitances (, including via-to-via capacitances , contact-to-gate capacitances , contact-to-active capacitances ( and fringe type capacitances with the top and bottom conductive layers.
{"title":"Smart-CX – Method of extraction of parasitic capacitances in ICs","authors":"O.M. Grudanov , M.B. Grudanov","doi":"10.1016/j.sse.2024.109007","DOIUrl":"10.1016/j.sse.2024.109007","url":null,"abstract":"<div><div>This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>a</mi><mo>)</mo></mrow></math></span>, coupling capacitances (<span><math><mrow><mi>C</mi><mi>c</mi><mo>)</mo></mrow></math></span>, including via-to-via capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>m</mi><mi>v</mi><mo>)</mo></mrow></math></span>, contact-to-gate capacitances <span><math><mrow><mo>(</mo><mi>C</mi><mi>m</mi><mi>g</mi><mo>)</mo></mrow></math></span>, contact-to-active capacitances <strong>(</strong><span><math><mrow><mi>C</mi><mi>m</mi><mi>c</mi><mo>)</mo></mrow></math></span> and fringe type capacitances with the top <span><math><mrow><mo>(</mo><mi>C</mi><mi>f</mi><mi>t</mi><mo>)</mo></mrow></math></span> and bottom <span><math><mrow><mo>(</mo><mi>C</mi><mi>f</mi><mi>b</mi><mo>)</mo></mrow></math></span> conductive layers.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109007"},"PeriodicalIF":1.4,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142437856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-19DOI: 10.1016/j.sse.2024.109006
Kaicaiayi Kelimu, Yiqun Zhang, Yangyang Zhu, Heping Su, Xi Lu, Li Juan Wang
Organic semiconductor gas sensors of α-hexathiophene (α-6 T) films as active layers with dual heterogeneous interface layers of p-hexabiphenyl and pentacene films are prepared by continuous vacuum evaporation method. The enhanced properties of sensors are achieved by modulating the thickness of the α-6 T films. The sensitivity of 1373 %/ ppm and a theoretical low detection limit of 361 ppb are obtained. The sensors demonstrate fast response and recovery properties of 1.05 and 1.51 min for NO2 gas of 20 ppm. The improved performance is attributed to the continuity of the interface layers and high adsorption of island-like growth. This approach is effective to improve organic sensors by introducing dual heterogeneous interface and tuning the growth of active layers.
{"title":"Enhanced response and recovery performance of α-hexathiophene sensors for NO2 gas by dual heterogeneous interface","authors":"Kaicaiayi Kelimu, Yiqun Zhang, Yangyang Zhu, Heping Su, Xi Lu, Li Juan Wang","doi":"10.1016/j.sse.2024.109006","DOIUrl":"10.1016/j.sse.2024.109006","url":null,"abstract":"<div><div>Organic semiconductor gas sensors of α-hexathiophene (α-6 T) films as active layers with dual heterogeneous interface layers of <em>p</em>-hexabiphenyl and pentacene films are prepared by continuous vacuum evaporation method. The enhanced properties of sensors are achieved by modulating the thickness of the α-6 T films. The sensitivity of 1373 %/ ppm and a theoretical low detection limit of 361 ppb are obtained. The sensors demonstrate fast response and recovery properties of 1.05 and 1.51 min for NO<sub>2</sub> gas of 20 ppm. The improved performance is attributed to the continuity of the interface layers and high adsorption of island-like growth. This approach is effective to improve organic sensors by introducing dual heterogeneous interface and tuning the growth of active layers.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109006"},"PeriodicalIF":1.4,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142328352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1016/j.sse.2024.109005
Guoxiang Song , Xinan Zhang , Haoxuan Xu
Doping is a useful technique for metal oxide thin-film transistors (TFTs) to adjust the threshold voltage and charge carrier density. However, a notable drawback is the disruption of the microstructure caused by doping crystalline lattice, leading to a partial decrease in charge carrier mobility. In this work, we suggest a surface doping technique that modifies the carrier concentration and passivates the device surface while preserving the channel layer lattice structure through the use of organic dopant molecules. It is shown that tin oxide (SnO2) TFTs doped in this manner typically exhibit improved electrical characteristics, particularly greater mobility and a noticeably lower threshold voltage, without negatively affecting the devices on/off current ratio. Furthermore, compared to pristine devices, bias stress stability and long-term durability are also enhanced. These findings suggest that surface doping may find use in high-performance oxide semiconductor devices and circuits.
{"title":"Carrier modulation and effective passivation of tin oxide thin-film transistors by organic surface doping","authors":"Guoxiang Song , Xinan Zhang , Haoxuan Xu","doi":"10.1016/j.sse.2024.109005","DOIUrl":"10.1016/j.sse.2024.109005","url":null,"abstract":"<div><p>Doping is a useful technique for metal oxide thin-film transistors (TFTs) to adjust the threshold voltage and charge carrier density. However, a notable drawback is the disruption of the microstructure caused by doping crystalline lattice, leading to a partial decrease in charge carrier mobility. In this work, we suggest a surface doping technique that modifies the carrier concentration and passivates the device surface while preserving the channel layer lattice structure through the use of organic dopant molecules. It is shown that tin oxide (SnO<sub>2</sub>) TFTs doped in this manner typically exhibit improved electrical characteristics, particularly greater mobility and a noticeably lower threshold voltage, without negatively affecting the devices on/off current ratio. Furthermore, compared to pristine devices, bias stress stability and long-term durability are also enhanced. These findings suggest that surface doping may find use in high-performance oxide semiconductor devices and circuits.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109005"},"PeriodicalIF":1.4,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142239541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1016/j.sse.2024.109004
Gehad Ali , Reem Mahmoud , Mohamed Wafeek , Moataz M.K. Yousef , Sameh O. Abdellatif
This study presents a comprehensive approach to fine-tuning Cesium Lead Chloride Perovskite Field-Effect Transistors (CsPbCl3-FETs) for sensing applications by bridging numerical modeling with experimental validation. By combining finite element methods in COMSOL Multiphysics for optimization, we tailored FET parameters such as oxide and perovskite thin film thickness. The fabricated FET, with a 200 nm semiconductor layer and 30 nm oxide thickness, was strategically chosen to operate in a non-depletion mode, maximizing mobility while minimizing power consumption. Experimental results closely aligned with numerical simulations, showcasing a threshold voltage of 0.50 V±0.07 V and an impressive on/off current ratio of 1.50 x 104 ± 0.3 x 104. Notably, the perovskite FET exhibited remarkable carrier mobility in saturation mode, reaching 5.40 cm2/V-s ± 0.8 cm2/V-s, outperforming other attempts in the literature. This work underscores the potential of CsPbCl3 FETs for high-performance sensing applications, offering insights into optimizing device parameters for enhanced functionality and efficiency.
本研究提出了一种综合方法，通过将数值建模与实验验证相结合，对用于传感应用的氯化铯铅包晶石场效应晶体管（CsPbCl3-FET）进行微调。通过结合 COMSOL Multiphysics 中的有限元方法进行优化，我们定制了场效应晶体管参数，如氧化物和包晶体薄膜厚度。制造的场效应晶体管具有 200 nm 的半导体层和 30 nm 的氧化物厚度，我们战略性地选择了在非耗尽模式下工作，从而在最大限度地提高迁移率的同时最大限度地降低功耗。实验结果与数值模拟紧密吻合，阈值电压为 0.50 V±0.07 V，导通/关断电流比为 1.50 x 104 ± 0.3 x 104，令人印象深刻。值得注意的是，这种过氧化物场效应晶体管在饱和模式下表现出显著的载流子迁移率，达到 5.40 cm2/V-s ± 0.8 cm2/V-s，优于文献中的其他尝试。这项研究强调了 CsPbCl3 FET 在高性能传感应用方面的潜力，为优化器件参数以增强功能和效率提供了启示。
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