Solid-state Electronics最新文献

英文中文

High blocking voltage and low on-state voltage drop 4H-SiC p-channel IGBTs with optimized multizone floating field rings 具有优化的多区浮场环的4H-SiC p沟道igbt高阻塞电压和低导通电压降

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-12 DOI: 10.1016/j.sse.2025.109248

Ruixue Mai , Xiaoli Tian , Xinyu Liu , Xinhua Wang , Yun Bai , Wei Wei , Yuhao Guo , Chengyue Yang , Chengzhan Li , Yidan Tang

A novel multizone floating field ring (M−FFR) edge termination structure with individually increasing ring spacing has been proposed, fabricated, and measured for 4H-silicon carbide (4H-SiC) p-channel insulated gate bipolar transistors (IGBTs). This M−FFR design effectively suppresses electric field crowding at the termination edge while maintaining a high tolerance to oxide charge accumulation. Numerical simulations indicate that the M−FFR achieves a 17.4 % higher blocking voltage compared to conventional equidistant floating field ring (Con-FFR) designs. Importantly, the proposed structure requires no complex fabrication steps or additional lithography processes, reducing manufacturing cost and complexity. To further enhance device performance, carrier lifetime enhancement techniques were applied to reduce the on-state voltage drop (V_f). Experimental measurements confirm that the fabricated p-channel SiC IGBTs are capable of sustaining blocking voltages exceeding 10 kV with leakage currents below 300nA. At a gate voltage of −20 V, a V_f of 5.77 V and a low differential specific on-resistance (R_on,sp,diff) of 17.5 mΩ·cm² were achieved. These results suggest that the device is promising for applications in high-power electronic devices.

针对4h -碳化硅（4H-SiC） p沟道绝缘栅双极晶体管（igbt），提出、制作并测量了一种新的多区浮动场环（M−FFR）边缘端接结构。这种M−FFR设计有效地抑制了终端边缘的电场拥挤，同时保持了对氧化物电荷积累的高容忍度。数值模拟表明，与传统的等距浮动场环（Con-FFR）设计相比，M−FFR实现了17.4%的高阻断电压。重要的是，所提出的结构不需要复杂的制造步骤或额外的光刻工艺，降低了制造成本和复杂性。为了进一步提高器件性能，采用了载波寿命增强技术来降低导通电压降（Vf）。实验测量证实，制备的p沟道SiC igbt能够承受超过10 kV的阻塞电压，泄漏电流低于300nA。在−20 V的栅极电压下，获得了5.77 V的Vf和17.5 mΩ·cm2的低差分比导通电阻（Ron,sp,diff）。这些结果表明，该器件在大功率电子器件中具有广阔的应用前景。

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引用次数: 0

A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model 基于斯坦福模型的基于氧化物的电阻随机存取存储单元编程的封闭模型

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-03 DOI: 10.1016/j.sse.2025.109238

Nadine Dersch , Eduardo Perez , Christian Wenger , Mike Schwarz , Benjamin Iniguez , Alexander Kloes

This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.

本文提出了一种基于脉冲编程的基于氧化物的电阻随机存取存储器器件的封闭模型。以斯坦福模型为基础，以封闭形式求解规划周期。这个溶液的温度是恒定的。通过封闭式模型，可以直接快速地计算出编程后器件的状态或实现特定器件电导所需的编程设置。斯坦福模型需要耗时的迭代计算以获得较高的瞬态分析精度，而这对于闭型模型来说是不必要的。封闭形式的模型可在不同的编程脉冲宽度和电压之间进行扩展。

引用次数: 0

Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs 几何变异性对栅极隧穿泄漏机制的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-20 DOI: 10.1016/j.sse.2025.109212

C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz

Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.

鉴于量子隧穿效应在纳米电子器件的行为中所起的关键作用，有必要研究这些现象对晶体管整体性能的影响和限制。在这项工作中，将先前开发的栅极泄漏模型整合到内部二维多子带集成蒙特卡罗模拟框架中，用于分析流过栅极绝缘子的泄漏电流。主要目的是评估关键几何参数（特别是栅极氧化物和半导体厚度尺寸）的变化如何影响隧道诱发泄漏的大小和偏置依赖性。在具有代表性的FinFET结构上进行了模拟，结果表明，在低栅极电压下，在更薄的氧化物和更厚的半导体厚度的器件中，隧道效应越来越明显。这些发现强调了在先进晶体管架构的预测建模中结合量子隧道机制的相关性。

引用次数: 0

Evidence of out-of-equilibrium body potential in undoped EZ-FET 未掺杂EZ-FET中非平衡体电位的证据

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-18 DOI: 10.1016/j.sse.2025.109251

Abbas Hamzeh , Maryline Bawedin , Nada Zerhouni Abdou , Miltiadis Alepidis , Pablo Acosta-Alba , Laurent Brunet , Irina Ionica

In this paper, we investigate for the first time the variation of out-of-equilibrium body potential during the scan of the back-gate voltage in EZ-FET double-gate structures, built on silicon-on-insulator. This simplified MOSFET, with undoped source and drain is typically used for front and back interface characterization purposes. The out of equilibrium phenomenon, induced by the difficulty to inject instantaneously the carriers needed for the conducting layer creation, is influenced by the front-gate. Two different behaviors are observed, depending on the sign of the front-gate. TCAD simulations confirm the main experimental tendencies.

本文首次研究了基于绝缘体上硅的EZ-FET双栅结构在扫描后栅电压时非平衡体电位的变化。这种简化的MOSFET，具有未掺杂的源极和漏极，通常用于前后界面表征目的。由于难以立即注入生成导电层所需的载流子而引起的非平衡现象受正极的影响。根据前门的标志，可以观察到两种不同的行为。TCAD模拟证实了主要的实验趋势。

引用次数: 0

Colossal permittivity and defect-engineered conduction in Ag/Al/SiO2/Si/Ag MIS structures for next-generation RRAM and 5G/6G capacitors 用于下一代RRAM和5G/6G电容器的Ag/Al/SiO2/Si/Ag MIS结构的巨大介电常数和缺陷工程导通

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-27 DOI: 10.1016/j.sse.2025.109256

A. Ashery

The Ag/Al/SiO₂/Si/Ag metal–insulator-semiconductor (MIS) structure exhibits remarkable dielectric and electrical properties, making it a promising candidate for next-generation electronic applications. This study systematically investigates the colossal permittivity, defect-mediated conduction, and relaxation dynamics of the dual-metal MIS structure using impedance spectroscopy, dielectric analysis, and AC conductivity measurements across wide frequency (1 kHz–20 MHz), temperature (80–400 K), and voltage (±5 V) ranges. Key findings reveal that the Ag/Al electrode configuration induces unique interfacial polarization effects, leading to ultrahigh dielectric constants (ε′ > 103 at low frequencies) and low loss tangents (tanδ < 0.1) suitable for high-frequency capacitors in 5G/6G technologies. The structure also demonstrates voltage-tunable resistive switching via Ag filament formation, enabling ultra-low-power resistive random-access memory (RRAM) with enhanced endurance.

Novelty: Unlike conventional Al/SiO₂/Si devices, the dual-metal design leverages Ag’s high ionic mobility to modulate defect states and conduction pathways, resulting in: Colossal permittivity from space charge polarization at Ag/SiO₂ and SiO₂/Si interfaces. Defect-engineered conduction via thermally activated hopping and Fowler-Nordheim tunneling. Negative capacitance effects at high frequencies, attributed to charge trapping/detrapping dynamics.

New Applications:

RRAM: Controlled Ag migration enables nanoscale filamentary switching with low operating voltages (<3 V).

High-frequency capacitors: Stable ε′ and low tanδ up to 1 MHz meet demands for 5G/6G integrated passives.

Flexible electronics: Compatibility with polymer hybrids (e.g., PVA-SiO₂) allows integration into stretchable substrates.

Challenges such as interfacial defect control and thermal stability are addressed, with proposed solutions including barrier layers and stoichiometric optimization. This work bridges fundamental dielectric spectroscopy with practical device engineering, offering a roadmap for advancing Ag/Al/SiO₂/Si/Ag structures in nanoelectronics and beyond.

Ag/Al/SiO2/Si/Ag金属-绝缘体-半导体（MIS）结构具有卓越的介电性能和电学性能，是下一代电子应用的有前途的候选者。本研究系统地研究了双金属MIS结构在宽频率（1 kHz-20 MHz）、温度（80-400 K）和电压（±5 V）范围内的巨大介电常数、缺陷介导的传导和弛豫动力学，采用阻抗谱、介电分析和交流电导率测量。主要研究结果表明，Ag/Al电极结构可诱导独特的界面极化效应，从而获得适合5G/6G技术中高频电容器的超高介电常数（低频ε′>； 103）和低损耗切线（tanδ < 0.1）。该结构还展示了通过银丝形成的电压可调电阻开关，使超低功耗电阻随机存取存储器（RRAM）具有增强的耐用性。新颖：与传统的Al/SiO2/Si器件不同，双金属设计利用Ag的高离子迁移率来调节缺陷状态和传导途径，从而在Ag/SiO2和SiO2/Si界面上产生巨大的空间电荷极化介电常数。通过热激活跳跃和Fowler-Nordheim隧道的缺陷工程传导。负电容效应在高频，归因于电荷捕获/去捕获动力学。新应用：RRAM：控制银迁移实现低工作电压（< 3v）的纳米级丝状开关。高频电容器：稳定的ε′和高达1 MHz的低tanδ满足5G/6G集成无源的需求。柔性电子：与聚合物杂化（例如，PVA-SiO2）的兼容性允许集成到可拉伸基板中。解决了界面缺陷控制和热稳定性等挑战，提出了包括屏障层和化学计量优化在内的解决方案。这项工作将基本的介电光谱与实际的器件工程联系起来，为在纳米电子学和其他领域推进Ag/Al/SiO2/Si/Ag结构提供了路线图。

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引用次数: 0

Monte Carlo analysis of hot electron injection in the passivation layer of GaN HEMTs 氮化镓hemt钝化层热电子注入的蒙特卡罗分析

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-10-10 DOI: 10.1016/j.sse.2025.109257

Pierpaolo Palestri , Luca Sayadi , Andrea Minetto , Gerhard Prechtl , Luca Selmi , Oliver Häberlen

We investigate the injection of hot electrons in the passivation layer above the drift region of GaN HEMTs by means of Monte-Carlo transport simulations. We find that the lateral component of the electric field in the AlGaN layer delivers a non-negligible kinetic energy to the electrons, thus enhancing injection in the passivation at the top, an effect that is not captured by the standard hot-carrier injection models developed for Si devices that requires the development of ad-hoc hot-carrier injection models for GaN devices. The implications of our calculations for the understanding of reliability and dynamic-

R_{o n}

are also briefly discussed.

利用蒙特卡罗输运模拟研究了GaN hemt漂移区上方钝化层中热电子的注入。我们发现，AlGaN层中电场的横向分量为电子提供了不可忽略的动能，从而增强了顶部钝化的注入，这一效应没有被为Si器件开发的标准热载子注入模型所捕获，因此需要为GaN器件开发特别的热载子注入模型。本文还简要讨论了我们的计算对理解可靠性和动态载荷的影响。

引用次数: 0

Enhancing carrier transport in AlGaN/GaN HEMTs through structural optimization and transconductance modeling 通过结构优化和跨电导建模增强AlGaN/GaN hemt中的载流子输运

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-29 DOI: 10.1016/j.sse.2025.109222

Hyo-Joung Kim , Walid Amir , Surajit Chakraborty , Ju-Won Shin , Ki-Young Shin , Hyuk-Min Kwon , Tae-Woo Kim

In GaN-based High-Electron Mobility Transistors (HEMTs), the carrier transport properties of the 2-Dimensional Electron Gas (2DEG), specifically the saturation velocity (υ_sat) and effective mobility (μ_{n_eff},), are critical determinants of device performance. To enhance these properties, we conducted structural optimizations, which included reducing the Al mole fraction in the Al_xGa_1-xN barrier and introducing an AlGaN back barrier. Recognizing the limitations of traditional extraction techniques, we employed transconductance modeling to accurately extract effective mobility and saturation velocity values. The implementation of the AlGaN back barrier resulted in an effective mobility enhancement to 748 cm²/V·s. Additionally, reducing the Al mole fraction in the Al_xGa_1-xN top barrier led to an effective mobility improvement of 484 cm²/V·s. These findings provide valuable insights into the design of epitaxial structures for AlGaN/GaN HEMTs aimed at achieving superior performance in future applications.

在基于氮化镓的高电子迁移率晶体管（hemt）中，二维电子气体（2DEG）的载流子输运特性，特别是饱和速度（sat）和有效迁移率（μn_eff,）是器件性能的关键决定因素。为了提高这些性能，我们进行了结构优化，包括减少AlxGa1-xN势垒中的Al摩尔分数和引入AlGaN后势垒。认识到传统提取技术的局限性，我们采用跨电导建模来准确提取有效迁移率和饱和速度值。AlGaN后屏障的实施使迁移率有效提高到748 cm2/V·s。此外，降低AlxGa1-xN顶势垒中的Al摩尔分数可使迁移率提高484 cm2/V·s。这些发现为AlGaN/GaN hemt的外延结构设计提供了有价值的见解，旨在在未来的应用中实现卓越的性能。

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引用次数: 0

Study on drain bias dependence of Y-parameters under on-state condition in GaN HEMTs using low-frequency vector network analyzer and device simulation 基于低频矢量网络分析仪和器件仿真的GaN hemt导通条件下y参数漏极偏置依赖性研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-17 DOI: 10.1016/j.sse.2025.109245

Toshiyuki Oishi , Ken Kudara , Yutaro Yamaguchi , Shintaro Shinjo , Koji Yamanaka , Saga University , Mitsubishi Electric Corporation

The drain bias dependence of low-frequency Y-parameters under on-state conditions in Gallium Nitride high electron mobility transistors (GaN HEMTs) is investigated using experimental results and device simulation. The Y-parameters for broadband frequencies from 10 Hz to 100 MHz were systematically measured using a vector network analyzer for drain voltage from 3 to 30 V at the gate voltage of 0 V from room temperature to 120 degrees Celsius. Six signals with the peaks were observed in the imaginary parts (Im) of Y₂₂ and Y₂₁. These peaks were categorized into two groups. One is that the peaks appeared around 5 MHz and have negative slopes in Arrhenius plots. Another is that the peaks appeared below 150 kHz and have an activation energy that can be estimated from Arrhenius plots. The second group was further divided into peaks appeared in both Im(Y₂₂) and Im(Y₂₁), and those that appeared only in Im(Y₂₁). The device simulation including self-heating effects was performed using the trap parameters estimated from the experimental results. Both DC and Y-parameter characteristics for the simulation have good agreement with the experimental results. By the simulation for the individual effects, the peaks around 5 MHz result from the heat generation in GaN HEMTs. The peaks below 150 kHz are considered to originate from the traps in AlGaN and GaN layers. The traps in the GaN layer generate the peaks in both Im(Y₂₂) and Im(Y₂₁), while the traps in the AlGaN layer generate peaks in only Im(Y₂₁).

利用实验结果和器件仿真研究了氮化镓高电子迁移率晶体管（GaN HEMTs）中低频y参数在通态条件下的漏极偏置依赖性。利用矢量网络分析仪系统测量了宽带频率为10 Hz至100 MHz，栅极电压为0 V，漏极电压为3至30 V，室温至120摄氏度范围内的y参数。在Y22和Y21的虚部（Im）观察到6个有峰的信号。这些峰被分为两组。一是在阿累尼乌斯图中，峰出现在5mhz左右，呈负斜率。另一个是峰出现在150khz以下，其活化能可以由Arrhenius图估计。第二组进一步分为同时出现在Im（Y22）和Im（Y21）的峰，以及只出现在Im（Y21）的峰。利用实验结果估计的阱参数，进行了包含自热效应的器件仿真。仿真得到的直流和y参数特性与实验结果吻合较好。通过对单个效应的模拟，5mhz左右的峰值是由GaN hemt中的发热产生的。150 kHz以下的峰被认为是来自于AlGaN和GaN层中的陷阱。GaN层中的陷阱在Im（Y22）和Im（Y21）中都产生峰，而AlGaN层中的陷阱只在Im（Y21）中产生峰。

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Silicon-oxide resistive switching memory based on the HSQ layer 基于HSQ层的氧化硅电阻开关存储器

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-26 DOI: 10.1016/j.sse.2025.109223

Piotr Wiśniewski , Andrzej Mazurak , Alicja Kądziela , Maciej Filipiak , Bartłomiej Stonio , Romuald B. Beck

In this work, we study the silicon-oxide resistive switching memory based on the hydrogen silsesquioxane (HSQ) layer. We fabricated the Al/HSQ/n++ − Si RRAM (Resistive Random Access Memory) devices and performed electrical characterization. Transport mechanisms for different voltage ranges in High Resistance State (HRS) and Low Resistance State (LRS) were identified and analyzed. We show that spin on the silicon oxide layer can result in good resistive switching properties that can be utilized in the design and fabrication of RRAM devices.

本文研究了基于氢硅氧烷（HSQ）层的氧化硅电阻开关存储器。我们制作了Al/HSQ/n++−Si RRAM（电阻随机存取存储器）器件，并进行了电学表征。确定并分析了高阻态和低阻态下不同电压范围的输运机制。我们表明，氧化硅层上的自旋可以产生良好的电阻开关特性，可用于RRAM器件的设计和制造。

引用次数: 0

Non-uniform matching performances in mesa-isolated SOI MOSFETs 台面隔离SOI mosfet的非均匀匹配性能

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-26 DOI: 10.1016/j.sse.2025.109224

Pierre Lhéritier , Daphnée Bosch , Giovanni Romano , Fabienne Ponthenier , Sylvain Joblot , Joris Lacord

This work studies the threshold voltage mismatch of mesa-isolated SOI pMOSFETs through a breakdown between edge and center contributions. Pelgrom’s law is followed if a proper care is taken in the Vt extraction method. Applied to pMOS devices we observed that despite its parasitic nature, the edge transistor mismatch is as good as that of the center, regardless of channel doping and back-gate bias. Mismatch degradation in reverse back-bias mode is observed and attributed to the presence of floating body effects.

本工作通过边缘和中心贡献击穿研究了台面隔离SOI pmosfet的阈值电压失配。如果在Vt提取方法中采取适当的措施，则遵循Pelgrom定律。应用于pMOS器件，我们观察到尽管其寄生性质，但无论通道掺杂和后门偏置如何，边缘晶体管的失配与中心晶体管的失配一样好。在反向偏置模式下观察到失配退化，并归因于浮体效应的存在。

引用次数: 0

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