Pub Date : 2025-10-02DOI: 10.1016/j.sse.2025.109260
Jui-Sheng Wu , Chen-Hsi Tsai , You-Chen Weng , Edward Yi Chang
Ultra-thin-barrier AlGaN/GaN HEMTs offer a gate-recess-free solution but suffer from high on-resistance and current degradation. In this work, ultra-thin-barrier AlGaN/GaN heterostructures with a 1-nm GaN cap and 5-nm Al0.22Ga0.78N barrier were fabricated, followed by LPCVD SiN passivation of four different thicknesses (50, 60, 150, and 220 nm) to solve the low carrier density issues associated with thin-barrier structures. The 220 nm LPCVD-SiN passivated device achieves a high ID,max of 907 mA/mm and the lowest on-resistance of 8.9 Ω·mm. In addition, to evaluate the stability of current output, thinner LPCVD-SiN layers exhibit better current stability under ON-state stress up to 150 °C. These findings highlight the benefits of ultra-thin-barrier AlGaN/GaN HEMTs design for future high-power GaN applications.
{"title":"Enhancing ultra-thin-barrier AlGaN/GaN HEMTs with LPCVD SiN passivation for high-power applications","authors":"Jui-Sheng Wu , Chen-Hsi Tsai , You-Chen Weng , Edward Yi Chang","doi":"10.1016/j.sse.2025.109260","DOIUrl":"10.1016/j.sse.2025.109260","url":null,"abstract":"<div><div>Ultra-thin-barrier AlGaN/GaN HEMTs offer a gate-recess-free solution but suffer from high on-resistance and current degradation. In this work, ultra-thin-barrier AlGaN/GaN heterostructures with a 1-nm GaN cap and 5-nm Al<sub>0.22</sub>Ga<sub>0.78</sub>N barrier were fabricated, followed by LPCVD SiN passivation of four different thicknesses (50, 60, 150, and 220 nm) to solve the low carrier density issues associated with thin-barrier structures. The 220 nm LPCVD-SiN passivated device achieves a high <em>I</em><sub>D,max</sub> of 907 mA/mm and the lowest on-resistance of 8.9 Ω·mm. In addition, to evaluate the stability of current output, thinner LPCVD-SiN layers exhibit better current stability under ON-state stress up to 150 °C. These findings highlight the benefits of ultra-thin-barrier AlGaN/GaN HEMTs design for future high-power GaN applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109260"},"PeriodicalIF":1.4,"publicationDate":"2025-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1016/j.sse.2025.109259
N. Paul , S. Chattopadhyay
The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10−4 μA/μm–1 μA/μm due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10−7 μS/μm–1 μS/μm at room temperature are obtained by varying the nanowire diameter in the range of 20 nm–5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.
{"title":"Design and modeling of resonant tunneling transport-controlled voltage-induced double quantum dot channel nanowire field-effect-transistor (DQD-FET) for multi-threshold current levels","authors":"N. Paul , S. Chattopadhyay","doi":"10.1016/j.sse.2025.109259","DOIUrl":"10.1016/j.sse.2025.109259","url":null,"abstract":"<div><div>The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10<sup>−4</sup> μA/μm–1 μA/μm due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10<sup>−7</sup> μS/μm–1 μS/μm at room temperature are obtained by varying the nanowire diameter in the range of 20 nm–5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109259"},"PeriodicalIF":1.4,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-30DOI: 10.1016/j.sse.2025.109253
Swapna Sarker, Abhishek Kumar, Avirup Dasgupta
We propose a geometry-dependent compact model for subband energies of stacked Gate-All-Around Field Effect Nanosheet Transistors (GAAFETs). The proposed model captures impact of the corner radius along with the width and thickness of the nanosheet on the subband energies. It is crucial to include corner radius dependence since, for highly scaled GAAFETs, variation in corner radius results in considerable change in the geometrical confinement which affects the terminal characteristics of the device. The proposed compact model has been leveraged to perform detailed variability analysis of the GAAFET. The model has been implemented in the industry standard BSIM-CMG framework and validated with subband energy calculations from TCAD. To the best of our knowledge, this is the first variability-aware compact model for subband energies in GAAFETs that takes into account the effect of corner rounding and its impact on terminal characteristics.
{"title":"Physics-based compact model of subband energy for GAAFETs including corner rounding and geometric variability analysis utilizing Monte Carlo simulation","authors":"Swapna Sarker, Abhishek Kumar, Avirup Dasgupta","doi":"10.1016/j.sse.2025.109253","DOIUrl":"10.1016/j.sse.2025.109253","url":null,"abstract":"<div><div>We propose a geometry-dependent compact model for subband energies of stacked Gate-All-Around Field Effect Nanosheet Transistors (GAAFETs). The proposed model captures impact of the corner radius along with the width and thickness of the nanosheet on the subband energies. It is crucial to include corner radius dependence since, for highly scaled GAAFETs, variation in corner radius results in considerable change in the geometrical confinement which affects the terminal characteristics of the device. The proposed compact model has been leveraged to perform detailed variability analysis of the GAAFET. The model has been implemented in the industry standard BSIM-CMG framework and validated with subband energy calculations from TCAD. To the best of our knowledge, this is the first variability-aware compact model for subband energies in GAAFETs that takes into account the effect of corner rounding and its impact on terminal characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109253"},"PeriodicalIF":1.4,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-27DOI: 10.1016/j.sse.2025.109256
A. Ashery
The Ag/Al/SiO2/Si/Ag metal–insulator-semiconductor (MIS) structure exhibits remarkable dielectric and electrical properties, making it a promising candidate for next-generation electronic applications. This study systematically investigates the colossal permittivity, defect-mediated conduction, and relaxation dynamics of the dual-metal MIS structure using impedance spectroscopy, dielectric analysis, and AC conductivity measurements across wide frequency (1 kHz–20 MHz), temperature (80–400 K), and voltage (±5 V) ranges. Key findings reveal that the Ag/Al electrode configuration induces unique interfacial polarization effects, leading to ultrahigh dielectric constants (ε′ > 103 at low frequencies) and low loss tangents (tanδ < 0.1) suitable for high-frequency capacitors in 5G/6G technologies. The structure also demonstrates voltage-tunable resistive switching via Ag filament formation, enabling ultra-low-power resistive random-access memory (RRAM) with enhanced endurance.
Novelty: Unlike conventional Al/SiO2/Si devices, the dual-metal design leverages Ag’s high ionic mobility to modulate defect states and conduction pathways, resulting in: Colossal permittivity from space charge polarization at Ag/SiO2 and SiO2/Si interfaces. Defect-engineered conduction via thermally activated hopping and Fowler-Nordheim tunneling. Negative capacitance effects at high frequencies, attributed to charge trapping/detrapping dynamics.
New Applications:
RRAM: Controlled Ag migration enables nanoscale filamentary switching with low operating voltages (<3 V).
High-frequency capacitors: Stable ε′ and low tanδ up to 1 MHz meet demands for 5G/6G integrated passives.
Flexible electronics: Compatibility with polymer hybrids (e.g., PVA-SiO2) allows integration into stretchable substrates.
Challenges such as interfacial defect control and thermal stability are addressed, with proposed solutions including barrier layers and stoichiometric optimization. This work bridges fundamental dielectric spectroscopy with practical device engineering, offering a roadmap for advancing Ag/Al/SiO2/Si/Ag structures in nanoelectronics and beyond.
{"title":"Colossal permittivity and defect-engineered conduction in Ag/Al/SiO2/Si/Ag MIS structures for next-generation RRAM and 5G/6G capacitors","authors":"A. Ashery","doi":"10.1016/j.sse.2025.109256","DOIUrl":"10.1016/j.sse.2025.109256","url":null,"abstract":"<div><div>The Ag/Al/SiO<sub>2</sub>/Si/Ag metal–insulator-semiconductor (MIS) structure exhibits remarkable dielectric and electrical properties, making it a promising candidate for next-generation electronic applications. This study systematically investigates the colossal permittivity, defect-mediated conduction, and relaxation dynamics of the dual-metal MIS structure using impedance spectroscopy, dielectric analysis, and AC conductivity measurements across wide frequency (1 kHz–20 MHz), temperature (80–400 K), and voltage (±5 V) ranges. Key findings reveal that the Ag/Al electrode configuration induces unique interfacial polarization effects, leading to ultrahigh dielectric constants (ε′ > 103 at low frequencies) and low loss tangents (tanδ < 0.1) suitable for high-frequency capacitors in 5G/6G technologies. The structure also demonstrates voltage-tunable resistive switching via Ag filament formation, enabling ultra-low-power resistive random-access memory (RRAM) with enhanced endurance.</div><div>Novelty: Unlike conventional Al/SiO<sub>2</sub>/Si devices, the dual-metal design leverages Ag’s high ionic mobility to modulate defect states and conduction pathways, resulting in: Colossal permittivity from space charge polarization at Ag/SiO<sub>2</sub> and SiO<sub>2</sub>/Si interfaces. Defect-engineered conduction via thermally activated hopping and Fowler-Nordheim tunneling. Negative capacitance effects at high frequencies, attributed to charge trapping/detrapping dynamics.</div><div>New Applications:</div><div><strong>RRAM</strong>: Controlled Ag migration enables nanoscale filamentary switching with low operating voltages (<3 V).</div><div><strong>High-frequency capacitors</strong>: Stable ε′ and low tanδ up to 1 MHz meet demands for 5G/6G integrated passives.</div><div><strong>Flexible electronics</strong>: Compatibility with polymer hybrids (e.g., PVA-SiO<sub>2</sub>) allows integration into stretchable substrates.</div><div>Challenges such as interfacial defect control and thermal stability are addressed, with proposed solutions including barrier layers and stoichiometric optimization. This work bridges fundamental dielectric spectroscopy with practical device engineering, offering a roadmap for advancing Ag/Al/SiO<sub>2</sub>/Si/Ag structures in nanoelectronics and beyond.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109256"},"PeriodicalIF":1.4,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-24DOI: 10.1016/j.sse.2025.109254
Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga
The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (Vth), ON current (ION), and OFF current (IOFF) is statistically calculated with varying channel doping, source/drain (S/D) extension region (LEXT), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σVth) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in LEXT, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.
{"title":"Statistical analysis of random dopant fluctuation in Complementary FET","authors":"Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga","doi":"10.1016/j.sse.2025.109254","DOIUrl":"10.1016/j.sse.2025.109254","url":null,"abstract":"<div><div>The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V<sub>th</sub>), ON current (I<sub>ON</sub>), and OFF current (I<sub>OFF</sub>) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L<sub>EXT</sub>), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV<sub>th</sub>) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L<sub>EXT</sub>, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109254"},"PeriodicalIF":1.4,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1016/j.sse.2025.109252
A.E. Mavropoulis , G. Pissanos , N. Vasileiadis , P. Normand , G.Ch. Sirakoulis , P. Dimitrakis
The microstructure of SiNx is strongly affected by its stoichiometry, x. The stoichiometry of SiNx thin films can be modified by adjusting the gas flow rates during LPCVD deposition. The deficiency or excess of Si atoms enhance the formation of defects such as nitrogen vacancies, silicon dangling bonds etc., and thus can enable performance tuning of the resulting MIS RRAM devices. DC electrical characterization, impedance spectroscopy and constant voltage stress measurements were carried out to investigate the properties of non-stoichiometric silicon nitride films as resistive switching material. The average SET time for each device was measured by applying voltage ramps. Improvement in the SET/RESET voltages and SET time is observed. Finally, the stoichiometric film exhibits the lowest breakdown acceleration factor, while the Si-rich film the highest.
{"title":"SiNx RRAMs performance with different stoichiometries","authors":"A.E. Mavropoulis , G. Pissanos , N. Vasileiadis , P. Normand , G.Ch. Sirakoulis , P. Dimitrakis","doi":"10.1016/j.sse.2025.109252","DOIUrl":"10.1016/j.sse.2025.109252","url":null,"abstract":"<div><div>The microstructure of SiN<sub>x</sub> is strongly affected by its stoichiometry, x. The stoichiometry of SiN<sub>x</sub> thin films can be modified by adjusting the gas flow rates during LPCVD deposition. The deficiency or excess of Si atoms enhance the formation of defects such as nitrogen vacancies, silicon dangling bonds etc., and thus can enable performance tuning of the resulting MIS RRAM devices. DC electrical characterization, impedance spectroscopy and constant voltage stress measurements were carried out to investigate the properties of non-stoichiometric silicon nitride films as resistive switching material. The average SET time for each device was measured by applying voltage ramps. Improvement in the SET/RESET voltages and SET time is observed. Finally, the stoichiometric film exhibits the lowest breakdown acceleration factor, while the Si-rich film the highest.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109252"},"PeriodicalIF":1.4,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf0.5Zr0.5O2 (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm2 at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.
{"title":"CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit","authors":"Keerthana Shajil Nair , Muhammad Hamid Raza , Catherine Dubourdieu , Veeresh Deshpande","doi":"10.1016/j.sse.2025.109255","DOIUrl":"10.1016/j.sse.2025.109255","url":null,"abstract":"<div><div>Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm<sup>2</sup> at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109255"},"PeriodicalIF":1.4,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1016/j.sse.2025.109247
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
In this work, different Y-function methodologies for the extraction of the electrical MOSFET parameters permitting to model the current–voltage (I–V) transfer characteristics from weak to strong inversion in ohmic mode of operation are compared on ideal I–V characteristics analytically constructed. It is evidenced that even if important discrepancies between the values of the estimated parameters using these methodologies exist, the access resistances value may be predicted with good accuracy. It is demonstrated that if the inversion charge is calculated by combining its asymptotic laws in weak and in strong inversion, this approximation will lead to an about 20% model-induced error in the moderate inversion range.
It is proved that the Y-function strategy which permits the best agreement between the extracted parameter values and the reference ones may be a solution to foresee with lower error the inversion charge behavior from weak to strong inversion even without performing capacitance–voltage measurements.
{"title":"Model and parameter extraction strategy impact on the estimated values of MOSFET parameters in ohmic operation","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109247","DOIUrl":"10.1016/j.sse.2025.109247","url":null,"abstract":"<div><div>In this work, different Y-function methodologies for the extraction of the electrical MOSFET parameters permitting to model the current–voltage (I–V) transfer characteristics from weak to strong inversion in ohmic mode of operation are compared on ideal I–V characteristics analytically constructed. It is evidenced that even if important discrepancies between the values of the estimated parameters using these methodologies exist, the access resistances value may be predicted with good accuracy. It is demonstrated that if the inversion charge is calculated by combining its asymptotic laws in weak and in strong inversion, this approximation will lead to an about 20% model-induced error in the moderate inversion range.</div><div>It is proved that the Y-function strategy which permits the best agreement between the extracted parameter values and the reference ones may be a solution to foresee with lower error the inversion charge behavior from weak to strong inversion even without performing capacitance–voltage measurements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109247"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145327383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we investigate for the first time the variation of out-of-equilibrium body potential during the scan of the back-gate voltage in EZ-FET double-gate structures, built on silicon-on-insulator. This simplified MOSFET, with undoped source and drain is typically used for front and back interface characterization purposes. The out of equilibrium phenomenon, induced by the difficulty to inject instantaneously the carriers needed for the conducting layer creation, is influenced by the front-gate. Two different behaviors are observed, depending on the sign of the front-gate. TCAD simulations confirm the main experimental tendencies.
{"title":"Evidence of out-of-equilibrium body potential in undoped EZ-FET","authors":"Abbas Hamzeh , Maryline Bawedin , Nada Zerhouni Abdou , Miltiadis Alepidis , Pablo Acosta-Alba , Laurent Brunet , Irina Ionica","doi":"10.1016/j.sse.2025.109251","DOIUrl":"10.1016/j.sse.2025.109251","url":null,"abstract":"<div><div>In this paper, we investigate for the first time the variation of out-of-equilibrium body potential during the scan of the back-gate voltage in EZ-FET double-gate structures, built on silicon-on-insulator. This simplified MOSFET, with undoped source and drain is typically used for front and back interface characterization purposes. The out of equilibrium phenomenon, induced by the difficulty to inject instantaneously the carriers needed for the conducting layer creation, is influenced by the front-gate. Two different behaviors are observed, depending on the sign of the front-gate. TCAD simulations confirm the main experimental tendencies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109251"},"PeriodicalIF":1.4,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145118393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1016/j.sse.2025.109250
Run-Song Dou , Jia-Min Li , Fan-Yu Liu , Hui-ping Zhu , Bo Li , Jiang-Jiang Li , Bao-Gang Sun , Yang Huang , Jing Wan , Yong Xu , Zheng-sheng Han , Sorin Cristoloveanu
In this research, we perform an in-depth analysis of the self-heating effect (SHE) and heat transfer characteristics of devices fabricated on silicon-on-insulator (SOI) and silicon-on-silicon carbide (SOS) substrates using technology computer-aided design (TCAD) numerical simulations. The results reveal that, under identical operating conditions, the maximum lattice temperature increase in SOI devices is approximately 3.9 times higher than that in SOS devices, highlighting the superior thermal management properties of SOS devices. When SHE is considered at a gate voltage of 1.8 V, the leakage current in SOS devices decreases by about 27 % compared to SOI devices, demonstrating enhanced resistance to SHE in SOS devices. Analysis of the thermal dissipation pathways reveals that for SOI devices, heat primarily dissipates through the source and drain regions within the device layer, while for SOS devices it predominantly dissipates through the silicon carbide substrate due to its high thermal conductivity, thereby significantly improving thermal dissipation efficiency. Additionally, our research uncovers a correlation between increasing device layer thickness and elevated lattice temperature for both SOI and SOS structures. This phenomenon is closely associated with thermal-electric coupling effects and changes in device thermal resistance.
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