Pub Date : 2024-11-22DOI: 10.1016/j.sse.2024.109035
A.E. Mavropoulis , N. Vasileiadis , P. Normand , C. Theodorou , G. Ch. Sirakoulis , S. Kim , P. Dimitrakis
The role of a 3 nm Al2O3 layer on top of stoichiometric LPCVD SiNx MIS RRAM cells is investigated by using various electrical characterization techniques. The conductive filament formation is explained, and a compact model is used to fit the current–voltage curves and find its evolution during each operation cycle. The conduction in SiNx is also studied.
通过使用各种电表征技术，研究了化学计量LPCVD SiNx MIS RRAM电池上3nm Al2O3层的作用。解释了导电灯丝的形成过程，并建立了一个紧凑的模型来拟合电流-电压曲线，并求出其在每个运行周期内的演变。研究了SiNx中的传导。
{"title":"Effect of Al2O3 on the operation of SiNX-based MIS RRAMs","authors":"A.E. Mavropoulis , N. Vasileiadis , P. Normand , C. Theodorou , G. Ch. Sirakoulis , S. Kim , P. Dimitrakis","doi":"10.1016/j.sse.2024.109035","DOIUrl":"10.1016/j.sse.2024.109035","url":null,"abstract":"<div><div>The role of a 3 nm Al<sub>2</sub>O<sub>3</sub> layer on top of stoichiometric LPCVD SiN<sub>x</sub> MIS RRAM cells is investigated by using various electrical characterization techniques. The conductive filament formation is explained, and a compact model is used to fit the current–voltage curves and find its evolution during each operation cycle. The conduction in SiN<sub>x</sub> is also studied.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109035"},"PeriodicalIF":1.4,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142744547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-19DOI: 10.1016/j.sse.2024.109029
Yili Wang , Kejun Xia , Guofu Niu , Michael Hamilton , Xu Cheng
This article presents a detailed characterization and analysis of a 45 V LDMOS device from production technology across a wide temperature range from 33 to 385 K. For the first time, quasi-saturation behavior is consistently observed throughout the entire temperature range studied. Compared to prior published data, this device shows some notable differences, including a substantially higher saturation temperature of around 200 K for threshold voltage and subthreshold swing due to band tail and a typical low on-resistance down to 33 K, free of freezeout. To account for the observed temperature dependencies, we propose improved semi-empirical temperature scaling equations for the PSPHV model. We extend its applicable temperature range down to 33 K from the previous lower limit of 240 K. The enhancement models the temperature behaviors of key device parameters, including threshold voltage, subthreshold swing, mobility, velocity saturation, drift resistance, and quasi-saturation effects. These results provide new insights into the low-temperature behavior of LDMOS devices for cryogenic electronics applications.
本文详细描述和分析了采用生产技术的 45 V LDMOS 器件在 33 至 385 K 宽温度范围内的特性。与之前公布的数据相比，该器件显示出一些显著差异，包括由于带尾效应，阈值电压和阈下摆动的饱和温度大大高于 200 K 左右，以及典型的低导通电阻（低至 33 K），无冻结现象。为了解释观察到的温度依赖性，我们为 PSPHV 模型提出了改进的半经验温度比例方程。我们将其适用的温度范围从以前的下限 240 K 扩展到 33 K。改进后的模型可模拟关键器件参数的温度行为，包括阈值电压、亚阈值摆幅、迁移率、速度饱和、漂移电阻和准饱和效应。这些结果为低温电子应用中 LDMOS 器件的低温行为提供了新的见解。
{"title":"Characterization of LDMOS down to cryogenic temperatures and modeling with PSPHV","authors":"Yili Wang , Kejun Xia , Guofu Niu , Michael Hamilton , Xu Cheng","doi":"10.1016/j.sse.2024.109029","DOIUrl":"10.1016/j.sse.2024.109029","url":null,"abstract":"<div><div>This article presents a detailed characterization and analysis of a 45 V LDMOS device from production technology across a wide temperature range from 33 to 385 K. For the first time, quasi-saturation behavior is consistently observed throughout the entire temperature range studied. Compared to prior published data, this device shows some notable differences, including a substantially higher saturation temperature of around 200 K for threshold voltage and subthreshold swing due to band tail and a typical low on-resistance down to 33 K, free of freezeout. To account for the observed temperature dependencies, we propose improved semi-empirical temperature scaling equations for the PSPHV model. We extend its applicable temperature range down to 33 K from the previous lower limit of 240 K. The enhancement models the temperature behaviors of key device parameters, including threshold voltage, subthreshold swing, mobility, velocity saturation, drift resistance, and quasi-saturation effects. These results provide new insights into the low-temperature behavior of LDMOS devices for cryogenic electronics applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109029"},"PeriodicalIF":1.4,"publicationDate":"2024-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142703505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-16DOI: 10.1016/j.sse.2024.109027
M. Bendra , R.L. de Orio , S. Selberherr , W. Goes , V. Sverdlov
The development of advanced magnetic tunnel junctions with a footprint in the single-digit nanometer range can be achieved using structures with an elongated and composite ferromagnetic free layer. Using advanced modeling techniques, we investigated the back-hopping effect in ultra-scaled STT-MRAM devices, defined as the unintended switching of the last part of the free layer, leading to an undesired magnetization state of the free layer. To understand the switching of the free layer, the torque acting on both parts of the composite-free layer must be studied in detail. A reduction in the size of MRAM components to increase the memory density may lead to back-hopping. However, the observed back-hopping effect can also be exploited for the realization of multi-level cells. For this purpose, we have carefully investigated the switching behavior of a device with several tunnel barrier interfaces and a few nanometers in diameter. Our studies on ultra-scaled STT-MRAM devices highlight the significant back-hopping effect which, when harnessed, can enable multi-bit cells with four distinct states, enhancing storage and functionality. These insights are pivotal for the design and optimization of future miniaturized spintronics devices.
{"title":"A multi-level cell for ultra-scaled STT-MRAM realized by back-hopping","authors":"M. Bendra , R.L. de Orio , S. Selberherr , W. Goes , V. Sverdlov","doi":"10.1016/j.sse.2024.109027","DOIUrl":"10.1016/j.sse.2024.109027","url":null,"abstract":"<div><div>The development of advanced magnetic tunnel junctions with a footprint in the single-digit nanometer range can be achieved using structures with an elongated and composite ferromagnetic free layer. Using advanced modeling techniques, we investigated the back-hopping effect in ultra-scaled STT-MRAM devices, defined as the unintended switching of the last part of the free layer, leading to an undesired magnetization state of the free layer. To understand the switching of the free layer, the torque acting on both parts of the composite-free layer must be studied in detail. A reduction in the size of MRAM components to increase the memory density may lead to back-hopping. However, the observed back-hopping effect can also be exploited for the realization of multi-level cells. For this purpose, we have carefully investigated the switching behavior of a device with several tunnel barrier interfaces and a few nanometers in diameter. Our studies on ultra-scaled STT-MRAM devices highlight the significant back-hopping effect which, when harnessed, can enable multi-bit cells with four distinct states, enhancing storage and functionality. These insights are pivotal for the design and optimization of future miniaturized spintronics devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109027"},"PeriodicalIF":1.4,"publicationDate":"2024-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142703504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-13DOI: 10.1016/j.sse.2024.109028
Welder F. Perina , Joao A. Martino , Eddy Simoen , Uthayasankaran Peralagu , Nadine Collaert , Paula G.D. Agopian
This work presents an analysis on experimental analog behavior of MISHEMTs operating in the temperature range from 450 K down to 200 K. The drain current (IDS) presented a slight anomaly, especially for temperatures lower than 400 K. In the transconductance it is possible to visualize a second peak, suggesting a second conduction. As shown, the transconductance presented a low dependence on gate length, and an anomaly was observed for the devices at 350 K. The output conductance and transistor efficiency behavior suggest a competition between the effects of the MOS and HEMT conductions, present in the device. A new kink was observed in the output characteristic (IDSxVDS) at room temperature, which is caused by the HEMT and MOS conductions interaction, and it is even more noticeable for higher overdrive voltages (VGT). This effect is called MISHEMT kink effect (MH-kink) in this work. The MH-kink shifts toward higher VDS for higher overdrive voltage, showing the stronger influence of the MOS conduction on the total drain current. The unity gain frequency (ft) increases from 800 MHz (450 K) to 1.8 GHz (200 K), while the AV goes in opposite direction from 43 dB (450 K) to 38 dB (200 K). Considering that the intrinsic voltage gain is good enough even at low temperatures, the MISHEMT can be identified as a good candidate for analog applications.
这项研究分析了在 450 K 至 200 K 温度范围内工作的 MISHEMT 的模拟实验行为。漏极电流（IDS）出现了轻微异常，尤其是在低于 400 K 的温度下。如图所示，跨导对栅极长度的依赖性较低，在 350 K 时器件出现异常。输出电导和晶体管效率行为表明，器件中存在 MOS 和 HEMT 传导效应之间的竞争。在室温下的输出特性（IDSxVDS）中观察到了一种新的扭结，这是 HEMT 和 MOS 导体相互作用造成的，在过驱动电压 (VGT) 较高时更为明显。这种效应在本文中称为 MISHEMT 扭结效应（MH-kink）。当过驱动电压升高时，MH-kink 会向更高的 VDS 方向移动，这表明 MOS 导通对漏极总电流的影响更大。统一增益频率 (ft) 从 800 MHz (450 K) 上升到 1.8 GHz (200 K)，而 AV 则相反，从 43 dB (450 K) 下降到 38 dB (200 K)。考虑到即使在低温条件下，MISHEMT 的固有电压增益也足够好，因此可以确定它是模拟应用的理想候选器件。
{"title":"Temperature influence on experimental analog behavior of MISHEMTs","authors":"Welder F. Perina , Joao A. Martino , Eddy Simoen , Uthayasankaran Peralagu , Nadine Collaert , Paula G.D. Agopian","doi":"10.1016/j.sse.2024.109028","DOIUrl":"10.1016/j.sse.2024.109028","url":null,"abstract":"<div><div>This work presents an analysis on experimental analog behavior of MISHEMTs operating in the temperature range from 450 K down to 200 K. The drain current (I<sub>DS</sub>) presented a slight anomaly, especially for temperatures lower than 400 K. In the transconductance it is possible to visualize a second peak, suggesting a second conduction. As shown, the transconductance presented a low dependence on gate length, and an anomaly was observed for the devices at 350 K. The output conductance and transistor efficiency behavior suggest a competition between the effects of the MOS and HEMT conductions, present in the device. A new kink was observed in the output characteristic (I<sub>DS</sub>xV<sub>DS</sub>) at room temperature, which is caused by the HEMT and MOS conductions interaction, and it is even more noticeable for higher overdrive voltages (V<sub>GT</sub>). This effect is called MISHEMT kink effect (MH-kink) in this work. The MH-kink shifts toward higher V<sub>DS</sub> for higher overdrive voltage, showing the stronger influence of the MOS conduction on the total drain current. The unity gain frequency (f<sub>t</sub>) increases from 800 MHz (450 K) to 1.8 GHz (200 K), while the A<sub>V</sub> goes in opposite direction from 43 dB (450 K) to 38 dB (200 K). Considering that the intrinsic voltage gain is good enough even at low temperatures, the MISHEMT can be identified as a good candidate for analog applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109028"},"PeriodicalIF":1.4,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-08DOI: 10.1016/j.sse.2024.109023
Wei-Qi Huang , Yin-Lian Li , Zhong-Mei Huang , Hao-Ze Wang , Shi-Rong Liu
We prepare the PN junction on silicon chip by a novel method with surface plasmon generated under pulsed laser irradiation. It is found that the interaction between laser photons and plasma produces a plasmon layer, in which the faster electrons take resonance with photons to generate surface electron gas. It is interesting that the electron gas in high vacuum and the plasmon polarized in various atmosphere are directly observed by the Talbot reflect image with outstanding challenge. It is demonstrated that injection and diffusion can be completed quickly to form higher quality PN region on interface between ions layer and substrate while the plasmon dipole makes resonance with phonon, where the quantum energy of plasmon is closed to the phonon energy in silicon crystal. In this novel way, the PN junction structure can be built by coherent photons on silicon chip at first, and the different preparing processes are explored comparatively by using the I-V curves measured with nonlinear characteristic of PN junction for application in optic-electronic integration field.
{"title":"A novel method used to prepare PN junction by plasmon generated under pulsed laser irradiation on silicon chip","authors":"Wei-Qi Huang , Yin-Lian Li , Zhong-Mei Huang , Hao-Ze Wang , Shi-Rong Liu","doi":"10.1016/j.sse.2024.109023","DOIUrl":"10.1016/j.sse.2024.109023","url":null,"abstract":"<div><div>We prepare the PN junction on silicon chip by a novel method with surface plasmon generated under pulsed laser irradiation. It is found that the interaction between laser photons and plasma produces a plasmon layer, in which the faster electrons take resonance with photons to generate surface electron gas. It is interesting that the electron gas in high vacuum and the plasmon polarized in various atmosphere are directly observed by the Talbot reflect image with outstanding challenge. It is demonstrated that injection and diffusion can be completed quickly to form higher quality PN region on interface between ions layer and substrate while the plasmon dipole makes resonance with phonon, where the quantum energy of plasmon is closed to the phonon energy in silicon crystal. In this novel way, the PN junction structure can be built by coherent photons on silicon chip at first, and the different preparing processes are explored comparatively by using the I-V curves measured with nonlinear characteristic of PN junction for application in optic-electronic integration field.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109023"},"PeriodicalIF":1.4,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-02DOI: 10.1016/j.sse.2024.109024
Gangadhar Bandewad , Chetan Kamble , Sunil Pawar
The gas sensing capabilities of Bi2S3 chalcogenide have been actively enhanced and explored revealing its potential for high-performance Cl2 gas detection under different environmental conditions and sensing configurations. This work successfully synthesized Bi2S3 material via the SILAR method and further enhanced its sensing capabilities by fabricating Ag-Bi2S3 nanocomposite. Both pristine Bi2S3 and Ag-Bi2S3 nanocomposite films underwent comprehensive characterization utilizing techniques such as FESEM, EDX, XRD, XPS, and RAMAN to analyze their morphological, structural, and chemical properties. Gas sensing capabilities were evaluated across a temperature range of 26–350 °C and varying Cl2 gas concentrations (0.1–50 ppm). The findings reveal that the Ag-Bi2S3 sensor demonstrates notably superior Cl2 sensing response, particularly at an operational temperature of 150 °C, suggesting its promising potential for Cl2 detection. The LOD has been calculated for Ag-Bi2S3 sensor showing results of 0.150 better than pristine Bi2S3. HOMO-LUMO and PCA analysis for sensors has been studied to understand their capabilities with different gas sensing.
{"title":"Influence of Ag-Bi2S3 nanocomposites for highly sensitive and selective Cl2 gas sensors: Synthesis, characterization, and gas sensing performance","authors":"Gangadhar Bandewad , Chetan Kamble , Sunil Pawar","doi":"10.1016/j.sse.2024.109024","DOIUrl":"10.1016/j.sse.2024.109024","url":null,"abstract":"<div><div>The gas sensing capabilities of Bi<sub>2</sub>S<sub>3</sub> chalcogenide have been actively enhanced and explored revealing its potential for high-performance Cl<sub>2</sub> gas detection under different environmental conditions and sensing configurations. This work successfully synthesized Bi<sub>2</sub>S<sub>3</sub> material via the SILAR method and further enhanced its sensing capabilities by fabricating Ag-Bi<sub>2</sub>S<sub>3</sub> nanocomposite. Both pristine Bi<sub>2</sub>S<sub>3</sub> and Ag-Bi<sub>2</sub>S<sub>3</sub> nanocomposite films underwent comprehensive characterization utilizing techniques such as FESEM, EDX, XRD, XPS, and RAMAN to analyze their morphological, structural, and chemical properties. Gas sensing capabilities were evaluated across a temperature range of 26–350 °C and varying Cl<sub>2</sub> gas concentrations (0.1–50 ppm). The findings reveal that the Ag-Bi<sub>2</sub>S<sub>3</sub> sensor demonstrates notably superior Cl<sub>2</sub> sensing response, particularly at an operational temperature of 150 °C, suggesting its promising potential for Cl<sub>2</sub> detection. The LOD has been calculated for Ag-Bi<sub>2</sub>S<sub>3</sub> sensor showing results of 0.150 better than pristine Bi<sub>2</sub>S<sub>3.</sub> HOMO-LUMO and PCA analysis for sensors has been studied to understand their capabilities with different gas sensing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109024"},"PeriodicalIF":1.4,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142652701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-02DOI: 10.1016/j.sse.2024.109025
Fahim Ullah , Kamran Hasrat , Sami Iqbal , Shuang Wang
This study investigates the progress in n-type solar cells utilizing implanted Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) front surface fields and diffused Ag rear emitters. The n-type structure utilizes a systematic approach involving surface passivation, localized laser ablation, and screen printing, similar to commercial p-type solar cells. This design enables the conversion from p-type to n-type cell production. Ion implantation allows for accurate management of doping profiles, improving processing sequences and increasing efficiency. Analysis indicates that reduced post-implant annealing durations lead to a shallower doping profile, enhancing short-wavelength response. Its results in efficiencies reaching up to 15.75 % on large-area 200 cm2 n-type wafers. The study also examines hybrid planar-Si/organic heterojunction solar cells, emphasizing Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) to improve photovoltaic efficiency. UV–visible and fluorescence spectroscopy indicate a maximum absorption wavelength of 360 nm and an emission wavelength of 420 nm. The concentration of TTB-TB-BNZ in (4,4′-di(9H-carbazol-9-yl)-1,1′-biphenyl) (CBP) films reaches its peak effectiveness at 40–50 %, leading to notable enhancements in light absorption and charge transport. The Si/PEDOT: PSS heterojunction solar cells incorporating TTB-TB-BNZ demonstrate a power conversion efficiency (PCE) of 15.75 %. This result underscores the potential for scalable fabrication methods to improve photovoltaic performance.
本研究探讨了利用植入式四叔丁基三咔唑-苯腈（TTB-TB-BNZ）前表面场和扩散式银后发射器的 n 型太阳能电池的研究进展。这种 n 型结构采用了与商用 p 型太阳能电池类似的系统方法，包括表面钝化、局部激光烧蚀和丝网印刷。这种设计实现了从 p 型电池到 n 型电池的生产转换。离子注入可实现对掺杂曲线的精确管理，改进加工顺序并提高效率。分析表明，缩短植入后退火持续时间可使掺杂剖面更浅，从而增强短波长响应。这使得 200 平方厘米大面积 n 型晶片的效率高达 15.75%。研究还考察了混合平面硅/有机异质结太阳能电池，强调利用四叔丁基三咔唑-苯腈（TTB-TB-BNZ）来提高光伏效率。紫外可见光谱和荧光光谱显示，其最大吸收波长为 360 纳米，发射波长为 420 纳米。在（4,4′-二（9H-咔唑-9-基）-1,1′-联苯）（CBP）薄膜中，TTB-TB-BNZ 的浓度在 40-50 % 时达到峰值效果，从而显著提高了光吸收和电荷传输能力。Si/PEDOT：PSS 异质结太阳能电池的功率转换效率 (PCE) 达到 15.75%。这一结果凸显了可扩展制造方法在提高光伏性能方面的潜力。
{"title":"Achieving 15.75% efficiency in solar cells: Advanced surface engineering using Tetra-Tert-Butyl-Tercarbazol-Benzonitrile and organic layer integration in n-type silicon wafer and hybrid Planar-Si systems","authors":"Fahim Ullah , Kamran Hasrat , Sami Iqbal , Shuang Wang","doi":"10.1016/j.sse.2024.109025","DOIUrl":"10.1016/j.sse.2024.109025","url":null,"abstract":"<div><div>This study investigates the progress in n-type solar cells utilizing implanted Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) front surface fields and diffused Ag rear emitters. The n-type structure utilizes a systematic approach involving surface passivation, localized laser ablation, and screen printing, similar to commercial p-type solar cells. This design enables the conversion from p-type to n-type cell production. Ion implantation allows for accurate management of doping profiles, improving processing sequences and increasing efficiency. Analysis indicates that reduced post-implant annealing durations lead to a shallower doping profile, enhancing short-wavelength response. Its results in efficiencies reaching up to 15.75 % on large-area 200 cm2 n-type wafers. The study also examines hybrid planar-Si/organic heterojunction solar cells, emphasizing Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) to improve photovoltaic efficiency. UV–visible and fluorescence spectroscopy indicate a maximum absorption wavelength of 360 nm and an emission wavelength of 420 nm. The concentration of TTB-TB-BNZ in (4,4′-di(9H-carbazol-9-yl)-1,1′-biphenyl) (CBP) films reaches its peak effectiveness at 40–50 %, leading to notable enhancements in light absorption and charge transport. The Si/PEDOT: PSS heterojunction solar cells incorporating TTB-TB-BNZ demonstrate a power conversion efficiency (PCE) of 15.75 %. This result underscores the potential for scalable fabrication methods to improve photovoltaic performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109025"},"PeriodicalIF":1.4,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142586195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The role of interface energetics-modification in interface-defect passivation and optimal interface energy-level matching is assumed to be a crucial aspect. Enhancing the performance and durability of perovskite solar cells (PSCs) can be achieved through this strategy. Here, spiro-OMeTAD [2,2′,7,7′-tetrakis (N, N-di-p-methoxyphenylamine)-9,9′-spirobifluorene] has been pipetted onto the spinning perovskite precursor film via a chlorobenzene anti-solvent strategy. It is found that spiro-OMeTAD serves as not only the filler at grain boundaries, but also the coverage on perovskite’s grain, and then forms the gradual homojunction interface from perovskite to spiro-OMeTAD hole transport layer, which can make spiro-OMeTAD anchor perovskite via the reaction between Pb2+ and C-O groups to decrease the interface barrier and obtain the optimal interface energy-level match between them for hole −migration and −collection. Moreover, these fillers or coverages can prevent moisture invading perovskite. Consequently, the counterpart PSC achieves a champion efficiency of 24.46 %, and has retained more than 88 % of the initial efficiency after 224 days of storage.
{"title":"Spiro-OMeTAD Anchoring perovskite for gradual homojunction in stable perovskite solar cells","authors":"Ziyi Wang , Bobo Yuan , Yiheng Gao, Rui Wu, Shuping Xiao, Wuchen Xiang, Xueli Yu, Pingli Qin","doi":"10.1016/j.sse.2024.109003","DOIUrl":"10.1016/j.sse.2024.109003","url":null,"abstract":"<div><div>The role of interface energetics-modification in interface-defect passivation and optimal interface energy-level matching is assumed to be a crucial aspect. Enhancing the performance and durability of perovskite solar cells (PSCs) can be achieved through this strategy. Here, spiro-OMeTAD [2,2′,7,7′-tetrakis (N, N-di-p-methoxyphenylamine)-9,9′-spirobifluorene] has been pipetted onto the spinning perovskite precursor film via a chlorobenzene anti-solvent strategy. It is found that spiro-OMeTAD serves as not only the filler at grain boundaries, but also the coverage on perovskite’s grain, and then forms the gradual homojunction interface from perovskite to spiro-OMeTAD hole transport layer, which can make spiro-OMeTAD anchor perovskite via the reaction between Pb<sup>2+</sup> and C-O groups to decrease the interface barrier and obtain the optimal interface energy-level match between them for hole −migration and −collection. Moreover, these fillers or coverages can prevent moisture invading perovskite. Consequently, the counterpart PSC achieves a champion efficiency of 24.46 %, and has retained more than 88 % of the initial efficiency after 224 days of storage.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109003"},"PeriodicalIF":1.4,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142571714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-22DOI: 10.1016/j.sse.2024.109012
Minsik Park , Minkyoung Seong , Jaeyong Jeong , Seungin Lee , Jonghyun Song , Hyoungho Ko , Ga-Won Lee , Woo-Suk Sul , Won-Chul Lee , Sanghyeon Kim , Jongwon Lee
In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).
{"title":"Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band","authors":"Minsik Park , Minkyoung Seong , Jaeyong Jeong , Seungin Lee , Jonghyun Song , Hyoungho Ko , Ga-Won Lee , Woo-Suk Sul , Won-Chul Lee , Sanghyeon Kim , Jongwon Lee","doi":"10.1016/j.sse.2024.109012","DOIUrl":"10.1016/j.sse.2024.109012","url":null,"abstract":"<div><div>In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"221 ","pages":"Article 109012"},"PeriodicalIF":1.4,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We explored the effects of gate work function variation (WFV) through device simulation on a fin-shaped silicon quantum dot device with a multi-gate configuration for a large-scale integrated array. The threshold voltage (Vth) of current–voltage characteristics is affected by WFV in both main and surrounding gates, indicating the existence of electrostatic coupling among these gates. The electrostatic coupling can be reduced by biasing on the surrounding gates. Furthermore, the concept of Vth, following conventional transistors, works as a reference of voltage and potential in the present multi-gate device. This knowledge contributes to establishing a practical method for the statistical analysis of qubit variability.
{"title":"Influence of gate work function variations on characteristics of fin-shaped silicon quantum dot device with multi-gate under existence of gate electrostatic coupling","authors":"Kimihiko Kato, Hidehiro Asai, Hiroshi Oka, Shota Iizuka, Hiroshi Fuketa, Takumi Inaba, Takahiro Mori","doi":"10.1016/j.sse.2024.109013","DOIUrl":"10.1016/j.sse.2024.109013","url":null,"abstract":"<div><div>We explored the effects of gate work function variation (WFV) through device simulation on a fin-shaped silicon quantum dot device with a multi-gate configuration for a large-scale integrated array. The threshold voltage (<em>V</em><sub>th</sub>) of current–voltage characteristics is affected by WFV in both main and surrounding gates, indicating the existence of electrostatic coupling among these gates. The electrostatic coupling can be reduced by biasing on the surrounding gates. Furthermore, the concept of <em>V</em><sub>th</sub>, following conventional transistors, works as a reference of voltage and potential in the present multi-gate device. This knowledge contributes to establishing a practical method for the statistical analysis of qubit variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109013"},"PeriodicalIF":1.4,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142533072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
扫码关注我们
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号