Pub Date : 2025-11-05DOI: 10.1016/j.sse.2025.109288
Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński
In this work, we present the investigation of resistive switching properties in Ag/SiOx/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.
{"title":"Investigation of compliance current effect on resistive switching properties in Ag/SiOx/Cr RRAM devices","authors":"Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński","doi":"10.1016/j.sse.2025.109288","DOIUrl":"10.1016/j.sse.2025.109288","url":null,"abstract":"<div><div>In this work, we present the investigation of resistive switching properties in Ag/SiO<sub>x</sub>/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109288"},"PeriodicalIF":1.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145517352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.sse.2025.109291
Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian
This work is related to the analysis of Gate-All-Around Nanosheet (GAA-NSH) devices operating from 125 °C down to −100 °C, focusing on their analog potential. The Verilog-A model was developed using experimental data, and the two-stage operational transconductance amplifier (OTA) was designed for transistor efficiency (gm ⁄ IDS) of around 8 V−1 and supply voltage (VDD) of 1.8 V at room temperature. The OTA temperature influence was analyzed for different temperatures. When the temperature ranges from 125 °C to −100 °C, the OTA voltage gain improved from 63.2 to 72.4 dB and the gain bandwidth product (GBW) also improved from 354 to 460 MHz, considering that the bias circuit (ISS) is temperature-compensated (ISS and VCM are constant in the studied temperature range). The obtained results show that the nanosheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits in this temperature range.
{"title":"Nanosheet Transistor Applied in a Two-Stage Operational Transconductance Amplifier from 125 °C down to −100 °C","authors":"Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian","doi":"10.1016/j.sse.2025.109291","DOIUrl":"10.1016/j.sse.2025.109291","url":null,"abstract":"<div><div>This work is related to the analysis of Gate-All-Around Nanosheet (GAA-NSH) devices operating from 125 °C down to −100 °C, focusing on their analog potential. The Verilog-A model was developed using experimental data, and the two-stage operational transconductance amplifier (OTA) was designed for transistor efficiency (g<sub>m</sub> ⁄ I<sub>DS</sub>) of around 8 V<sup>−1</sup> and supply voltage (V<sub>DD</sub>) of 1.8 V at room temperature. The OTA temperature influence was analyzed for different temperatures. When the temperature ranges from 125 °C to −100 °C, the OTA voltage gain improved from 63.2 to 72.4 dB and the gain bandwidth product (GBW) also improved from 354 to 460 MHz, considering that the bias circuit (I<sub>SS</sub>) is temperature-compensated (I<sub>SS</sub> and V<sub>CM</sub> are constant in the studied temperature range). The obtained results show that the nanosheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits in this temperature range.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109291"},"PeriodicalIF":1.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-02DOI: 10.1016/j.sse.2025.109283
Yitao Wang , Shuoxin Ji , Yang Wang
Due to the harsh working environments of Input/Output (I/O) pins, the electro-static discharge (ESD) protection devices of these ports often require high robustness. To design highly robust ESD protection devices with dual polarities, the Gate-controlled dual direction silicon controlled rectifier (GCDDSCR) and a DDSCR embedded with Schottky barrier diode (SBD-GCDDSCR) structures are designed and studied in this article as standalone devices for primary protection. The gate-controlled diodes and Schottky diodes are integrated into the simple DDSCR structure to enhance its robustness while reducing the on-resistance. The inclusion of gate diodes introduced an additional current path near the surface, improving space utilization in the longitudinal direction of the device, and the addition of Schottky junctions placed adjacent to the Anode and Cathode can provide additional electron extraction paths. Both methods contribute in a more uniform current distribution, improving the robustness of the device. Two-dimensional device simulation based on a classical set of equations was employed to investigate its electrical behavior during an ESD event. Based on the 0.18 μm CMOS process, all structures were fabricated into 6-finger devices with a finger length of 50 μm. The Transmission Line Pulse (TLP) testing method was used to evaluate their ESD characteristics, revealing that the addition of the gate-controlled diodes and Schottky shunt paths improved robustness. The proposed SBD-GCDDSCR structure demonstrated superior robustness under ESD stress, with a failure current exceeding 19 A in both forward and reverse directions, and its Vt2 in strong saturation regime is around 48 V.
{"title":"Design of high robustness DDSCR with embedded gate-controlled diodes and Schottky diodes","authors":"Yitao Wang , Shuoxin Ji , Yang Wang","doi":"10.1016/j.sse.2025.109283","DOIUrl":"10.1016/j.sse.2025.109283","url":null,"abstract":"<div><div>Due to the harsh working environments of Input/Output (I/O) pins, the electro-static discharge (ESD) protection devices of these ports often require high robustness. To design highly robust ESD protection devices with dual polarities, the Gate-controlled dual direction silicon controlled rectifier (GCDDSCR) and a DDSCR embedded with Schottky barrier diode (SBD-GCDDSCR) structures are designed and studied in this article as standalone devices for primary protection. The gate-controlled diodes and Schottky diodes are integrated into the simple DDSCR structure to enhance its robustness while reducing the on-resistance. The inclusion of gate diodes introduced an additional current path near the surface, improving space utilization in the longitudinal direction of the device, and the addition of Schottky junctions placed adjacent to the Anode and Cathode can provide additional electron extraction paths. Both methods contribute in a more uniform current distribution, improving the robustness of the device. Two-dimensional device simulation based on a classical set of equations was employed to investigate its electrical behavior during an ESD event. Based on the 0.18 μm CMOS process, all structures were fabricated into 6-finger devices with a finger length of 50 μm. The Transmission Line Pulse (TLP) testing method was used to evaluate their ESD characteristics, revealing that the addition of the gate-controlled diodes and Schottky shunt paths improved robustness. The proposed SBD-GCDDSCR structure demonstrated superior robustness under ESD stress, with a failure current exceeding 19 A in both forward and reverse directions, and its V<sub>t2</sub> in strong saturation regime is around 48 V.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109283"},"PeriodicalIF":1.4,"publicationDate":"2025-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01DOI: 10.1016/j.sse.2025.109270
Kosuke Yamaguchi, Satofumi Souma
We propose an efficient device-circuit co-simulation framework for phosphorene tunnel FETs, focusing on circuit-level impacts of structural imperfections such as grain boundaries and adsorption. A fast table-generation scheme based on the scattering matrix approach and a capacitance model enables physically grounded current and capacitance characteristics to be obtained across bias conditions. These tables are smoothly integrated into SPICE simulations via Verilog-A, naturally capturing effects such as DIBL and intrinsic capacitances. Using this framework, we demonstrate the sensitivity of inverter and ring oscillator performance to the magnitude and position of grain boundaries, highlighting their role as a major source of variability in 2D TFET circuits. Overall, the framework provides a practical and extensible platform for evaluating low-power 2D devices under realistic variability.
{"title":"Scattering matrix-based low computational cost model for the device and circuit co-simulation of phosphorene tunnel field-effect transistors","authors":"Kosuke Yamaguchi, Satofumi Souma","doi":"10.1016/j.sse.2025.109270","DOIUrl":"10.1016/j.sse.2025.109270","url":null,"abstract":"<div><div>We propose an efficient device-circuit co-simulation framework for phosphorene tunnel FETs, focusing on circuit-level impacts of structural imperfections such as grain boundaries and adsorption. A fast table-generation scheme based on the scattering matrix approach and a capacitance model enables physically grounded current and capacitance characteristics to be obtained across bias conditions. These tables are smoothly integrated into SPICE simulations via Verilog-A, naturally capturing effects such as DIBL and intrinsic capacitances. Using this framework, we demonstrate the sensitivity of inverter and ring oscillator performance to the magnitude and position of grain boundaries, highlighting their role as a major source of variability in 2D TFET circuits. Overall, the framework provides a practical and extensible platform for evaluating low-power 2D devices under realistic variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109270"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Schottky barrier photodetectors (SBPDs) have low-cost fabrication, CMOS compatibility, and scalability. This work presents a comparative analysis of Cu/n-Si Schottky photodetectors fabricated using two distinct copper deposition techniques: thermal evaporation and RF sputtering. Comparative analyses were conducted using field-emission scanning electron microscopy (FE-SEM), electrical I–V measurements, responsivity analysis, and time-resolved photocurrent studies. Morphological characterization revealed that thermally evaporated films formed larger, anisotropic grains, whereas RF-sputtered films exhibited finer and more uniform grain structures. Devices fabricated via RF sputtering exhibited superior electrical and optoelectronic performance with higher photocurrent, enhanced responsivity (up to 0.146 A/W under 532 nm illumination and 0.038 A/W under 650 nm illumination), and faster, more stable photoresponses—even under zero-bias conditions. These results demonstrate the significant role of deposition technique in tuning microstructure and optimizing photodetector efficiency for low-power sensing applications.
{"title":"Enhanced photoresponse in Cu/n-Si Schottky photodetectors via RF sputtering: A comparative study with thermal evaporation","authors":"Rajat Kumar Goyal , Madhuram Mishra , Pragya Kushwaha , Sunil Babu Eadi , Harshit Agarwal","doi":"10.1016/j.sse.2025.109268","DOIUrl":"10.1016/j.sse.2025.109268","url":null,"abstract":"<div><div>Schottky barrier photodetectors (SBPDs) have low-cost fabrication, CMOS compatibility, and scalability. This work presents a comparative analysis of Cu/n-Si Schottky photodetectors fabricated using two distinct copper deposition techniques: thermal evaporation and RF sputtering. Comparative analyses were conducted using field-emission scanning electron microscopy (FE-SEM), electrical I–V measurements, responsivity analysis, and time-resolved photocurrent studies. Morphological characterization revealed that thermally evaporated films formed larger, anisotropic grains, whereas RF-sputtered films exhibited finer and more uniform grain structures. Devices fabricated via RF sputtering exhibited superior electrical and optoelectronic performance with higher photocurrent, enhanced responsivity (up to 0.146 A/W under 532 nm illumination and 0.038 A/W under 650 nm illumination), and faster, more stable photoresponses—even under zero-bias conditions. These results demonstrate the significant role of deposition technique in tuning microstructure and optimizing photodetector efficiency for low-power sensing applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109268"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-29DOI: 10.1016/j.sse.2025.109285
Benjamin Bureau , Félix Beaudoin , Pericles Philippopoulos , Salvador Mir , Eva Dupont-Ferrier , Philippe Galy
The emergence of cryo-electronics and quantum applications has shown that experiments involving quantum dots are highly sensitive to disorder and variability. This sensitivity offers the opportunity to detect and classify defects, evaluate process quality in detail, and guide the enhancement of robustness. In this preliminary work, we explore the 3D quantum simulation of an industrial FD-SOI quantum dot device, with and without a charge defect.
{"title":"3D simulation of charge defect impact on an industrial 28 nm FD-SOI quantum dot","authors":"Benjamin Bureau , Félix Beaudoin , Pericles Philippopoulos , Salvador Mir , Eva Dupont-Ferrier , Philippe Galy","doi":"10.1016/j.sse.2025.109285","DOIUrl":"10.1016/j.sse.2025.109285","url":null,"abstract":"<div><div>The emergence of cryo-electronics and quantum applications has shown that experiments involving quantum dots are highly sensitive to disorder and variability. This sensitivity offers the opportunity to detect and classify defects, evaluate process quality in detail, and guide the enhancement of robustness. In this preliminary work, we explore the 3D quantum simulation of an industrial FD-SOI quantum dot device, with and without a charge defect.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109285"},"PeriodicalIF":1.4,"publicationDate":"2025-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-28DOI: 10.1016/j.sse.2025.109266
Sara Sacchi , Anirudh Varanasi , Robin Degraeve , Andrea Vici , Giorgio Molinaro , Jacopo Franco , Philippe Roussel , Ben Kaczer , Clement Merckling
Time-Dependent Dielectric Breakdown (TDDB) remains a critical reliability challenge in advanced CMOS technologies using thin /High-k oxides. While extensive research focused on the formation of conductive filaments and the physics and statistics of soft breakdown and hard breakdown events, the intermediate wear-out phase — where a localized leakage path gradually increases in conductivity — has not been thoroughly analyzed or modeled. Firstly, this work addresses this gap by experimentally isolating and analyzing the wear-out phase with a Machine learning-assisted analysis, revealing key statistical features of wear-out and its dependence on stress voltage. Secondly, a Monte Carlo-implemented Markov model is used to simulate the localized degradation of a one-defect percolation path by means of a thermally activated defect creation and deactivation/annealing process, governed by an Arrhenius-like transition probability function. Simulations qualitatively reproduce the observed experimental degradation trends, with discrepancies in voltage dependence and initial defect accumulation, highlighting the need for a more nuanced approach, including statistical distributions of atomic bond strengths.
{"title":"Markov model describing progressive degradation of local percolation path in thin oxides","authors":"Sara Sacchi , Anirudh Varanasi , Robin Degraeve , Andrea Vici , Giorgio Molinaro , Jacopo Franco , Philippe Roussel , Ben Kaczer , Clement Merckling","doi":"10.1016/j.sse.2025.109266","DOIUrl":"10.1016/j.sse.2025.109266","url":null,"abstract":"<div><div>Time-Dependent Dielectric Breakdown (TDDB) remains a critical reliability challenge in advanced CMOS technologies using thin <span><math><msub><mrow><mi>SiO</mi></mrow><mrow><mn>2</mn></mrow></msub></math></span>/High-k oxides. While extensive research focused on the formation of conductive filaments and the physics and statistics of soft breakdown and hard breakdown events, the intermediate wear-out phase — where a localized leakage path gradually increases in conductivity — has not been thoroughly analyzed or modeled. Firstly, this work addresses this gap by experimentally isolating and analyzing the wear-out phase with a Machine learning-assisted analysis, revealing key statistical features of wear-out and its dependence on stress voltage. Secondly, a Monte Carlo-implemented Markov model is used to simulate the localized degradation of a one-defect percolation path by means of a thermally activated defect creation and deactivation/annealing process, governed by an Arrhenius-like transition probability function. Simulations qualitatively reproduce the observed experimental degradation trends, with discrepancies in voltage dependence and initial defect accumulation, highlighting the need for a more nuanced approach, including statistical distributions of atomic bond strengths.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109266"},"PeriodicalIF":1.4,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-28DOI: 10.1016/j.sse.2025.109281
Jae Woog Jung , Jinho Park , Hyunwoo Kim
Forksheet FET (FSFET) is a promising candidate to replace the nanosheet FET (NSFET) for sub-3-nm technology nodes, offering further scalability. To realize FSFETs, a dielectric wall (DW) must be positioned between the NMOS and PMOS regions. However, the DW thickness (THKDW) has a significant influence on the electrical performance of FSFETs, including RC delay and power consumption. In this study, the effects of DW variation on FSFET performance were investigated using 3D TCAD simulations, focusing on RC delay and power characteristics. The DW thickness was varied from 5 nm to 25 nm with respect to the device width, and its influence on NMOS and PMOS characteristics and intrinsic RC delay was analyzed. The performance was further evaluated in terms of RC delay, operating frequency, and power using a CMOS inverter configuration. The results indicate that, at a constant active power, the RC delay continuously improves as THKDW decreases. However, considering practical DW process limitations, the impact of misalignment during FSFET fabrication was also analyzed. It was found that to retain optimal performance, the misalignment should be restricted to less than 3 nm, ensuring more than 95 % preservation of the original device functionality.
{"title":"Investigation on dielectric wall variations in Forksheet FETs","authors":"Jae Woog Jung , Jinho Park , Hyunwoo Kim","doi":"10.1016/j.sse.2025.109281","DOIUrl":"10.1016/j.sse.2025.109281","url":null,"abstract":"<div><div>Forksheet FET (FSFET) is a promising candidate to replace the nanosheet FET (NSFET) for sub-3-nm technology nodes, offering further scalability. To realize FSFETs, a dielectric wall (DW) must be positioned between the NMOS and PMOS regions. However, the DW thickness (<em>THK</em><sub>DW</sub>) has a significant influence on the electrical performance of FSFETs, including RC delay and power consumption. In this study, the effects of DW variation on FSFET performance were investigated using 3D TCAD simulations, focusing on RC delay and power characteristics. The DW thickness was varied from 5 nm to 25 nm with respect to the device width, and its influence on NMOS and PMOS characteristics and intrinsic RC delay was analyzed. The performance was further evaluated in terms of RC delay, operating frequency, and power using a CMOS inverter configuration. The results indicate that, at a constant active power, the RC delay continuously improves as <em>THK</em><sub>DW</sub> decreases. However, considering practical DW process limitations, the impact of misalignment during FSFET fabrication was also analyzed. It was found that to retain optimal performance, the misalignment should be restricted to less than 3 nm, ensuring more than 95 % preservation of the original device functionality.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109281"},"PeriodicalIF":1.4,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-28DOI: 10.1016/j.sse.2025.109265
Luigi Balestra , Simone Di Stasi , Elena Gnani , Susanna Reggiani , Mu-Yu Chen , Hiroshi Iwai , Edward Yi Chang
The performance of InGaAs based transistors can be significantly affected by the presence of interface traps, particularly in the subthreshold regime. In this study, the role of such defects has been investigated through the fabrication and the characterization of MOSCAP structures and nanosheet transistors. TCAD simulations have been used to extract interface-trap densities. Results reveal that the distributed defect tail into the bandgap is 5 × 1011 cm and degrades the subthreshold slope of about 39%, while interface traps inside the conduction band limit g to 561 S/m. The study emphasizes the need for improved interface engineering to unlock the full potential of nanoscale InGaAs-based devices.
{"title":"Impact of interface traps on the subthreshold performance of InGaAs nanosheet transistors","authors":"Luigi Balestra , Simone Di Stasi , Elena Gnani , Susanna Reggiani , Mu-Yu Chen , Hiroshi Iwai , Edward Yi Chang","doi":"10.1016/j.sse.2025.109265","DOIUrl":"10.1016/j.sse.2025.109265","url":null,"abstract":"<div><div>The performance of InGaAs based transistors can be significantly affected by the presence of interface traps, particularly in the subthreshold regime. In this study, the role of such defects has been investigated through the fabrication and the characterization of MOSCAP structures and nanosheet transistors. TCAD simulations have been used to extract interface-trap densities. Results reveal that the distributed defect tail into the bandgap is <span><math><mo>∼</mo></math></span>5 × 10<sup>11</sup> cm<span><math><mrow><msup><mrow></mrow><mrow><mo>−</mo><mn>2</mn></mrow></msup><mspace></mspace><msup><mrow><mi>eV</mi></mrow><mrow><mo>−</mo><mn>1</mn></mrow></msup></mrow></math></span> and degrades the subthreshold slope of about 39%, while interface traps inside the conduction band limit g<span><math><msubsup><mrow></mrow><mrow><mi>m</mi></mrow><mrow><mi>MAX</mi></mrow></msubsup></math></span> to 561 <span><math><mi>μ</mi></math></span>S/<span><math><mi>μ</mi></math></span>m. The study emphasizes the need for improved interface engineering to unlock the full potential of nanoscale InGaAs-based devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109265"},"PeriodicalIF":1.4,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-27DOI: 10.1016/j.sse.2025.109282
Rezwana Sultana, Karimul Islam, Robert Mroczyński
In this work, the temperature effect in dielectric, impedance, and leakage current characteristics of TiOx-incorporated HfOx (HTO) thin film integrated into metal–oxide–semiconductor (MOS) structure were investigated. The thin HTO layer was prepared using a pulsed-DC reactive magnetron sputtering technique. The successful preparation of HTO has been confirmed by analyzing the spectral profile of the refractive index. Energy dispersive X-ray analysis was employed to determine the elemental composition of the oxide film. The capacitance-frequency study of the Al/HTO/p-Si structure was carried out over a temperature range of 25 to 100 °C and a frequency range of 1 kHz to 3.5 MHz. The experimental results indicate that the dielectric constant, dielectric loss, and AC conductivity increase with rising temperature. Detailed impedance spectroscopy analysis reveals that the composite film follows a non-Debye type relaxation process signifying thermally activated dielectric relaxation and a reduced relaxation time with increasing temperature. The current–voltage characteristics demonstrated that the leakage current of the device increases with temperature, while exhibiting a nominal value within the measured temperature range. The findings underscore the influence of temperature on the dielectric, impedance, and leakage current properties of HTO films, providing key insights into enhancing the reliability of Al/HTO/p-Si MOS devices, particularly under high-temperature operation.
{"title":"Exploring temperature effects in dielectric and impedance spectroscopy of TiOx-Incorporated HfOx thin film","authors":"Rezwana Sultana, Karimul Islam, Robert Mroczyński","doi":"10.1016/j.sse.2025.109282","DOIUrl":"10.1016/j.sse.2025.109282","url":null,"abstract":"<div><div>In this work, the temperature effect in dielectric, impedance, and leakage current characteristics of TiO<sub>x</sub>-incorporated HfO<sub>x</sub> (HTO) thin film integrated into metal–oxide–semiconductor (MOS) structure were investigated. The thin HTO layer was prepared using a pulsed-DC reactive magnetron sputtering technique. The successful preparation of HTO has been confirmed by analyzing the spectral profile of the refractive index. Energy dispersive X-ray analysis was employed to determine the elemental composition of the oxide film. The capacitance-frequency study of the Al/HTO/<em>p</em>-Si structure was carried out over a temperature range of 25 to 100 °C and a frequency range of 1 kHz to 3.5 MHz. The experimental results indicate that the dielectric constant, dielectric loss, and AC conductivity increase with rising temperature. Detailed impedance spectroscopy analysis reveals that the composite film follows a non-Debye type relaxation process signifying thermally activated dielectric relaxation and a reduced relaxation time with increasing temperature. The current–voltage characteristics demonstrated that the leakage current of the device increases with temperature, while exhibiting a nominal value within the measured temperature range. The findings underscore the influence of temperature on the dielectric, impedance, and leakage current properties of HTO films, providing key insights into enhancing the reliability of Al/HTO/<em>p</em>-Si MOS devices, particularly under high-temperature operation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109282"},"PeriodicalIF":1.4,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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