Solid-state Electronics最新文献

英文中文

Markov model describing progressive degradation of local percolation path in thin oxides 描述薄氧化物局部渗透路径逐步退化的马尔可夫模型

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-28 DOI: 10.1016/j.sse.2025.109266

Sara Sacchi , Anirudh Varanasi , Robin Degraeve , Andrea Vici , Giorgio Molinaro , Jacopo Franco , Philippe Roussel , Ben Kaczer , Clement Merckling

Time-Dependent Dielectric Breakdown (TDDB) remains a critical reliability challenge in advanced CMOS technologies using thin

{SiO}_{2}

/High-k oxides. While extensive research focused on the formation of conductive filaments and the physics and statistics of soft breakdown and hard breakdown events, the intermediate wear-out phase — where a localized leakage path gradually increases in conductivity — has not been thoroughly analyzed or modeled. Firstly, this work addresses this gap by experimentally isolating and analyzing the wear-out phase with a Machine learning-assisted analysis, revealing key statistical features of wear-out and its dependence on stress voltage. Secondly, a Monte Carlo-implemented Markov model is used to simulate the localized degradation of a one-defect percolation path by means of a thermally activated defect creation and deactivation/annealing process, governed by an Arrhenius-like transition probability function. Simulations qualitatively reproduce the observed experimental degradation trends, with discrepancies in voltage dependence and initial defect accumulation, highlighting the need for a more nuanced approach, including statistical distributions of atomic bond strengths.

在使用薄SiO2/高k氧化物的先进CMOS技术中，时间相关介电击穿（TDDB）仍然是一个关键的可靠性挑战。虽然广泛的研究集中在导电细丝的形成以及软击穿和硬击穿事件的物理和统计上，但中间磨损阶段（局部泄漏路径逐渐增加电导率）尚未得到彻底的分析或建模。首先，这项工作通过实验隔离和分析磨损阶段，通过机器学习辅助分析，揭示磨损的关键统计特征及其对应力电压的依赖，解决了这一差距。其次，采用蒙特卡罗实现的马尔可夫模型，通过类似arrhenius的转移概率函数来控制热激活缺陷的产生和失活/退火过程，模拟单缺陷渗透路径的局部退化。模拟定性地再现了观察到的实验退化趋势，具有电压依赖性和初始缺陷积累的差异，强调需要更细致的方法，包括原子键强度的统计分布。

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引用次数: 0

Investigation on dielectric wall variations in Forksheet FETs 叉片场效应管介电壁变化的研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-28 DOI: 10.1016/j.sse.2025.109281

Jae Woog Jung , Jinho Park , Hyunwoo Kim

Forksheet FET (FSFET) is a promising candidate to replace the nanosheet FET (NSFET) for sub-3-nm technology nodes, offering further scalability. To realize FSFETs, a dielectric wall (DW) must be positioned between the NMOS and PMOS regions. However, the DW thickness (THK_DW) has a significant influence on the electrical performance of FSFETs, including RC delay and power consumption. In this study, the effects of DW variation on FSFET performance were investigated using 3D TCAD simulations, focusing on RC delay and power characteristics. The DW thickness was varied from 5 nm to 25 nm with respect to the device width, and its influence on NMOS and PMOS characteristics and intrinsic RC delay was analyzed. The performance was further evaluated in terms of RC delay, operating frequency, and power using a CMOS inverter configuration. The results indicate that, at a constant active power, the RC delay continuously improves as THK_DW decreases. However, considering practical DW process limitations, the impact of misalignment during FSFET fabrication was also analyzed. It was found that to retain optimal performance, the misalignment should be restricted to less than 3 nm, ensuring more than 95 % preservation of the original device functionality.

叉片FET （fset）是取代纳米片FET （NSFET）在亚3nm技术节点上的有前途的候选器件，具有进一步的可扩展性。为了实现fsfet，介电壁（DW）必须位于NMOS和PMOS区域之间。然而，DW厚度（THKDW）对fsfet的电学性能有显著影响，包括RC延迟和功耗。在本研究中，采用三维TCAD仿真研究了DW变化对fset性能的影响，重点研究了RC延迟和功率特性。DW厚度随器件宽度的变化范围为5 nm ~ 25 nm，分析了DW厚度对NMOS和PMOS特性及固有RC延迟的影响。使用CMOS逆变器配置，进一步评估了RC延迟、工作频率和功率方面的性能。结果表明，在一定有功功率下，随THKDW的减小，RC延迟不断提高。然而，考虑到实际DW工艺的限制，还分析了fset制造过程中不对准的影响。研究发现，为了保持最佳性能，不对准应限制在3 nm以下，以确保95% %以上的原始设备功能保留。

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引用次数: 0

Impact of interface traps on the subthreshold performance of InGaAs nanosheet transistors 界面陷阱对InGaAs纳米片晶体管亚阈值性能的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-28 DOI: 10.1016/j.sse.2025.109265

Luigi Balestra , Simone Di Stasi , Elena Gnani , Susanna Reggiani , Mu-Yu Chen , Hiroshi Iwai , Edward Yi Chang

The performance of InGaAs based transistors can be significantly affected by the presence of interface traps, particularly in the subthreshold regime. In this study, the role of such defects has been investigated through the fabrication and the characterization of MOSCAP structures and nanosheet transistors. TCAD simulations have been used to extract interface-trap densities. Results reveal that the distributed defect tail into the bandgap is

\sim

5 × 10¹¹ cm

^{- 2} {eV}^{- 1}

and degrades the subthreshold slope of about 39%, while interface traps inside the conduction band limit g

_{m}^{MAX}

to 561

μ

μ

m. The study emphasizes the need for improved interface engineering to unlock the full potential of nanoscale InGaAs-based devices.

基于InGaAs的晶体管的性能会受到界面陷阱的显著影响，特别是在亚阈值区域。在本研究中，通过MOSCAP结构和纳米片晶体管的制备和表征，研究了这些缺陷的作用。TCAD模拟已用于提取界面陷阱密度。结果表明，分布在带隙内的缺陷尾为~ 5 × 1011 cm−2eV−1，使亚阈值斜率降低约39%，而导带内的界面陷阱使gmMAX限制在561 μS/μm。该研究强调了改进界面工程的必要性，以释放基于ingaas的纳米级器件的全部潜力。

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引用次数: 0

Exploring temperature effects in dielectric and impedance spectroscopy of TiOx-Incorporated HfOx thin film 探讨含tiox - HfOx薄膜介电和阻抗谱的温度效应

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-27 DOI: 10.1016/j.sse.2025.109282

Rezwana Sultana, Karimul Islam, Robert Mroczyński

In this work, the temperature effect in dielectric, impedance, and leakage current characteristics of TiO_x-incorporated HfO_x (HTO) thin film integrated into metal–oxide–semiconductor (MOS) structure were investigated. The thin HTO layer was prepared using a pulsed-DC reactive magnetron sputtering technique. The successful preparation of HTO has been confirmed by analyzing the spectral profile of the refractive index. Energy dispersive X-ray analysis was employed to determine the elemental composition of the oxide film. The capacitance-frequency study of the Al/HTO/p-Si structure was carried out over a temperature range of 25 to 100 °C and a frequency range of 1 kHz to 3.5 MHz. The experimental results indicate that the dielectric constant, dielectric loss, and AC conductivity increase with rising temperature. Detailed impedance spectroscopy analysis reveals that the composite film follows a non-Debye type relaxation process signifying thermally activated dielectric relaxation and a reduced relaxation time with increasing temperature. The current–voltage characteristics demonstrated that the leakage current of the device increases with temperature, while exhibiting a nominal value within the measured temperature range. The findings underscore the influence of temperature on the dielectric, impedance, and leakage current properties of HTO films, providing key insights into enhancing the reliability of Al/HTO/p-Si MOS devices, particularly under high-temperature operation.

本文研究了温度对金属氧化物半导体（MOS）结构中含tiox的HfOx （HTO）薄膜介电、阻抗和漏电流特性的影响。采用脉冲直流反应磁控溅射技术制备了HTO薄层。通过对折射率谱图的分析，证实了HTO的成功制备。采用能量色散x射线分析方法测定了氧化膜的元素组成。Al/HTO/p-Si结构的电容频率研究在25 ~ 100℃的温度范围和1 kHz ~ 3.5 MHz的频率范围内进行。实验结果表明，介质常数、介质损耗和交流电导率随温度升高而增大。详细的阻抗谱分析表明，复合膜遵循非德拜型弛豫过程，表明热激活的介电弛豫和弛豫时间随温度的升高而减少。电流-电压特性表明，器件的泄漏电流随温度升高而增加，而在测量温度范围内呈现标称值。研究结果强调了温度对HTO薄膜介电、阻抗和漏电流特性的影响，为提高Al/HTO/p-Si MOS器件的可靠性，特别是在高温下的可靠性提供了关键的见解。

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引用次数: 0

Performance evaluation of SiC MOSFET-based converter for EV fast charging systems 基于SiC mosfet的电动汽车快速充电变换器性能评价

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-27 DOI: 10.1016/j.sse.2025.109286

Quoc Tuan Tran , Nguyen Phuong Tran

The deployment of fast-charging infrastructure for electric vehicles (EVs) demands power conversion systems that are compact, efficient, and capable of delivering high power. Silicon Carbide (SiC) MOSFETs offer substantial advantages over conventional Silicon (Si) devices, particularly in switching speed and thermal performance. This study evaluates AC–DC and DC–DC converters employing SiC MOSFETs for fast EV charging applications. Simulation analyses compare SiC-based designs with IGBT-based systems and examine multiple fast-charging topologies. The investigation, for different topologies of SiC converters, addresses losses, efficiency, total harmonic distortion (THD), control strategies, and ancillary services enabled by EVs, including voltage regulation, dynamic response, and vehicle-to-grid (V2G) functionality.

电动汽车快速充电基础设施的部署要求电力转换系统紧凑、高效、能够提供高功率。碳化硅（SiC） mosfet与传统硅（Si）器件相比具有实质性优势，特别是在开关速度和热性能方面。本研究评估了采用SiC mosfet的AC-DC和DC-DC转换器用于电动汽车快速充电的应用。仿真分析比较了基于sic的设计与基于igbt的系统，并检查了多种快速充电拓扑结构。针对不同拓扑结构的SiC转换器，研究了损耗、效率、总谐波失真（THD）、控制策略和电动汽车支持的辅助服务，包括电压调节、动态响应和车辆到电网（V2G）功能。

引用次数: 0

Exploring low-frequency noise dynamics in a-IGZO TFTs: Unveiling the impact of contact metal variations for advanced semiconductor applications 探索a-IGZO TFTs中的低频噪声动力学：揭示接触金属变化对先进半导体应用的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-26 DOI: 10.1016/j.sse.2025.109271

Junseong Park , Haesung Kim , Sung-Jin Choi , Dae Hwan Kim , Dong Myong Kim , Jong-Ho Bae

Amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs) are highly promising for applications such as embedded memory in CMOS BEOL 2T-DRAM due to their low leakage current and high field-effective mobility. This study systematically analyzes the a-IGZO TFTs, focusing on their low-frequency noise (LFN) characteristics with varying contact metals. We fabricated the staggered a-IGZO TFTs utilizing gate, source and drain metals with different work functions (Mo ∼ 4.6 eV and Pd ∼ 5.1 eV) to investigate the impact of electrode materials on device performance. The findings demonstrate distinct LFN characteristics influenced by the contact properties. Specifically, the device with Mo source and drain exhibits behavior consistent with carrier mobility fluctuation (CMF), while the device with Pd shows Schottky barrier height fluctuation in low current regions and carrier number fluctuation (CNF) in high current regions. This differentiation in noise characteristics is crucial for understanding and optimizing the device operation mechanism, performance and reliability in advanced memory applications. The result highlights the importance of selecting appropriate contact materials to minimize noise and enhance device performance, providing valuable insights for the design and development of high-performance a-IGZO TFT-based memory technologies.

非晶铟镓锌氧化物（a-IGZO）薄膜晶体管（TFTs）由于其低泄漏电流和高场有效迁移率，在CMOS BEOL 2T-DRAM的嵌入式存储器等应用中具有很高的应用前景。本研究系统地分析了a-IGZO tft，重点研究了其在不同接触金属下的低频噪声特性。我们利用具有不同功函数（Mo ~ 4.6 eV和Pd ~ 5.1 eV）的栅极、源极和漏极金属制作了交错的a-IGZO TFTs，以研究电极材料对器件性能的影响。研究结果表明，不同的LFN特性受接触特性的影响。具体而言，含Mo源极和漏极的器件表现出与载流子迁移率波动（CMF）一致的行为，而含Pd的器件在低电流区表现出肖特基势垒高度波动，在高电流区表现出载流子数波动（CNF）。这种噪声特性的差异对于理解和优化先进存储器应用中的器件操作机制、性能和可靠性至关重要。该结果强调了选择合适的触点材料以最小化噪声和提高器件性能的重要性，为高性能a-IGZO tft存储技术的设计和开发提供了有价值的见解。

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引用次数: 0

Traps and radio-frequency characterization of polysilicon layer on high resistivity silicon substrate 高电阻率硅衬底上多晶硅层的陷阱和射频特性

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-25 DOI: 10.1016/j.sse.2025.109269

Eric Vandermolen , Philippe Ferrandis , Frédéric Allibert , Emmanuel Augendre , Massinissa Nabet , Martin Rack , Jean-Pierre Raskin , Mikaël Cassé

In this work, radio-frequency and traps properties of unintentionally doped polycrystalline silicon (polySi) deposited by low pressure chemical vapor deposition (LPCVD) on high resistivity silicon (HR-Si) substrate are characterized. Both volume (i.e. inside polySi) and interface traps (i.e. near polySi/HR-Si) are detected by photo-induced current transient spectroscopy (PICTS). A thermal budget of 900 °C during 2 h is sufficient to observe trap densities reduction near the polySi/HR-Si interface, affecting the RF performance of the fabricated substrates.

在这项工作中，通过低压化学气相沉积（LPCVD）在高电阻率硅（r - si）衬底上沉积无意掺杂多晶硅（polySi）的射频和陷阱特性进行了表征。通过光致电流瞬态光谱（PICTS）检测体积（即多晶硅内部）和界面陷阱（即多晶硅/HR-Si附近）。900°C的热收支在2小时内足以观察到聚硅/HR-Si界面附近的陷阱密度降低，影响了制备基板的射频性能。

引用次数: 0

Modeling of RRAM based PUF: a case study 基于RRAM的PUF建模：一个案例研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-21 DOI: 10.1016/j.sse.2025.109267

Kamil Ber , Piotr Wiśniewski

This work presents the modeling and analysis of PUFs based on Resistive Random-Access Memory (RRAM) devices. Empirical data is utilized to identify statistical distributions that best replicate the stochastic nature of RRAM cells. Parameters for random variables simulating SET/RESET voltages and Low/High Resistance State (LRS/HRS) currents are extracted from current-voltage (I-V) measurements. This simplified behavioral model is subsequently used to evaluate the potential of a given manufacturing technology as a basis for developing energy-efficient hardware PUFs [1,2].

这项工作提出了基于电阻随机存取存储器（RRAM）器件的puf的建模和分析。利用经验数据来确定统计分布，最好地复制随机存储器细胞的随机性。模拟SET/RESET电压和低/高阻状态（LRS/HRS）电流的随机变量参数从电流-电压（I-V）测量中提取。这个简化的行为模型随后被用来评估给定制造技术的潜力，作为开发节能硬件puf的基础[1,2]。

引用次数: 0

Pursuing the FD-SOI roadmap down to 10 nm and 7 nm nodes for high energy efficient, low power and RF/mmWave applications 追求FD-SOI路线图至10 nm和7 nm节点，用于高能效，低功耗和RF/毫米波应用

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-11 DOI: 10.1016/j.sse.2025.109264

C. Fenouillet-Beranger, O. Rozeau, R. Chouk, O. Cueto, A-S. Royet, M. Charbonneau, B. Mohamad, L. Brévard, Z. Chalupa, A. Bond, F. Baudin, L. Brunet, P. Rodriguez, R. Gassilloud, T. Mota-Frutuoso, P. Pimenta-Barros, S. Beaurepaire, V. Lapras, J. Kanyandekwe, E. Petitprez, D. Noguet

This paper will review the device specifications and the key technological boosters that are targeted in view of pursuing the FD-SOI roadmap down to the 10 nm and 7 nm nodes. In order to achieve the electrical specifications for both 10 nm and 7 nm FD-SOI devices the mobility improvement is key. Thanks to the combination of global (at wafer level) and local strain boosters (at device level), the reduction of parasitic (by introduction of low-k spacers) and two original technological options for design flexibility, the targeted performances should be reached.

本文将回顾器件规格和关键技术助推器的目标，以追求FD-SOI路线图到10纳米和7纳米节点。为了达到10nm和7nm FD-SOI器件的电气规格，提高迁移率是关键。由于结合了全局（晶圆级）和局部应变增强器（器件级），减少了寄生（通过引入低k间隔器）和两种设计灵活性的原始技术选择，应该可以达到目标性能。

引用次数: 0

Interpretation of electrical instability for polycrystalline silicon vertical TFT 多晶硅垂直TFT的电不稳定性解释

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-11 DOI: 10.1016/j.sse.2025.109263

Peng Zhang , Emmanuel Jacques , Régis Rogel , Laurent Pichon , Olivier Bonnaud

Due to its excellent electrical performance and compatibility with CMOS processing, polycrystalline silicon TFT has been applied in AMOLED display backplane. As short channel length can potentially benefit current density and cutoff frequency, polycrystalline silicon vertical TFT can be applied in conventional 2-transistor and 1-capcitor (2T1C) pixel unit. The fabrication of polycrystalline silicon vertical TFT was introduced, and the electrical characteristics of the fabricated device was demonstrated. Thereafter, the electrical parameters of the vertical TFT were analyzed and compared under different electrical stress durations, which interprets the inherent mechanism of the stress instability. The total density of states (DOS) and interface DOS of the fabricated devices also indicate that the stress instability is due to charge trapping in gate dielectric layer. The electrical instability is simulated by using high-k gate dielectric layer, and the reduced electrical field in the gate dielectric layer can potentially improve the electrical stability. Finally, 2T1C configuration of AMOLED pixel unit shows the influence of gate dielectric layer on the stress stability, the TFTs with high-k gate dielectric layer shows higher stress stability and lower error rate of OLED current.

多晶硅TFT由于其优异的电性能和与CMOS工艺的兼容性，已被应用于AMOLED显示背板。由于通道长度较短可能有利于电流密度和截止频率，多晶硅垂直TFT可以应用于传统的2晶体管和1电容（2T1C）像素单元。介绍了多晶硅垂直TFT器件的制备方法，并对其电学特性进行了验证。分析比较了不同电应力持续时间下垂直TFT的电参数，揭示了应力失稳的内在机理。制备器件的总态密度（DOS）和界面DOS也表明应力不稳定性是由于栅极介电层中的电荷捕获引起的。采用高k栅极介电层模拟了栅极介电层的电不稳定性，表明栅极介电层电场的减小可以潜在地提高电稳定性。最后，AMOLED像素单元的2T1C配置显示了栅极介电层对应力稳定性的影响，具有高k栅极介电层的tft具有更高的应力稳定性和更低的OLED电流错误率。

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