Pub Date : 2025-12-04DOI: 10.1016/j.sse.2025.109296
Alan Blumenstein , Eduardo Pérez , Christian Wenger , Nadine Dersch , Alexander Kloes , Benjamín Iñíguez , Mike Schwarz
This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network’s robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.
{"title":"Exploring variability and quantization effects in artificial neural networks using the MNIST dataset","authors":"Alan Blumenstein , Eduardo Pérez , Christian Wenger , Nadine Dersch , Alexander Kloes , Benjamín Iñíguez , Mike Schwarz","doi":"10.1016/j.sse.2025.109296","DOIUrl":"10.1016/j.sse.2025.109296","url":null,"abstract":"<div><div>This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network’s robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109296"},"PeriodicalIF":1.4,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.sse.2025.109312
Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky
This paper reports on progress in cryogenic magnetic field sensing using vortex magnetic tunnel junctions (MTJs) at T < 10 K. The MTJ magnetoresistive signal is amplified using a wire-bonded foundry-fabricated 180 nm-process cryo-CMOS sense amplifier, providing ∼ 100 mG single-shot detectivity. Functional MTJ sensor deposition results on a true CMOS surface with fill exclusion are also presented. The aim is to make a magnetic field camera for tracking flux vortex motion in superconducting films, leading to optimized VLSI superconducting electronic (SCE) circuitry.
{"title":"Progress towards integration of MTJ devices with cryo-CMOS readout circuitry for magnetic field sensing","authors":"Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky","doi":"10.1016/j.sse.2025.109312","DOIUrl":"10.1016/j.sse.2025.109312","url":null,"abstract":"<div><div>This paper reports on progress in cryogenic magnetic field sensing using vortex magnetic tunnel junctions (MTJs) at <em>T</em> < 10 K. The MTJ magnetoresistive signal is amplified using a wire-bonded foundry-fabricated 180 nm-process cryo-CMOS sense amplifier, providing ∼ 100 mG single-shot detectivity. Functional MTJ sensor deposition results on a true CMOS surface with fill exclusion are also presented. The aim is to make a magnetic field camera for tracking flux vortex motion in superconducting films, leading to optimized VLSI superconducting electronic (SCE) circuitry.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109312"},"PeriodicalIF":1.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.sse.2025.109311
Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu
In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage (I-V) characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity (R) and detectability (D*) values of the photodiode were measured as 2.9 mA/W and 1.95 × 1013 Jones, respectively, at an illumination intensity of 80 mW/cm2. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.
{"title":"Design, Synthesis, and Optoelectronic Characterization of a Novel Cu(II) Complex-Based Photodiode with Prof. Dr. Yakuphanoglu’s Advanced Fytronix Solar Simulator Characterization Techniques","authors":"Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu","doi":"10.1016/j.sse.2025.109311","DOIUrl":"10.1016/j.sse.2025.109311","url":null,"abstract":"<div><div>In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage <em>(I-V)</em> characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity <em>(R)</em> and detectability <em>(D*)</em> values of the photodiode were measured as 2.9 mA/W and 1.95 × 10<sup>13</sup> Jones, respectively, at an illumination intensity of 80 mW/cm<sup>2</sup>. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109311"},"PeriodicalIF":1.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145842278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-30DOI: 10.1016/j.sse.2025.109305
Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria
This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (VGS) at a low drain-to-source voltage (VDS) to observe its direct effect on the current noise spectral density (Sid), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The Sid extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing Sid with higher VGS, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct Sid trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).
{"title":"Evaluation of a single interface trap position on the low-frequency noise of junctionless nanowire transistors","authors":"Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria","doi":"10.1016/j.sse.2025.109305","DOIUrl":"10.1016/j.sse.2025.109305","url":null,"abstract":"<div><div>This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (<em>V<sub>GS</sub></em>) at a low drain-to-source voltage (<em>V<sub>DS</sub></em>) to observe its direct effect on the current noise spectral density (<em>S<sub>id</sub></em>), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The <em>S<sub>id</sub></em> extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing S<sub>id</sub> with higher V<sub>GS</sub>, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct <em>S<sub>id</sub></em> trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109305"},"PeriodicalIF":1.4,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-30DOI: 10.1016/j.sse.2025.109307
D. Barge , M. Gallard , J.-M. Hartmann , F. Fournel , V. Loup , F. Mazen , E. Nolot , P. Hauchecorne , J. Sturm , V.H. Le , I. Huyet , D. Delprat , F. Boedt , F. Servant
This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.
{"title":"300 Mm sSOI engineering with ultra thin buried oxide","authors":"D. Barge , M. Gallard , J.-M. Hartmann , F. Fournel , V. Loup , F. Mazen , E. Nolot , P. Hauchecorne , J. Sturm , V.H. Le , I. Huyet , D. Delprat , F. Boedt , F. Servant","doi":"10.1016/j.sse.2025.109307","DOIUrl":"10.1016/j.sse.2025.109307","url":null,"abstract":"<div><div>This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109307"},"PeriodicalIF":1.4,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work employs a two-stage low temperature defect reduction annealing treatment for oxidation state modulation and defect reduction of stannous oxide (SnO) thin-film transistors (TFTs). With higher Sn2+ proportion and fewer defects, the device stability and carrier mobility of p-type SnO TFTs are improved. The SnO TFTs with two-stage low temperature defect reduction annealing exhibit an on/off ratio of 1.22 × 104, a field-effect mobility of 0.44 cm2/V·s, a 50.2 % reduction in IOFF, without subthreshold swing degradation. With the detailed material analysis, the internal physical mechanism of the defect reduction in of SnO is well discussed. The discoveries presented in this work are expected to provide technical methodologies for the high-performance TFTs.
{"title":"Oxidation state modulation for p-Type stannous oxide with Two-Stage low temperature defect reduction annealing","authors":"Zhibo Zeng , Kai-Jhih Gan , Wenjie Lei , Shiyu Zeng , Jialong Xiang , Bojun Zhang , Kuei-Shu Chang-Liao , Cheng-Chang Yu , Po-Chung Huang , Dun-Bao Ruan","doi":"10.1016/j.sse.2025.109308","DOIUrl":"10.1016/j.sse.2025.109308","url":null,"abstract":"<div><div>This work employs a two-stage low temperature defect reduction annealing treatment for oxidation state modulation and defect reduction of stannous oxide (SnO) thin-film transistors (TFTs). With higher Sn<sup>2+</sup> proportion and fewer defects, the device stability and carrier mobility of p-type SnO TFTs are improved. The SnO TFTs with two-stage low temperature defect reduction annealing exhibit an on/off ratio of 1.22 × 10<sup>4</sup>, a field-effect mobility of 0.44 cm<sup>2</sup>/V·s, a 50.2 % reduction in I<sub>OFF</sub>, without subthreshold swing degradation. With the detailed material analysis, the internal physical mechanism of the defect reduction in of SnO is well discussed. The discoveries presented in this work are expected to provide technical methodologies for the high-performance TFTs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109308"},"PeriodicalIF":1.4,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145652096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-29DOI: 10.1016/j.sse.2025.109295
Bogdan Majkusiak
A computational model of probability of tunneling through Schottky barrier, based on the transfer matrix method, is presented and used for a quantitative study of tunneling probability and tunnel current at comparison to the over-barrier transitions for various parameters of Al-SiO2-Si(n) material system. It is proved that tunneling through Schottky barrier can significantly contribute to the total current even at moderate doping levels, especially if the insulator layer is very thin.
{"title":"Modeling of tunneling through Schottky barriers","authors":"Bogdan Majkusiak","doi":"10.1016/j.sse.2025.109295","DOIUrl":"10.1016/j.sse.2025.109295","url":null,"abstract":"<div><div>A computational model of probability of tunneling through Schottky barrier, based on the transfer matrix method, is presented and used for a quantitative study of tunneling probability and tunnel current at comparison to the over-barrier transitions for various parameters of Al-SiO<sub>2</sub>-Si(n) material system. It is proved that tunneling through Schottky barrier can significantly contribute to the total current even at moderate doping levels, especially if the insulator layer is very thin.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109295"},"PeriodicalIF":1.4,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145652095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1016/j.sse.2025.109284
Tomáš Hadámek , Viktor Sverdlov
A fully 3D model coupling spin, charge, magnetization, and temperature dynamics has been employed to study the two-terminal spin–orbit-torque magnetoresistive random-access memory (2T-SOT-MRAM). To account for heating from tunneling electrons, we applied an asymmetric heating model near the tunnel barrier, revealing that symmetric model can underestimate free layer temperature increase by over 25%. We further employ the model to simulate switching of the 2T-SOT-MRAM under different voltage pulse shapes and show that the pulse-shaping strategies can not only reduce power consumption by more than 30%, but also significantly reduce peak temperature of the device during writing.
{"title":"Temperature modeling and pulse shaping strategies for energy optimization in 2T-SOT-MRAM","authors":"Tomáš Hadámek , Viktor Sverdlov","doi":"10.1016/j.sse.2025.109284","DOIUrl":"10.1016/j.sse.2025.109284","url":null,"abstract":"<div><div>A fully 3D model coupling spin, charge, magnetization, and temperature dynamics has been employed to study the two-terminal spin–orbit-torque magnetoresistive random-access memory (2T-SOT-MRAM). To account for heating from tunneling electrons, we applied an asymmetric heating model near the tunnel barrier, revealing that symmetric model can underestimate free layer temperature increase by over 25%. We further employ the model to simulate switching of the 2T-SOT-MRAM under different voltage pulse shapes and show that the pulse-shaping strategies can not only reduce power consumption by more than 30%, but also significantly reduce peak temperature of the device during writing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109284"},"PeriodicalIF":1.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-19DOI: 10.1016/j.sse.2025.109294
H. García , G. Vinuesa , T.del Val , K. Kalam , M.B. González , F. Campabadal , S. Dueñas , H. Castán
Memristors have drawn interest due to their use as artificial synapses in neuromorphic circuits. This work investigates the multilevel conductance modulation in Al2O3 and HfO2-based memristors. Specifically, the control of the depression or reset transition when applying identical consecutive voltage pulses was the main objective. Both pulse amplitude and pulse accumulated time can control the reset transition. Voltage required to reset the device is higher for Al2O3, which can lead to higher energy consumption. However, this material showed better reset transition linearity.
{"title":"Multilevel conductance modulation in HfO2, Al2O3, and HfO2/Al2O3 bilayer memristors","authors":"H. García , G. Vinuesa , T.del Val , K. Kalam , M.B. González , F. Campabadal , S. Dueñas , H. Castán","doi":"10.1016/j.sse.2025.109294","DOIUrl":"10.1016/j.sse.2025.109294","url":null,"abstract":"<div><div>Memristors have drawn interest due to their use as artificial synapses in neuromorphic circuits. This work investigates the multilevel conductance modulation in Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub>-based memristors. Specifically, the control of the depression or reset transition when applying identical consecutive voltage pulses was the main objective. Both pulse amplitude and pulse accumulated time can control the reset transition. Voltage required to reset the device is higher for Al<sub>2</sub>O<sub>3</sub>, which can lead to higher energy consumption. However, this material showed better reset transition linearity.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109294"},"PeriodicalIF":1.4,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-15DOI: 10.1016/j.sse.2025.109293
M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska
This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.
{"title":"Effect of PN passivation on MOSFETs performance in 28 nm FD-SOI","authors":"M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska","doi":"10.1016/j.sse.2025.109293","DOIUrl":"10.1016/j.sse.2025.109293","url":null,"abstract":"<div><div>This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109293"},"PeriodicalIF":1.4,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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