Pub Date : 2026-04-01Epub Date: 2026-01-01DOI: 10.1016/j.sse.2025.109330
Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi
This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/ID of 5, 8 and 11 V−1. The experimental n-type forksheet used in this work presents a sheet thickness of HFS = 7 nm, sheet width of WFS = 23 nm and a transistor channel length of LG = 70 nm. When the gm/ID increases from 5 to 11 V−1, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/ID) from 49 dB to 63 dB, the total power dissipation (Power ∝ ID) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.
{"title":"Application of forksheet transistor in operational transconductance amplifier","authors":"Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi","doi":"10.1016/j.sse.2025.109330","DOIUrl":"10.1016/j.sse.2025.109330","url":null,"abstract":"<div><div>This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/I<sub>D</sub> of 5, 8 and 11 V<sup>−1</sup>. The experimental n-type forksheet used in this work presents a sheet thickness of H<sub>FS</sub> = 7 nm, sheet width of W<sub>FS</sub> = 23 nm and a transistor channel length of L<sub>G</sub> = 70 nm. When the gm/I<sub>D</sub> increases from 5 to 11 V<sup>−1</sup>, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/I<sub>D</sub>) from 49 dB to 63 dB, the total power dissipation (Power ∝ I<sub>D</sub>) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109330"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-04-01Epub Date: 2025-12-02DOI: 10.1016/j.sse.2025.109311
Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu
In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage (I-V) characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity (R) and detectability (D*) values of the photodiode were measured as 2.9 mA/W and 1.95 × 1013 Jones, respectively, at an illumination intensity of 80 mW/cm2. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.
{"title":"Design, Synthesis, and Optoelectronic Characterization of a Novel Cu(II) Complex-Based Photodiode with Prof. Dr. Yakuphanoglu’s Advanced Fytronix Solar Simulator Characterization Techniques","authors":"Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu","doi":"10.1016/j.sse.2025.109311","DOIUrl":"10.1016/j.sse.2025.109311","url":null,"abstract":"<div><div>In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage <em>(I-V)</em> characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity <em>(R)</em> and detectability <em>(D*)</em> values of the photodiode were measured as 2.9 mA/W and 1.95 × 10<sup>13</sup> Jones, respectively, at an illumination intensity of 80 mW/cm<sup>2</sup>. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109311"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145842278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-04-01Epub Date: 2026-01-11DOI: 10.1016/j.sse.2026.109332
Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick
This study investigates the short-term (µs to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries’ 28 nm bulk high-k metal gate (HKMG) technology.
Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection.
A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain.
Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive.
The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.
{"title":"Short-term charge trapping effects in ferroelectric FETs: impact of pulse amplitude and timing","authors":"Dominik Kleimaier , Stefan Dünkel , Halid Mulaosmanovic , Johannes Müller , Sven Beyer , Viktor Havel , Thomas Mikolajick","doi":"10.1016/j.sse.2026.109332","DOIUrl":"10.1016/j.sse.2026.109332","url":null,"abstract":"<div><div>This study investigates the short-term (µs to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries’ 28 <!--> <!-->nm bulk high-k metal gate (HKMG) technology.</div><div>Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection.</div><div>A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain.</div><div>Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive.</div><div>The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109332"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-04-01Epub Date: 2025-12-30DOI: 10.1016/j.sse.2025.109326
Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li
Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (PVE) and intrinsic parameter fluctuations (IPF). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (TNS), width (WNS), and gate length (LG)—play a pivotal role in shaping intrinsic resistance (ro), output resistance (Rout), voltage gain (AV), cut-off frequency (fT), and 3-dB bandwidth (f3dB), due to their influence on surface potential profiles and carrier transport behavior. Notably, within IPF, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (WKF) strongly perturb the channel surface potential, thereby inducing significant variability in AV, fT, f3dB, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of PVE and IPF. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.
栅极全能（GAA）硅纳米片互补场效应晶体管（cfet）的可变性主要来自两个方面：工艺变化效应（PVE）和内在参数波动（IPF）。在这项工作中，开发了一个系统的基于tcad的可变性框架，以定量评估PVE和IPF对垂直堆叠GAA Si NS cfet模拟和射频（RF）性能的影响。关键的几何因素-即NS厚度（TNS），宽度（WNS）和栅极长度(LG) -由于其对表面电位分布和载流子输运行为的影响，在形成固有电阻（ro），输出电阻（route），电压增益（AV），截止频率（fT）和3db带宽（f3dB）中起关键作用。值得注意的是，在IPF中，变化主要由随机纳米级金属颗粒控制，其中功函数波动（WKF）强烈干扰通道表面电位，从而诱导AV、fT、f3dB和其他射频参数的显著变化。采用统计上显著的校准设备模拟集合来解耦和量化PVE和IPF的单独和联合贡献。此外，还进行了小信号s参数分析，以提取实际负载条件下的RF值，为可变感知的CFET优化提供实用的设计见解。
{"title":"Radio-frequency variability of GAA Si NS CFETs induced by PVE and IPF simultaneously","authors":"Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li","doi":"10.1016/j.sse.2025.109326","DOIUrl":"10.1016/j.sse.2025.109326","url":null,"abstract":"<div><div>Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (<em>PVE</em>) and intrinsic parameter fluctuations (<em>IPF</em>). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (<em>T<sub>NS</sub></em>), width (<em>W<sub>NS</sub></em>), and gate length (<em>L<sub>G</sub></em>)—play a pivotal role in shaping intrinsic resistance (<em>r<sub>o</sub></em>), output resistance (<em>R<sub>out</sub></em>), voltage gain (<em>A<sub>V</sub></em>), cut-off frequency (<em>f<sub>T</sub></em>), and 3-dB bandwidth (<em>f</em><sub>3</sub><em><sub>dB</sub></em>), due to their influence on surface potential profiles and carrier transport behavior. Notably, within <em>IPF</em>, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (<em>WKF</em>) strongly perturb the channel surface potential, thereby inducing significant variability in <em>A<sub>V</sub></em>, <em>f<sub>T</sub></em>, <em>f</em><sub>3</sub><em><sub>dB</sub></em>, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of <em>PVE</em> and <em>IPF</em>. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109326"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-04-01Epub Date: 2026-01-20DOI: 10.1016/j.sse.2026.109334
Haruki Yoshida, Takashi Onaya, Atsushi Tamura, Koji Kita
Thermal nitridation is the most common method for SiC surface defect passivation by introducing nitrogen on the surface, however, the nitridation process using active species such as N-radicals is one of the possible alternatives. This study investigated the kinetics of nitridation on SiC surface by N-radicals and compared them with those of thermal nitridation. Both processes showed a saturation of surface N density after prolonged nitridation, which is explainable by considering the competition between N-incorporation and N-desorption. N-desorption is driven by surface oxidation in the case of thermal nitridation, whereas it is caused by a heating in a high vacuum environment in the case of N-radical nitridation. In addition, N-incorporation rate reduction due to the depletion of surface reactive sites as surface N density increases must be taken into account in the case of radical nitridation.
{"title":"Difference in kinetics between thermal nitridation and radical nitridation processes of 4H-SiC surface considering simultaneous N-incorporation and N-desorption reactions","authors":"Haruki Yoshida, Takashi Onaya, Atsushi Tamura, Koji Kita","doi":"10.1016/j.sse.2026.109334","DOIUrl":"10.1016/j.sse.2026.109334","url":null,"abstract":"<div><div>Thermal nitridation is the most common method for SiC surface defect passivation by introducing nitrogen on the surface, however, the nitridation process using active species such as N-radicals is one of the possible alternatives. This study investigated the kinetics of nitridation on SiC surface by N-radicals and compared them with those of thermal nitridation. Both processes showed a saturation of surface N density after prolonged nitridation, which is explainable by considering the competition between N-incorporation and N-desorption. N-desorption is driven by surface oxidation in the case of thermal nitridation, whereas it is caused by a heating in a high vacuum environment in the case of N-radical nitridation. In addition, N-incorporation rate reduction due to the depletion of surface reactive sites as surface N density increases must be taken into account in the case of radical nitridation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109334"},"PeriodicalIF":1.4,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146023139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-11-29DOI: 10.1016/j.sse.2025.109295
Bogdan Majkusiak
A computational model of probability of tunneling through Schottky barrier, based on the transfer matrix method, is presented and used for a quantitative study of tunneling probability and tunnel current at comparison to the over-barrier transitions for various parameters of Al-SiO2-Si(n) material system. It is proved that tunneling through Schottky barrier can significantly contribute to the total current even at moderate doping levels, especially if the insulator layer is very thin.
{"title":"Modeling of tunneling through Schottky barriers","authors":"Bogdan Majkusiak","doi":"10.1016/j.sse.2025.109295","DOIUrl":"10.1016/j.sse.2025.109295","url":null,"abstract":"<div><div>A computational model of probability of tunneling through Schottky barrier, based on the transfer matrix method, is presented and used for a quantitative study of tunneling probability and tunnel current at comparison to the over-barrier transitions for various parameters of Al-SiO<sub>2</sub>-Si(n) material system. It is proved that tunneling through Schottky barrier can significantly contribute to the total current even at moderate doping levels, especially if the insulator layer is very thin.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109295"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145652095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-11-30DOI: 10.1016/j.sse.2025.109305
Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria
This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (VGS) at a low drain-to-source voltage (VDS) to observe its direct effect on the current noise spectral density (Sid), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The Sid extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing Sid with higher VGS, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct Sid trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).
{"title":"Evaluation of a single interface trap position on the low-frequency noise of junctionless nanowire transistors","authors":"Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria","doi":"10.1016/j.sse.2025.109305","DOIUrl":"10.1016/j.sse.2025.109305","url":null,"abstract":"<div><div>This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (<em>V<sub>GS</sub></em>) at a low drain-to-source voltage (<em>V<sub>DS</sub></em>) to observe its direct effect on the current noise spectral density (<em>S<sub>id</sub></em>), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The <em>S<sub>id</sub></em> extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing S<sub>id</sub> with higher V<sub>GS</sub>, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct <em>S<sub>id</sub></em> trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109305"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-08DOI: 10.1016/j.sse.2025.109314
Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang
Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.
{"title":"Improving the analog switching behavior in HfO2-based RRAM with simple 1T1R structure configuration","authors":"Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang","doi":"10.1016/j.sse.2025.109314","DOIUrl":"10.1016/j.sse.2025.109314","url":null,"abstract":"<div><div>Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109314"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-02DOI: 10.1016/j.sse.2025.109312
Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky
This paper reports on progress in cryogenic magnetic field sensing using vortex magnetic tunnel junctions (MTJs) at T < 10 K. The MTJ magnetoresistive signal is amplified using a wire-bonded foundry-fabricated 180 nm-process cryo-CMOS sense amplifier, providing ∼ 100 mG single-shot detectivity. Functional MTJ sensor deposition results on a true CMOS surface with fill exclusion are also presented. The aim is to make a magnetic field camera for tracking flux vortex motion in superconducting films, leading to optimized VLSI superconducting electronic (SCE) circuitry.
{"title":"Progress towards integration of MTJ devices with cryo-CMOS readout circuitry for magnetic field sensing","authors":"Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky","doi":"10.1016/j.sse.2025.109312","DOIUrl":"10.1016/j.sse.2025.109312","url":null,"abstract":"<div><div>This paper reports on progress in cryogenic magnetic field sensing using vortex magnetic tunnel junctions (MTJs) at <em>T</em> < 10 K. The MTJ magnetoresistive signal is amplified using a wire-bonded foundry-fabricated 180 nm-process cryo-CMOS sense amplifier, providing ∼ 100 mG single-shot detectivity. Functional MTJ sensor deposition results on a true CMOS surface with fill exclusion are also presented. The aim is to make a magnetic field camera for tracking flux vortex motion in superconducting films, leading to optimized VLSI superconducting electronic (SCE) circuitry.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109312"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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