Pub Date : 2026-01-01DOI: 10.1016/j.sse.2025.109329
Karimul Islam , Rezwana Sultana , Aleksandra Dzięgielewska , Robert Mroczyński
This study investigates the influence of the top metal electrode on the resistive switching (RS) behavior of the metal/TiOx/ITO structure. Specifically, the effects of Al and TiN as top electrodes were examined in devices utilizing a 30 nm TiOx thin film as the active layer, deposited using a pulsed-DC reactive sputtering technique. Both configurations exhibited non-volatile bipolar resistive switching, demonstrating endurance over 100 cycles and stable data retention (>104 s). The results indicate that the choice of top electrode (TE) plays a crucial role in determining the electroforming process, current conduction mechanisms, and overall RS performance. Notably, devices with TiN as a TE exhibited more consistent RS behavior, with a superior ON/OFF ratio and enhanced operational stability. These findings demonstrate that electrode engineering offers a viable pathway to enhance resistive switching performance. The insights gained from this study provide a basis for the rational design and optimization of CMOS-compatible TiOx-based resistive random-access memory (RRAM) devices.
{"title":"Impact of top electrode materials on resistive switching characteristics of TiOx-based MIM structures","authors":"Karimul Islam , Rezwana Sultana , Aleksandra Dzięgielewska , Robert Mroczyński","doi":"10.1016/j.sse.2025.109329","DOIUrl":"10.1016/j.sse.2025.109329","url":null,"abstract":"<div><div>This study investigates the influence of the top metal electrode on the resistive switching (RS) behavior of the metal/TiO<sub>x</sub>/ITO structure. Specifically, the effects of Al and TiN as top electrodes were examined in devices utilizing a 30 nm TiO<sub>x</sub> thin film as the active layer, deposited using a pulsed-DC reactive sputtering technique. Both configurations exhibited non-volatile bipolar resistive switching, demonstrating endurance over 100 cycles and stable data retention (>10<sup>4</sup> s). The results indicate that the choice of top electrode (TE) plays a crucial role in determining the electroforming process, current conduction mechanisms, and overall RS performance. Notably, devices with TiN as a TE exhibited more consistent RS behavior, with a superior ON/OFF ratio and enhanced operational stability. These findings demonstrate that electrode engineering offers a viable pathway to enhance resistive switching performance. The insights gained from this study provide a basis for the rational design and optimization of CMOS-compatible TiO<sub>x</sub>-based resistive random-access memory (RRAM) devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109329"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01DOI: 10.1016/j.sse.2025.109330
Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi
This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/ID of 5, 8 and 11 V−1. The experimental n-type forksheet used in this work presents a sheet thickness of HFS = 7 nm, sheet width of WFS = 23 nm and a transistor channel length of LG = 70 nm. When the gm/ID increases from 5 to 11 V−1, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/ID) from 49 dB to 63 dB, the total power dissipation (Power ∝ ID) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.
{"title":"Application of forksheet transistor in operational transconductance amplifier","authors":"Joao Antonio Martino , Julius Andretti Peixoto Pires de Paula , Paula Ghedini Der Agopian , Romain Ritzenthaler , Hans Mertens , Anabela Veloso , Naoto Horiguchi","doi":"10.1016/j.sse.2025.109330","DOIUrl":"10.1016/j.sse.2025.109330","url":null,"abstract":"<div><div>This work presents, for the first time, experimental data on forksheet transistor used in the design of operational transconductance amplifiers (OTA), highlighting their potential for application in analog circuits. The OTA was designed for three different transistor efficiencies: gm/I<sub>D</sub> of 5, 8 and 11 V<sup>−1</sup>. The experimental n-type forksheet used in this work presents a sheet thickness of H<sub>FS</sub> = 7 nm, sheet width of W<sub>FS</sub> = 23 nm and a transistor channel length of L<sub>G</sub> = 70 nm. When the gm/I<sub>D</sub> increases from 5 to 11 V<sup>−1</sup>, the drain current and the transconductance decrease, which improves the OTA voltage gain (Av ∝ gm/I<sub>D</sub>) from 49 dB to 63 dB, the total power dissipation (Power ∝ I<sub>D</sub>) also improves (decreases) from 528 μW to 129 μW, while degrades the Gain-Bandwidth Product (GBW) from 343 MHz to 196 MHz (GBW ∝ gm). Depending on the application, the OTA bias conditions must be set appropriately due to the trade-off between Av and GBW. The obtained results show that the forksheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits using this technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109330"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-30DOI: 10.1016/j.sse.2025.109326
Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li
Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (PVE) and intrinsic parameter fluctuations (IPF). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (TNS), width (WNS), and gate length (LG)—play a pivotal role in shaping intrinsic resistance (ro), output resistance (Rout), voltage gain (AV), cut-off frequency (fT), and 3-dB bandwidth (f3dB), due to their influence on surface potential profiles and carrier transport behavior. Notably, within IPF, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (WKF) strongly perturb the channel surface potential, thereby inducing significant variability in AV, fT, f3dB, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of PVE and IPF. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.
栅极全能（GAA）硅纳米片互补场效应晶体管（cfet）的可变性主要来自两个方面：工艺变化效应（PVE）和内在参数波动（IPF）。在这项工作中，开发了一个系统的基于tcad的可变性框架，以定量评估PVE和IPF对垂直堆叠GAA Si NS cfet模拟和射频（RF）性能的影响。关键的几何因素-即NS厚度（TNS），宽度（WNS）和栅极长度(LG) -由于其对表面电位分布和载流子输运行为的影响，在形成固有电阻（ro），输出电阻（route），电压增益（AV），截止频率（fT）和3db带宽（f3dB）中起关键作用。值得注意的是，在IPF中，变化主要由随机纳米级金属颗粒控制，其中功函数波动（WKF）强烈干扰通道表面电位，从而诱导AV、fT、f3dB和其他射频参数的显著变化。采用统计上显著的校准设备模拟集合来解耦和量化PVE和IPF的单独和联合贡献。此外，还进行了小信号s参数分析，以提取实际负载条件下的RF值，为可变感知的CFET优化提供实用的设计见解。
{"title":"Radio-frequency variability of GAA Si NS CFETs induced by PVE and IPF simultaneously","authors":"Sekhar Reddy Kola , Min-Hui Chuang , Yiming Li","doi":"10.1016/j.sse.2025.109326","DOIUrl":"10.1016/j.sse.2025.109326","url":null,"abstract":"<div><div>Variability in gate-all-around (GAA) silicon nanosheet (Si NS) complementary field-effect transistors (CFETs) stems from two primary sources: process-variation effect (<em>PVE</em>) and intrinsic parameter fluctuations (<em>IPF</em>). In this work, a systematic TCAD-based variability framework is developed to quantitatively assess the impact of PVE and IPF on the analog and radio frequency (RF) performance of vertically stacked GAA Si NS CFETs. Key geometrical factors—namely NS thickness (<em>T<sub>NS</sub></em>), width (<em>W<sub>NS</sub></em>), and gate length (<em>L<sub>G</sub></em>)—play a pivotal role in shaping intrinsic resistance (<em>r<sub>o</sub></em>), output resistance (<em>R<sub>out</sub></em>), voltage gain (<em>A<sub>V</sub></em>), cut-off frequency (<em>f<sub>T</sub></em>), and 3-dB bandwidth (<em>f</em><sub>3</sub><em><sub>dB</sub></em>), due to their influence on surface potential profiles and carrier transport behavior. Notably, within <em>IPF</em>, variations are predominantly governed by random nanoscale metal grains, where work function fluctuations (<em>WKF</em>) strongly perturb the channel surface potential, thereby inducing significant variability in <em>A<sub>V</sub></em>, <em>f<sub>T</sub></em>, <em>f</em><sub>3</sub><em><sub>dB</sub></em>, other radio RF parameters. A statistically significant ensemble of calibrated device simulations is employed to decouple and quantify the individual and combined contributions of <em>PVE</em> and <em>IPF</em>. Furthermore, small-signal s-parameter analysis is performed to extract RF figures of merit under realistic loading conditions, providing practical design insights for variability-aware CFET optimizations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109326"},"PeriodicalIF":1.4,"publicationDate":"2025-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-29DOI: 10.1016/j.sse.2025.109327
Ghusoon M. Ali , Kahtan Adnan Hussain , Shahad T. Armoot
This study investigates the electrical sensitivities of warm white Al/pentacene/p-Si/Pd Schottky photodiodes with respect to current–voltage (I-V), capacitance–voltage (C-V), and conductance-voltage (G-V) characteristics. The pentacene thin film is deposited using the vacuum thermal evaporation technique. The energy level parameters of the Schottky junction are estimated through energy band diagrams. Two models are introduced to analyze the forward I-V characteristics of the pentacene Schottky diode: the thermionic emission theory and the space-charge-limited current model, both of which explain the mechanisms of charge carrier transport. The I-V, C-V, and G-V characteristics were examined under both dark and warm white illumination conditions, across a voltage range of −4 to 4 V at room temperature. Moreover, a study was conducted to assess, extract, and compare the sensitivities of current (SI), capacitance (SC), and conductance (SCO). The maximum SI is 1682 % at 0 V. Therefore, the proposed device demonstrates outstanding performance as a self-powered photodetector. The maximum SC is 38 % at −2.1 V, and SCO is 370 % at −1.6 V. The variations in sensitivity values are attributed to the different detection mechanisms employed. Overall, the results demonstrate the significant potential of the current-mode Schottky pentacene diode for use as a warm white self-powered photodetector.
{"title":"Warm white electrical sensitivities of pentacene-based Schottky photodiode","authors":"Ghusoon M. Ali , Kahtan Adnan Hussain , Shahad T. Armoot","doi":"10.1016/j.sse.2025.109327","DOIUrl":"10.1016/j.sse.2025.109327","url":null,"abstract":"<div><div>This study investigates the electrical sensitivities of warm white Al/pentacene/p-Si/Pd Schottky photodiodes with respect to current–voltage (I-V), capacitance–voltage (C-V), and conductance-voltage (G-V) characteristics. The pentacene thin film is deposited using the vacuum thermal evaporation technique. The energy level parameters of the Schottky junction are estimated through energy band diagrams. Two models are introduced to analyze the forward I-V characteristics of the pentacene Schottky diode: the thermionic emission theory and the space-charge-limited current model, both of which explain the mechanisms of charge carrier transport. The I-V, C-V, and G-V characteristics were examined under both dark and warm white illumination conditions, across a voltage range of −4 to 4 V at room temperature. Moreover, a study was conducted to assess, extract, and compare the sensitivities of current (S<sub>I</sub>), capacitance (S<sub>C</sub>), and conductance (S<sub>CO</sub>). The maximum S<sub>I</sub> is 1682 % at 0 V. Therefore, the proposed device demonstrates outstanding performance as a self-powered photodetector. The maximum S<sub>C</sub> is 38 % at −2.1 V, and S<sub>CO</sub> is 370 % at −1.6 V. The variations in sensitivity values are attributed to the different detection mechanisms employed. Overall, the results demonstrate the significant potential of the current-mode Schottky pentacene diode for use as a warm white self-powered photodetector.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109327"},"PeriodicalIF":1.4,"publicationDate":"2025-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-20DOI: 10.1016/j.sse.2025.109316
Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen
This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μeff) calculated from the ratio ID/(VG–VT) at low drain voltage; field-effect mobility (μFE) obtained from the transconductance in the linear regime; low-field mobility (μo) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of gm. The results consistently followed the trend μeff > μFE > μo, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (VT), subthreshold swing (SS), transconductance (gm), DIBL, output conductance (gD), Early voltage (VEA), and intrinsic gain (AV) were also evaluated, confirming that temperature and geometry critically influence device performance.
{"title":"Geometrical and thermal effects on mobility and analog parameters of AlGaN/GaN HEMTs on silicon substrates","authors":"Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen","doi":"10.1016/j.sse.2025.109316","DOIUrl":"10.1016/j.sse.2025.109316","url":null,"abstract":"<div><div>This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μ<sub>eff</sub>) calculated from the ratio I<sub>D</sub>/(V<sub>G</sub>–V<sub>T</sub>) at low drain voltage; field-effect mobility (μ<sub>FE</sub>) obtained from the transconductance in the linear regime; low-field mobility (μ<sub>o</sub>) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of g<sub>m</sub>. The results consistently followed the trend μ<sub>eff</sub> > μ<sub>FE</sub> > μ<sub>o</sub>, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (V<sub>T</sub>), subthreshold swing (SS), transconductance (g<sub>m</sub>), DIBL, output conductance (g<sub>D</sub>), Early voltage (V<sub>EA</sub>), and intrinsic gain (A<sub>V</sub>) were also evaluated, confirming that temperature and geometry critically influence device performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109316"},"PeriodicalIF":1.4,"publicationDate":"2025-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145840714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-18DOI: 10.1016/j.sse.2025.109315
Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui
This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.
{"title":"1T-DRAM with retrograde doping","authors":"Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui","doi":"10.1016/j.sse.2025.109315","DOIUrl":"10.1016/j.sse.2025.109315","url":null,"abstract":"<div><div>This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109315"},"PeriodicalIF":1.4,"publicationDate":"2025-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145840715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.
在这项工作中，我们提出了一种基于紧密结合方法（TBM）的算法，通过在紧密结合（TB）哈密顿量中包含与掺杂相关的自能校正项，来考虑通道掺杂对超薄体（UTB）双栅（DG）绝缘体上硅（SOI） MOS器件的能带结构和带隙的影响。首先，我们以现有的带隙缩小（BGN）模型为参考，确定室温下厚度和本征SOI通道（43 nm，量子约束效应可以忽略）的紧密结合哈密顿量中包含的自能量修正项，以确保n和p型掺杂的影响可以准确考虑。通过使用相同的自能校正项，同时也包括温度相关的带隙校正，然后我们量化了在大范围的器件温度（15 K - 300 K）、沟道厚度和掺杂密度下带隙缩小的程度。通过用泊松方程求解带结构的自洽解，进一步评价了这些器件的通道静电特性。此外，通过基于带结构的仿真方法，我们提出了考虑通道掺杂、厚度和器件温度变化的带隙模型。
{"title":"Unified approach for considering the effect of doping and device temperature on the band structure and electrostatics of UTB SOI DG MOS devices","authors":"Yogesh Dhote, Nalin Vilochan Mishra, Aditya Sankar Medury","doi":"10.1016/j.sse.2025.109313","DOIUrl":"10.1016/j.sse.2025.109313","url":null,"abstract":"<div><div>In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109313"},"PeriodicalIF":1.4,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.sse.2025.109314
Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang
Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.
{"title":"Improving the analog switching behavior in HfO2-based RRAM with simple 1T1R structure configuration","authors":"Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang","doi":"10.1016/j.sse.2025.109314","DOIUrl":"10.1016/j.sse.2025.109314","url":null,"abstract":"<div><div>Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109314"},"PeriodicalIF":1.4,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-05DOI: 10.1016/j.sse.2025.109304
So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, Ga-Won Lee
In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.
{"title":"A 10T2R non-volatile SRAM cell design with high-reliability","authors":"So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, Ga-Won Lee","doi":"10.1016/j.sse.2025.109304","DOIUrl":"10.1016/j.sse.2025.109304","url":null,"abstract":"<div><div>In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109304"},"PeriodicalIF":1.4,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.
{"title":"A methodology for process design kit re-centering using TCAD and experimental data for cryogenic temperatures","authors":"Tapas Dutta , Fikru Adamu-Lema , Djamel Bensouiah , Asen Asenov","doi":"10.1016/j.sse.2025.109306","DOIUrl":"10.1016/j.sse.2025.109306","url":null,"abstract":"<div><div>In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109306"},"PeriodicalIF":1.4,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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