Pub Date : 2025-12-20DOI: 10.1016/j.sse.2025.109316
Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen
This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μeff) calculated from the ratio ID/(VG–VT) at low drain voltage; field-effect mobility (μFE) obtained from the transconductance in the linear regime; low-field mobility (μo) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of gm. The results consistently followed the trend μeff > μFE > μo, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (VT), subthreshold swing (SS), transconductance (gm), DIBL, output conductance (gD), Early voltage (VEA), and intrinsic gain (AV) were also evaluated, confirming that temperature and geometry critically influence device performance.
{"title":"Geometrical and thermal effects on mobility and analog parameters of AlGaN/GaN HEMTs on silicon substrates","authors":"Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen","doi":"10.1016/j.sse.2025.109316","DOIUrl":"10.1016/j.sse.2025.109316","url":null,"abstract":"<div><div>This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μ<sub>eff</sub>) calculated from the ratio I<sub>D</sub>/(V<sub>G</sub>–V<sub>T</sub>) at low drain voltage; field-effect mobility (μ<sub>FE</sub>) obtained from the transconductance in the linear regime; low-field mobility (μ<sub>o</sub>) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of g<sub>m</sub>. The results consistently followed the trend μ<sub>eff</sub> > μ<sub>FE</sub> > μ<sub>o</sub>, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (V<sub>T</sub>), subthreshold swing (SS), transconductance (g<sub>m</sub>), DIBL, output conductance (g<sub>D</sub>), Early voltage (V<sub>EA</sub>), and intrinsic gain (A<sub>V</sub>) were also evaluated, confirming that temperature and geometry critically influence device performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109316"},"PeriodicalIF":1.4,"publicationDate":"2025-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145840714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-18DOI: 10.1016/j.sse.2025.109315
Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui
This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.
{"title":"1T-DRAM with retrograde doping","authors":"Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui","doi":"10.1016/j.sse.2025.109315","DOIUrl":"10.1016/j.sse.2025.109315","url":null,"abstract":"<div><div>This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109315"},"PeriodicalIF":1.4,"publicationDate":"2025-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145840715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.
在这项工作中，我们提出了一种基于紧密结合方法（TBM）的算法，通过在紧密结合（TB）哈密顿量中包含与掺杂相关的自能校正项，来考虑通道掺杂对超薄体（UTB）双栅（DG）绝缘体上硅（SOI） MOS器件的能带结构和带隙的影响。首先，我们以现有的带隙缩小（BGN）模型为参考，确定室温下厚度和本征SOI通道（43 nm，量子约束效应可以忽略）的紧密结合哈密顿量中包含的自能量修正项，以确保n和p型掺杂的影响可以准确考虑。通过使用相同的自能校正项，同时也包括温度相关的带隙校正，然后我们量化了在大范围的器件温度（15 K - 300 K）、沟道厚度和掺杂密度下带隙缩小的程度。通过用泊松方程求解带结构的自洽解，进一步评价了这些器件的通道静电特性。此外，通过基于带结构的仿真方法，我们提出了考虑通道掺杂、厚度和器件温度变化的带隙模型。
{"title":"Unified approach for considering the effect of doping and device temperature on the band structure and electrostatics of UTB SOI DG MOS devices","authors":"Yogesh Dhote, Nalin Vilochan Mishra, Aditya Sankar Medury","doi":"10.1016/j.sse.2025.109313","DOIUrl":"10.1016/j.sse.2025.109313","url":null,"abstract":"<div><div>In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109313"},"PeriodicalIF":1.4,"publicationDate":"2025-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.sse.2025.109314
Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang
Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.
{"title":"Improving the analog switching behavior in HfO2-based RRAM with simple 1T1R structure configuration","authors":"Jian Xia , Huikai He , Dingyi Shen , Xiangyang Jiang , Juntao Yang","doi":"10.1016/j.sse.2025.109314","DOIUrl":"10.1016/j.sse.2025.109314","url":null,"abstract":"<div><div>Resistive random-access memory (RRAM) featuring analog switching (AS) presents a compelling prospect for computing-in-memory (CIM) applications. However, achieving desirable analog switching behavior in filamentary RRAM cells remains challenging. In this work, two device structure configurations (1nT1rR & 1pT1R) were proposed to improve the AS behavior in one transistor and one resistor (1T1R) structure RRAM. The effect of the device structure configuration on analog switching behavior in 1T1R RRAM is elucidated. Compared with the conventional configuration in 1T1R RRAM, the RRAM with 1nT1rR & 1pT1R structure can effectively solve the problem of an abrupt changes in conductivity caused by the self-acceleration of ion migration during SET process. Under the excitation of electrical signals, the device shows excellent analog switching behavior and can achieve continuous modulation of conductivity. Thanks to the good linearity of the conductance modulation in the RRAM with modified structure, an artificial neural network (ANN) is established for the task of handwritten digit images recognition with a recognition accuracy of over 91%. Our work provides a simple strategy for the optimization of the switching behavior in RRAM and demonstrates great potential in the field of neuromorphic computing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109314"},"PeriodicalIF":1.4,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-05DOI: 10.1016/j.sse.2025.109304
So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, Ga-Won Lee
In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.
{"title":"A 10T2R non-volatile SRAM cell design with high-reliability","authors":"So-Yeon Kwon, Woon-San Ko, Jun-Ho Byun, Do-Yeon Lee, So-Yeong Park, Hye-Ri Hong, Ga-Won Lee","doi":"10.1016/j.sse.2025.109304","DOIUrl":"10.1016/j.sse.2025.109304","url":null,"abstract":"<div><div>In this study, a highly reliable 10T2R non-volatile SRAM (nvSRAM) cell is proposed. The previous nvSRAM structures face reliability issues of Resistive Random-Access Memory (RRAM) due to unwanted stress-induced data nodes. To overcome this challenge, the proposed 10T2R nvSRAM design integrates two transistors that effectively isolate both ends of the RRAM, acting as voltage blockers and current controllers. The SPICE simulation results show that the voltage stress applied to the RRAM during the Read/Write operation is less than 1 mV. Regarding the static noise margin (SNM), the SNM value of the 10T2R in each operation is similar to that of a 6T SRAM. Additionally, it successfully performs the RESTORE operation after power-on and demonstrates low power consumption. This highlights the potential of the proposed 10T2R cell to advance non-volatile memory technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109304"},"PeriodicalIF":1.4,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.
{"title":"A methodology for process design kit re-centering using TCAD and experimental data for cryogenic temperatures","authors":"Tapas Dutta , Fikru Adamu-Lema , Djamel Bensouiah , Asen Asenov","doi":"10.1016/j.sse.2025.109306","DOIUrl":"10.1016/j.sse.2025.109306","url":null,"abstract":"<div><div>In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109306"},"PeriodicalIF":1.4,"publicationDate":"2025-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1016/j.sse.2025.109296
Alan Blumenstein , Eduardo Pérez , Christian Wenger , Nadine Dersch , Alexander Kloes , Benjamín Iñíguez , Mike Schwarz
This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network’s robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.
{"title":"Exploring variability and quantization effects in artificial neural networks using the MNIST dataset","authors":"Alan Blumenstein , Eduardo Pérez , Christian Wenger , Nadine Dersch , Alexander Kloes , Benjamín Iñíguez , Mike Schwarz","doi":"10.1016/j.sse.2025.109296","DOIUrl":"10.1016/j.sse.2025.109296","url":null,"abstract":"<div><div>This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network’s robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109296"},"PeriodicalIF":1.4,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.sse.2025.109312
Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky
This paper reports on progress in cryogenic magnetic field sensing using vortex magnetic tunnel junctions (MTJs) at T < 10 K. The MTJ magnetoresistive signal is amplified using a wire-bonded foundry-fabricated 180 nm-process cryo-CMOS sense amplifier, providing ∼ 100 mG single-shot detectivity. Functional MTJ sensor deposition results on a true CMOS surface with fill exclusion are also presented. The aim is to make a magnetic field camera for tracking flux vortex motion in superconducting films, leading to optimized VLSI superconducting electronic (SCE) circuitry.
{"title":"Progress towards integration of MTJ devices with cryo-CMOS readout circuitry for magnetic field sensing","authors":"Z.C. Adamson , Liam K. Mitchell , Benjamin J. Brown , William R. Patterson , Gang Xiao , A. Zaslavsky","doi":"10.1016/j.sse.2025.109312","DOIUrl":"10.1016/j.sse.2025.109312","url":null,"abstract":"<div><div>This paper reports on progress in cryogenic magnetic field sensing using vortex magnetic tunnel junctions (MTJs) at <em>T</em> < 10 K. The MTJ magnetoresistive signal is amplified using a wire-bonded foundry-fabricated 180 nm-process cryo-CMOS sense amplifier, providing ∼ 100 mG single-shot detectivity. Functional MTJ sensor deposition results on a true CMOS surface with fill exclusion are also presented. The aim is to make a magnetic field camera for tracking flux vortex motion in superconducting films, leading to optimized VLSI superconducting electronic (SCE) circuitry.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109312"},"PeriodicalIF":1.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.sse.2025.109311
Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu
In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage (I-V) characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity (R) and detectability (D*) values of the photodiode were measured as 2.9 mA/W and 1.95 × 1013 Jones, respectively, at an illumination intensity of 80 mW/cm2. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.
{"title":"Design, Synthesis, and Optoelectronic Characterization of a Novel Cu(II) Complex-Based Photodiode with Prof. Dr. Yakuphanoglu’s Advanced Fytronix Solar Simulator Characterization Techniques","authors":"Aysegul Dere , Digdem Erdener , Mesut Yalcin , Namık Özdemir , Osman Dayan , Shehab Mansour , Fahrettin Yakuphanoglu","doi":"10.1016/j.sse.2025.109311","DOIUrl":"10.1016/j.sse.2025.109311","url":null,"abstract":"<div><div>In this study, a Cu(II) complex, [CuLCl2], containing pyridine-2,6-dicarboxamide (L) and two chloro ligands was synthesized from the reaction of CuCl2·.2H2O with pyridine-2,6-dicarboxamide in methanol and characterized for optoelectronic applications. X-ray crystallography confirmed the monoclinic structure of the complex and the presence of a square pyramidal geometry around the Cu(II) ion. Further characterization was performed using FT-IR spectroscopy, mass spectrometry, and electrochemical analysis. Additionally, the photonic device was fabricated by incorporating the Cu(II) complex as a layer on a p-type silicon substrate. The electrical and optical properties of the device were investigated at different illumination intensities. The current–voltage <em>(I-V)</em> characteristics indicate that the photodiode generates significant photocurrent under illumination. The device exhibited a stable and rapid photoresponse. The responsivity <em>(R)</em> and detectability <em>(D*)</em> values of the photodiode were measured as 2.9 mA/W and 1.95 × 10<sup>13</sup> Jones, respectively, at an illumination intensity of 80 mW/cm<sup>2</sup>. Time-dependent photo-response and detection analyses demonstrated the stability of the diode under light on–off cycles.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"233 ","pages":"Article 109311"},"PeriodicalIF":1.4,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145842278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-30DOI: 10.1016/j.sse.2025.109305
Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria
This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (VGS) at a low drain-to-source voltage (VDS) to observe its direct effect on the current noise spectral density (Sid), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The Sid extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing Sid with higher VGS, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct Sid trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).
{"title":"Evaluation of a single interface trap position on the low-frequency noise of junctionless nanowire transistors","authors":"Everton M. Silva , Renan Trevisoli , Rodrigo T. Doria","doi":"10.1016/j.sse.2025.109305","DOIUrl":"10.1016/j.sse.2025.109305","url":null,"abstract":"<div><div>This work investigates the impact of key operating parameters on the low-frequency noise (LFN) of experimental and simulated junctionless nanowire transistors. The primary goal was to vary the gate-to-source voltage (<em>V<sub>GS</sub></em>) at a low drain-to-source voltage (<em>V<sub>DS</sub></em>) to observe its direct effect on the current noise spectral density (<em>S<sub>id</sub></em>), as this provides crucial insights into the characteristics of predominant traps. The noise was measured by shifting the source and drain terminals, aiming to verify the influence of the dominant traps’ position on the noise. The <em>S<sub>id</sub></em> extractions were performed using a Keysight B1500 with an SR560 amplifier and an HP4395 spectrum analyzer. The analysis was supported by 3D numerical simulations of structures considering a single dominant trap center. The main results show a clear trend of increasing S<sub>id</sub> with higher V<sub>GS</sub>, although this is affected in short-channel devices. Most importantly, the trap location was confirmed to be a critical factor, demonstrating distinct <em>S<sub>id</sub></em> trends when traps are closer to the source with respect to the drain, a behavior also impacted by short-channel effects (SCEs).</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109305"},"PeriodicalIF":1.4,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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