Solid-state Electronics最新文献

Doping is a useful technique for metal oxide thin-film transistors (TFTs) to adjust the threshold voltage and charge carrier density. However, a notable drawback is the disruption of the microstructure caused by doping crystalline lattice, leading to a partial decrease in charge carrier mobility. In this work, we suggest a surface doping technique that modifies the carrier concentration and passivates the device surface while preserving the channel layer lattice structure through the use of organic dopant molecules. It is shown that tin oxide (SnO₂) TFTs doped in this manner typically exhibit improved electrical characteristics, particularly greater mobility and a noticeably lower threshold voltage, without negatively affecting the devices on/off current ratio. Furthermore, compared to pristine devices, bias stress stability and long-term durability are also enhanced. These findings suggest that surface doping may find use in high-performance oxide semiconductor devices and circuits.

This study presents a comprehensive approach to fine-tuning Cesium Lead Chloride Perovskite Field-Effect Transistors (CsPbCl₃-FETs) for sensing applications by bridging numerical modeling with experimental validation. By combining finite element methods in COMSOL Multiphysics for optimization, we tailored FET parameters such as oxide and perovskite thin film thickness. The fabricated FET, with a 200 nm semiconductor layer and 30 nm oxide thickness, was strategically chosen to operate in a non-depletion mode, maximizing mobility while minimizing power consumption. Experimental results closely aligned with numerical simulations, showcasing a threshold voltage of 0.50 V±0.07 V and an impressive on/off current ratio of 1.50 x 10⁴ ± 0.3 x 10⁴. Notably, the perovskite FET exhibited remarkable carrier mobility in saturation mode, reaching 5.40 cm²/V-s ± 0.8 cm²/V-s, outperforming other attempts in the literature. This work underscores the potential of CsPbCl₃ FETs for high-performance sensing applications, offering insights into optimizing device parameters for enhanced functionality and efficiency.

In this paper, accurate temperature-dependent static model for Silicon-Carbide (SiC) power MOSFET is presented. The proposed model is formed by two equations relating to linear and saturation operating regions. In this model, new formalism of the saturation drain current is introduced to consider the peculiar features observed in the I-V static characteristics of the SiC power MOSFET: a) moderate inversion region, or region of low gate voltages and b) quasi-saturation region, region of high gate voltages at which the drain current becomes less sensitive to the increase of gate voltage. In addition, the model captures with high-precision the transition region between linear and saturation region, pinch-off region, noticed in the output characteristics of the SiC power MOSFETs. It will be shown that the model equations ensure continuity and smooth transition between all operating regions. Temperature scaling of the model is carried out by its temperature scaling parameters. The proposed compact model is simple and efficient using reduced number of technology independent parameters. Simple parameter extraction procedure is described that uses an optimizer algorithm based on good experimental initial guess. Excellent agreement is obtained by comparing model to TCAD simulation and device measurement.

The AlGaN/GaN high electron mobility transistors (HEMTs) with T-gate that suitable for high frequency applications were fabricated. A novel method to extract the bias-dependent source and drain parasitic series resistances (R_s and R_d) of AlGaN/GaN HEMTs is proposed. By analyzing the distributed capacitance and current generator network in the velocity saturated regions of the AlGaN/GaN HEMTs, a new restriction relationship between small-signal equivalent circuit elements is found. The R_s and R_d can be determined under active bias through wideband S-parameter measurements, which can better reflect the physical mechanism of AlGaN/GaN HEMTs under normal operation. The S-parameters and extrinsic transconductance calculated based the small-signal equivalent circuit element values extracted by the method proposed in this paper are very consistent with the experimental values, which reflects the accuracy of this element extraction method. In this paper, the physical mechanism that causes R_s and R_d to vary with bias voltage is also studied. This study has a deeper insight into the bias-dependence of R_s and R_d, which modifies the understanding for physical mechanisms of AlGaN/GaN HEMTs. The research results provide new ideas for establishing small-signal equivalent circuit models containing more physical effects and is of great significance to GaN-based integrated circuit design.

The metal and two-dimension (2D) semiconductor contact interfaces have a more considerable contact resistance hindering carrier injection, which makes the performance of 2D semiconductor devices less than the theory. The contact properties of Ni, Au, and Mo with MoS₂ are simulated by the first-principles method. The interface dipole caused by the interface charge redistribution changes the work function difference at the metal-MoS₂ interface, so the interface charge redistribution is one of the important factors for correctly evaluating the contact properties. Due to the metal-induced gap states (MIGS) at metal-monolayer (ML) MoS₂ interfaces, the Fermi level is strongly pinned to fixed energy, and the Schottky barrier height (SBH) cannot be regulated efficiently by the metal work function. Although the work function of Au is bigger than Ni, the Fermi level of Au is pinned at a higher position. In the meantime, the bandgap of MoS₂ narrows and metallization occurs due to the larger MIGS. In the Mo-MoS₂ interface, the Fermi level is pinned near the conduction band minimum of MoS₂. The contact resistances (R_c) of the three structures are tested by the Circular Transfer Length Method (CTLM), which is consistent with the prediction of the simulation. The Mo-MoS₂ has the smallest R_c. The results indicate that contact resistance of 2D semiconductors cannot be simply predicted by soled work functions or Fermi level pinning, but is determined by several factors.

In this work, we present a machine-learning augmented compact modeling framework for modeling process induced variations in advanced semiconductor devices. The framework employs BSIM-CMG unified compact model at the core and can be used for any advanced devices like GAA nanosheets and nanowires, FinFETs etc. We have validated the model with extensive numerical simulations and experimental data such as $14\mathrm{nm}$ technology FinFET and $24\mathrm{nm}$ technology Nanowire. Our results show excellent accuracy in modeling variability in key electrical parameters of the device including off-current (I_off), on-current (I_on), threshold voltage (V_th), subthreshold swing (SS) etc. We observe that the overall accuracy of the ML-based framework strongly depends on the nature and physical behavior of the core model used for modeling the nominal device.