Solid-state Electronics最新文献

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Analysis of leakage current mechanisms in AlInGaN/GaN metal-insulator-semiconductor capacitors AlInGaN/GaN金属绝缘体-半导体电容器漏电流机理分析

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-11 DOI: 10.1016/j.sse.2025.109292

Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan

For emerging 5G millimeter-wave base stations and automotive radar systems operating in the V/W bands, suppressing gate leakage currents in AlInGaN/GaN MIS capacitors is critical to mitigate energy losses exceeding 15 % and thermal runaway risks under high-power RF conditions. This study systematically investigates the leakage mechanisms in AlInGaN/GaN Metal-Insulator-Semiconductor (MIS) capacitors, focusing on the influence of electrode geometry. We analyze the factors governing leakage behavior by fabricating devices with a series of electrode dimensions and spacings, and conducting comprehensive current–voltage (I-V) and capacitance–voltage (C-V) measurements. The results demonstrate that reducing electrode spacing intensifies local electric field concentration, enhancing trap-assisted tunneling at the interface and thereby increasing leakage current density. Conversely, increasing electrode size and spacing improves the uniformity of the electric field distribution and significantly mitigates the leakage currents. In addition, C-V measurement shows that the Si₃N₄ passivation process can effectively suppress the defects of the heterojunction interface. After passivation, the interface state density decreases to 6.1 × 10¹¹ cm⁻² eV⁻¹. Further analysis elucidates the voltage-dependent nature of leakage mechanisms: ohmic conduction dominates in low-field regions, while Schottky emission and Frenkel-Poole emission contribute in medium-to-high fields, with Fowler-Nordheim tunneling prevails under high electric fields. These findings emphasize the critical role of optimizing electrode geometries and interface passivation strategies in enhancing device reliability. This work provides theoretical insights and experimental guidance for advancing high-frequency, high-power GaN-based devices for emerging applications in communications and RF technologies.

对于新兴的5G毫米波基站和运行在V/W频段的汽车雷达系统，抑制AlInGaN/GaN MIS电容器中的栅极泄漏电流对于降低高功率射频条件下超过15%的能量损失和热失控风险至关重要。本研究系统地研究了AlInGaN/GaN金属绝缘体半导体（MIS）电容器的泄漏机制，重点研究了电极几何形状的影响。我们通过制造具有一系列电极尺寸和间距的器件，并进行全面的电流-电压（I-V）和电容-电压（C-V）测量，分析了影响泄漏行为的因素。结果表明，减小电极间距可增强局部电场浓度，增强界面处的陷阱辅助隧道效应，从而提高漏电流密度。相反，增加电极尺寸和间距可以改善电场分布的均匀性，并显著减轻泄漏电流。此外，C-V测量表明，Si3N4钝化工艺可以有效抑制异质结界面的缺陷。钝化后，界面态密度降至6.1 × 1011 cm−2 eV−1。进一步分析阐明了泄漏机制的电压依赖性：在低电场区域欧姆传导占主导地位，而在中高电场区域肖特基发射和Frenkel-Poole发射占主导地位，在高电场区域以Fowler-Nordheim隧穿为主。这些发现强调了优化电极几何形状和界面钝化策略在提高器件可靠性方面的关键作用。这项工作为推进高频，高功率基于gan的器件在通信和射频技术中的新兴应用提供了理论见解和实验指导。

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引用次数: 0

In-depth DC characterization of asymmetric vertical nanowire Accumulation-Mode junctionless GAA pMOSFETs on SOI from 300 K to 400 K 非对称垂直纳米线累积模式无结GAA pmosfet在300 K至400 K SOI上的深入直流特性

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-07 DOI: 10.1016/j.sse.2025.109290

A. Tahiat , B. Cretu , A. Veloso , E. Simoen

In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances (

R_{S} > R_{D}

). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.

在本文中，我们深入研究了在绝缘体上硅（SOI）衬底上制备的非对称垂直纳米线（VNW）积累模式无结（JL）栅极全能（GAA） pmosfet的直流（DC）特性。在线性和饱和状态下，测量温度范围从300 K到400 K。我们的结果揭示了显著的温度和极化依赖行为。研究表明，纳米线直径对直流性能有影响。与直径较小的纳米线相比，直径大于20nm的纳米线会导致断开状态泄漏电流显著增加，并且导通状态驱动电流更高。虽然更大的直径提高了导通电流，但它降低了亚阈值摆幅（SS），表明静电控制较弱。此外，由于其不对称结构，使用顶部电极作为漏极（正向工作模式）或源极（反向工作模式）会显著影响器件性能。在正向模式下，观察到更高的断开状态泄漏电流，而在反向模式下，导通状态饱和电流更高。这种不对称可能归因于非对称访问阻力（RS>；RD）。通过高温测量，采用不同的无串联电阻参数提取方法（基于y函数），观察到器件的串联电阻保持不变，低场迁移率主要受到库仑散射的限制。该研究为VNW积累模式JL GAA pmosfet的行为和性能提供了更好的理解，并为进一步优化铺平了道路。

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引用次数: 0

Band structure-based methodology for analysis of radiation-induced interface traps on reliability of UTB MOS devices 基于波段结构的辐射诱导界面陷阱对UTB MOS器件可靠性分析方法

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-07 DOI: 10.1016/j.sse.2025.109289

Nalin Vilochan Mishra, Yogesh Dhote, Aditya Sankar Medury

The impact of Ionizing Radiation (IR) dose on interface trap state generation is critical to consider in Ultra-Thin (UT) Silicon-on-Insulator (SOI) MOS devices, where these radiation-induced interface traps are likely to have a significant effect on the reliability of these devices. Additionally, in these devices, the effect of Quantum Confinement also needs to be properly considered to ensure an accurate analysis of device tolerance to radiation. Therefore, in this work, we present a band structure-based simulation approach to accurately quantify the maximum extent of radiation-induced (

α

, proton,

γ

, X-rays) interface traps and their degradation on these devices for various SOI channel thicknesses. Through this analysis, we then determine the practical radiation tolerance of these devices for various IR, with the consideration of partial recovery when subjected to continuous stress, and show the impact of QCEs on key electrostatic parameters such as threshold voltage and gate capacitance.

在超薄（UT）绝缘体上硅（SOI） MOS器件中，电离辐射（IR）剂量对界面阱态产生的影响至关重要，这些辐射诱导的界面阱可能对这些器件的可靠性产生重大影响。此外，在这些器件中，还需要适当考虑量子限制的影响，以确保准确分析器件的辐射耐受性。因此，在这项工作中，我们提出了一种基于能带结构的模拟方法，以准确量化辐射诱导（α，质子，γ， x射线）界面陷阱的最大程度及其在不同SOI通道厚度下在这些器件上的降解。通过这一分析，我们确定了这些器件在各种红外下的实际辐射容限，并考虑了在连续应力下的部分恢复，并显示了qce对阈值电压和栅极电容等关键静电参数的影响。

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引用次数: 0

A mathematical model for non-equilibrium body potential of SOI Pseudo-MOS and physical mechanism analysis SOI伪mos非平衡体势的数学模型及物理机理分析

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-07 DOI: 10.1016/j.sse.2025.109287

Tiexin Zhang , Fanyu Liu , Lei Shu , Bo Li , Zhengsheng Han , Tianchun Ye

Based on SOI Pseudo-MOS, an equivalent circuit model of non-equilibrium body potential (V_neq) is proposed. The non-equilibrium majority carriers cannot be neglected to interpret the mechanism of V_neq. An accurate mathematical V_neq is determined through bringing non-equilibrium majority carriers into the discrete Poisson equation, which is validated by TCAD simulations.

基于SOI伪mos，提出了非平衡体电位（Vneq）的等效电路模型。非平衡多数载流子是解释Vneq机理的重要因素。通过在离散泊松方程中引入非平衡多数载流子，确定了精确的数学Vneq，并通过TCAD仿真进行了验证。

引用次数: 0

Investigation of compliance current effect on resistive switching properties in Ag/SiOx/Cr RRAM devices 顺应电流对Ag/SiOx/Cr RRAM器件阻性开关特性影响的研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-05 DOI: 10.1016/j.sse.2025.109288

Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński

In this work, we present the investigation of resistive switching properties in Ag/SiO_x/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.

在这项工作中，我们提出了Ag/SiOx/Cr RRAM器件的电阻开关特性的研究。我们制作了器件，并分析了顺应电流对器件性能的影响。电特性揭示了双极和阈值开关取决于顺应电流的值。我们使用电化学阻抗谱来获得关于成形过程的信息，揭示金属离子在成形过程中的迁移。

引用次数: 0

Nanosheet Transistor Applied in a Two-Stage Operational Transconductance Amplifier from 125 °C down to −100 °C 纳米片晶体管应用于二级操作跨导放大器从125°C到- 100°C

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-05 DOI: 10.1016/j.sse.2025.109291

Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian

This work is related to the analysis of Gate-All-Around Nanosheet (GAA-NSH) devices operating from 125 °C down to −100 °C, focusing on their analog potential. The Verilog-A model was developed using experimental data, and the two-stage operational transconductance amplifier (OTA) was designed for transistor efficiency (g_m ⁄ I_DS) of around 8 V⁻¹ and supply voltage (V_DD) of 1.8 V at room temperature. The OTA temperature influence was analyzed for different temperatures. When the temperature ranges from 125 °C to −100 °C, the OTA voltage gain improved from 63.2 to 72.4 dB and the gain bandwidth product (GBW) also improved from 354 to 460 MHz, considering that the bias circuit (I_SS) is temperature-compensated (I_SS and V_CM are constant in the studied temperature range). The obtained results show that the nanosheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits in this temperature range.

这项工作与栅极全能纳米片（GAA-NSH）器件在125°C至- 100°C下工作的分析有关，重点关注它们的模拟电位。利用实验数据开发了Verilog-A模型，并设计了两级操作跨导放大器（OTA），室温下晶体管效率（gm / IDS）约为8 V−1，电源电压（VDD）为1.8 V。分析了不同温度对OTA温度的影响。当温度范围为125℃~−100℃时，考虑到偏置电路（ISS）是温度补偿的（ISS和VCM在研究温度范围内不变），OTA电压增益从63.2提高到72.4 dB，增益带宽积（GBW）也从354提高到460 MHz。结果表明，该纳米片可用于OTA等模拟电路，在该温度范围内可用于混合信号集成电路。

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引用次数: 0

Design of high robustness DDSCR with embedded gate-controlled diodes and Schottky diodes 嵌入式门控二极管和肖特基二极管的高鲁棒性DDSCR设计

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-02 DOI: 10.1016/j.sse.2025.109283

Yitao Wang , Shuoxin Ji , Yang Wang

Due to the harsh working environments of Input/Output (I/O) pins, the electro-static discharge (ESD) protection devices of these ports often require high robustness. To design highly robust ESD protection devices with dual polarities, the Gate-controlled dual direction silicon controlled rectifier (GCDDSCR) and a DDSCR embedded with Schottky barrier diode (SBD-GCDDSCR) structures are designed and studied in this article as standalone devices for primary protection. The gate-controlled diodes and Schottky diodes are integrated into the simple DDSCR structure to enhance its robustness while reducing the on-resistance. The inclusion of gate diodes introduced an additional current path near the surface, improving space utilization in the longitudinal direction of the device, and the addition of Schottky junctions placed adjacent to the Anode and Cathode can provide additional electron extraction paths. Both methods contribute in a more uniform current distribution, improving the robustness of the device. Two-dimensional device simulation based on a classical set of equations was employed to investigate its electrical behavior during an ESD event. Based on the 0.18 μm CMOS process, all structures were fabricated into 6-finger devices with a finger length of 50 μm. The Transmission Line Pulse (TLP) testing method was used to evaluate their ESD characteristics, revealing that the addition of the gate-controlled diodes and Schottky shunt paths improved robustness. The proposed SBD-GCDDSCR structure demonstrated superior robustness under ESD stress, with a failure current exceeding 19 A in both forward and reverse directions, and its V_t2 in strong saturation regime is around 48 V.

由于输入/输出（I/O）引脚的工作环境恶劣，因此这些端口的ESD （electrostatic discharge）保护器件通常要求很高的鲁棒性。为了设计具有高鲁棒性的双极性ESD保护器件，本文设计并研究了门控双向可控硅整流器（GCDDSCR）和嵌入肖特基势垒二极管（SBD-GCDDSCR）作为独立的初级保护器件。门控二极管和肖特基二极管集成到简单的DDSCR结构中，以提高其稳健性，同时降低导通电阻。栅极二极管的包含在表面附近引入了额外的电流路径，提高了器件纵向上的空间利用率，并且在阳极和阴极附近添加的肖特基结可以提供额外的电子提取路径。这两种方法都有助于更均匀的电流分布，提高器件的稳健性。采用基于经典方程组的二维器件仿真方法研究了其在ESD事件中的电学行为。基于0.18 μm CMOS工艺，将所有结构制作成指长为50 μm的6指器件。使用传输线脉冲（TLP）测试方法评估了它们的ESD特性，结果表明，门控二极管和肖特基分流路径的加入提高了稳健性。所提出的SBD-GCDDSCR结构在ESD应力下具有优异的鲁棒性，正反方向失效电流均超过19 a，强饱和状态下的Vt2约为48 V。

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引用次数: 0

Scattering matrix-based low computational cost model for the device and circuit co-simulation of phosphorene tunnel field-effect transistors 基于散射矩阵的磷二烯隧道场效应晶体管器件与电路联合仿真的低计算成本模型

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-01 DOI: 10.1016/j.sse.2025.109270

Kosuke Yamaguchi, Satofumi Souma

We propose an efficient device-circuit co-simulation framework for phosphorene tunnel FETs, focusing on circuit-level impacts of structural imperfections such as grain boundaries and adsorption. A fast table-generation scheme based on the scattering matrix approach and a capacitance model enables physically grounded current and capacitance characteristics to be obtained across bias conditions. These tables are smoothly integrated into SPICE simulations via Verilog-A, naturally capturing effects such as DIBL and intrinsic capacitances. Using this framework, we demonstrate the sensitivity of inverter and ring oscillator performance to the magnitude and position of grain boundaries, highlighting their role as a major source of variability in 2D TFET circuits. Overall, the framework provides a practical and extensible platform for evaluating low-power 2D devices under realistic variability.

我们提出了一个高效的器件电路联合模拟框架，用于磷烯隧道场效应管，重点关注结构缺陷（如晶界和吸附）对电路水平的影响。基于散射矩阵方法和电容模型的快速表生成方案可以获得跨偏置条件下的物理接地电流和电容特性。这些表通过Verilog-A顺利集成到SPICE模拟中，自然捕获DIBL和固有电容等效果。利用这个框架，我们展示了逆变器和环形振荡器性能对晶界的大小和位置的敏感性，突出了它们作为二维ttfet电路中可变性的主要来源的作用。总体而言，该框架为在现实可变性下评估低功耗2D器件提供了一个实用且可扩展的平台。

引用次数: 0

Enhanced photoresponse in Cu/n-Si Schottky photodetectors via RF sputtering: A comparative study with thermal evaporation 通过射频溅射增强Cu/n-Si肖特基光电探测器的光响应：与热蒸发的比较研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-11-01 DOI: 10.1016/j.sse.2025.109268

Rajat Kumar Goyal , Madhuram Mishra , Pragya Kushwaha , Sunil Babu Eadi , Harshit Agarwal

Schottky barrier photodetectors (SBPDs) have low-cost fabrication, CMOS compatibility, and scalability. This work presents a comparative analysis of Cu/n-Si Schottky photodetectors fabricated using two distinct copper deposition techniques: thermal evaporation and RF sputtering. Comparative analyses were conducted using field-emission scanning electron microscopy (FE-SEM), electrical I–V measurements, responsivity analysis, and time-resolved photocurrent studies. Morphological characterization revealed that thermally evaporated films formed larger, anisotropic grains, whereas RF-sputtered films exhibited finer and more uniform grain structures. Devices fabricated via RF sputtering exhibited superior electrical and optoelectronic performance with higher photocurrent, enhanced responsivity (up to 0.146 A/W under 532 nm illumination and 0.038 A/W under 650 nm illumination), and faster, more stable photoresponses—even under zero-bias conditions. These results demonstrate the significant role of deposition technique in tuning microstructure and optimizing photodetector efficiency for low-power sensing applications.

肖特基势垒光电探测器（sbpd）具有低成本制造，CMOS兼容性和可扩展性。这项工作提出了使用两种不同的铜沉积技术：热蒸发和射频溅射制备的Cu/n-Si肖特基光电探测器的比较分析。采用场发射扫描电镜（FE-SEM）、电I-V测量、响应性分析和时间分辨光电流研究进行了比较分析。形貌表征表明，热蒸发膜形成较大的各向异性晶粒，而射频溅射膜的晶粒结构更细、更均匀。通过射频溅射制备的器件具有优异的电学和光电性能，具有更高的光电流，增强的响应率（在532 nm照明下高达0.146 A/W，在650 nm照明下高达0.038 A/W）以及更快，更稳定的光响应-即使在零偏置条件下。这些结果证明了沉积技术在调整微观结构和优化光电探测器效率方面的重要作用。

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引用次数: 0

3D simulation of charge defect impact on an industrial 28 nm FD-SOI quantum dot 工业28 nm FD-SOI量子点上电荷缺陷影响的三维模拟

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-10-29 DOI: 10.1016/j.sse.2025.109285

Benjamin Bureau , Félix Beaudoin , Pericles Philippopoulos , Salvador Mir , Eva Dupont-Ferrier , Philippe Galy

The emergence of cryo-electronics and quantum applications has shown that experiments involving quantum dots are highly sensitive to disorder and variability. This sensitivity offers the opportunity to detect and classify defects, evaluate process quality in detail, and guide the enhancement of robustness. In this preliminary work, we explore the 3D quantum simulation of an industrial FD-SOI quantum dot device, with and without a charge defect.

低温电子学和量子应用的出现表明，涉及量子点的实验对无序和可变性高度敏感。这种灵敏度提供了检测和分类缺陷的机会，详细评估过程质量，并指导鲁棒性的增强。在这项初步工作中，我们探索了工业FD-SOI量子点器件的三维量子模拟，有和没有电荷缺陷。

引用次数: 0

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