Pub Date : 2025-11-30DOI: 10.1016/j.sse.2025.109307
D. Barge , M. Gallard , J.-M. Hartmann , F. Fournel , V. Loup , F. Mazen , E. Nolot , P. Hauchecorne , J. Sturm , V.H. Le , I. Huyet , D. Delprat , F. Boedt , F. Servant
This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.
{"title":"300 Mm sSOI engineering with ultra thin buried oxide","authors":"D. Barge , M. Gallard , J.-M. Hartmann , F. Fournel , V. Loup , F. Mazen , E. Nolot , P. Hauchecorne , J. Sturm , V.H. Le , I. Huyet , D. Delprat , F. Boedt , F. Servant","doi":"10.1016/j.sse.2025.109307","DOIUrl":"10.1016/j.sse.2025.109307","url":null,"abstract":"<div><div>This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109307"},"PeriodicalIF":1.4,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work employs a two-stage low temperature defect reduction annealing treatment for oxidation state modulation and defect reduction of stannous oxide (SnO) thin-film transistors (TFTs). With higher Sn2+ proportion and fewer defects, the device stability and carrier mobility of p-type SnO TFTs are improved. The SnO TFTs with two-stage low temperature defect reduction annealing exhibit an on/off ratio of 1.22 × 104, a field-effect mobility of 0.44 cm2/V·s, a 50.2 % reduction in IOFF, without subthreshold swing degradation. With the detailed material analysis, the internal physical mechanism of the defect reduction in of SnO is well discussed. The discoveries presented in this work are expected to provide technical methodologies for the high-performance TFTs.
{"title":"Oxidation state modulation for p-Type stannous oxide with Two-Stage low temperature defect reduction annealing","authors":"Zhibo Zeng , Kai-Jhih Gan , Wenjie Lei , Shiyu Zeng , Jialong Xiang , Bojun Zhang , Kuei-Shu Chang-Liao , Cheng-Chang Yu , Po-Chung Huang , Dun-Bao Ruan","doi":"10.1016/j.sse.2025.109308","DOIUrl":"10.1016/j.sse.2025.109308","url":null,"abstract":"<div><div>This work employs a two-stage low temperature defect reduction annealing treatment for oxidation state modulation and defect reduction of stannous oxide (SnO) thin-film transistors (TFTs). With higher Sn<sup>2+</sup> proportion and fewer defects, the device stability and carrier mobility of p-type SnO TFTs are improved. The SnO TFTs with two-stage low temperature defect reduction annealing exhibit an on/off ratio of 1.22 × 10<sup>4</sup>, a field-effect mobility of 0.44 cm<sup>2</sup>/V·s, a 50.2 % reduction in I<sub>OFF</sub>, without subthreshold swing degradation. With the detailed material analysis, the internal physical mechanism of the defect reduction in of SnO is well discussed. The discoveries presented in this work are expected to provide technical methodologies for the high-performance TFTs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109308"},"PeriodicalIF":1.4,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145652096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-29DOI: 10.1016/j.sse.2025.109295
Bogdan Majkusiak
A computational model of probability of tunneling through Schottky barrier, based on the transfer matrix method, is presented and used for a quantitative study of tunneling probability and tunnel current at comparison to the over-barrier transitions for various parameters of Al-SiO2-Si(n) material system. It is proved that tunneling through Schottky barrier can significantly contribute to the total current even at moderate doping levels, especially if the insulator layer is very thin.
{"title":"Modeling of tunneling through Schottky barriers","authors":"Bogdan Majkusiak","doi":"10.1016/j.sse.2025.109295","DOIUrl":"10.1016/j.sse.2025.109295","url":null,"abstract":"<div><div>A computational model of probability of tunneling through Schottky barrier, based on the transfer matrix method, is presented and used for a quantitative study of tunneling probability and tunnel current at comparison to the over-barrier transitions for various parameters of Al-SiO<sub>2</sub>-Si(n) material system. It is proved that tunneling through Schottky barrier can significantly contribute to the total current even at moderate doping levels, especially if the insulator layer is very thin.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109295"},"PeriodicalIF":1.4,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145652095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1016/j.sse.2025.109284
Tomáš Hadámek , Viktor Sverdlov
A fully 3D model coupling spin, charge, magnetization, and temperature dynamics has been employed to study the two-terminal spin–orbit-torque magnetoresistive random-access memory (2T-SOT-MRAM). To account for heating from tunneling electrons, we applied an asymmetric heating model near the tunnel barrier, revealing that symmetric model can underestimate free layer temperature increase by over 25%. We further employ the model to simulate switching of the 2T-SOT-MRAM under different voltage pulse shapes and show that the pulse-shaping strategies can not only reduce power consumption by more than 30%, but also significantly reduce peak temperature of the device during writing.
{"title":"Temperature modeling and pulse shaping strategies for energy optimization in 2T-SOT-MRAM","authors":"Tomáš Hadámek , Viktor Sverdlov","doi":"10.1016/j.sse.2025.109284","DOIUrl":"10.1016/j.sse.2025.109284","url":null,"abstract":"<div><div>A fully 3D model coupling spin, charge, magnetization, and temperature dynamics has been employed to study the two-terminal spin–orbit-torque magnetoresistive random-access memory (2T-SOT-MRAM). To account for heating from tunneling electrons, we applied an asymmetric heating model near the tunnel barrier, revealing that symmetric model can underestimate free layer temperature increase by over 25%. We further employ the model to simulate switching of the 2T-SOT-MRAM under different voltage pulse shapes and show that the pulse-shaping strategies can not only reduce power consumption by more than 30%, but also significantly reduce peak temperature of the device during writing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109284"},"PeriodicalIF":1.4,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-19DOI: 10.1016/j.sse.2025.109294
H. García , G. Vinuesa , T.del Val , K. Kalam , M.B. González , F. Campabadal , S. Dueñas , H. Castán
Memristors have drawn interest due to their use as artificial synapses in neuromorphic circuits. This work investigates the multilevel conductance modulation in Al2O3 and HfO2-based memristors. Specifically, the control of the depression or reset transition when applying identical consecutive voltage pulses was the main objective. Both pulse amplitude and pulse accumulated time can control the reset transition. Voltage required to reset the device is higher for Al2O3, which can lead to higher energy consumption. However, this material showed better reset transition linearity.
{"title":"Multilevel conductance modulation in HfO2, Al2O3, and HfO2/Al2O3 bilayer memristors","authors":"H. García , G. Vinuesa , T.del Val , K. Kalam , M.B. González , F. Campabadal , S. Dueñas , H. Castán","doi":"10.1016/j.sse.2025.109294","DOIUrl":"10.1016/j.sse.2025.109294","url":null,"abstract":"<div><div>Memristors have drawn interest due to their use as artificial synapses in neuromorphic circuits. This work investigates the multilevel conductance modulation in Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub>-based memristors. Specifically, the control of the depression or reset transition when applying identical consecutive voltage pulses was the main objective. Both pulse amplitude and pulse accumulated time can control the reset transition. Voltage required to reset the device is higher for Al<sub>2</sub>O<sub>3</sub>, which can lead to higher energy consumption. However, this material showed better reset transition linearity.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109294"},"PeriodicalIF":1.4,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-15DOI: 10.1016/j.sse.2025.109293
M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska
This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.
{"title":"Effect of PN passivation on MOSFETs performance in 28 nm FD-SOI","authors":"M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska","doi":"10.1016/j.sse.2025.109293","DOIUrl":"10.1016/j.sse.2025.109293","url":null,"abstract":"<div><div>This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109293"},"PeriodicalIF":1.4,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1016/j.sse.2025.109292
Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan
For emerging 5G millimeter-wave base stations and automotive radar systems operating in the V/W bands, suppressing gate leakage currents in AlInGaN/GaN MIS capacitors is critical to mitigate energy losses exceeding 15 % and thermal runaway risks under high-power RF conditions. This study systematically investigates the leakage mechanisms in AlInGaN/GaN Metal-Insulator-Semiconductor (MIS) capacitors, focusing on the influence of electrode geometry. We analyze the factors governing leakage behavior by fabricating devices with a series of electrode dimensions and spacings, and conducting comprehensive current–voltage (I-V) and capacitance–voltage (C-V) measurements. The results demonstrate that reducing electrode spacing intensifies local electric field concentration, enhancing trap-assisted tunneling at the interface and thereby increasing leakage current density. Conversely, increasing electrode size and spacing improves the uniformity of the electric field distribution and significantly mitigates the leakage currents. In addition, C-V measurement shows that the Si3N4 passivation process can effectively suppress the defects of the heterojunction interface. After passivation, the interface state density decreases to 6.1 × 1011 cm−2 eV−1. Further analysis elucidates the voltage-dependent nature of leakage mechanisms: ohmic conduction dominates in low-field regions, while Schottky emission and Frenkel-Poole emission contribute in medium-to-high fields, with Fowler-Nordheim tunneling prevails under high electric fields. These findings emphasize the critical role of optimizing electrode geometries and interface passivation strategies in enhancing device reliability. This work provides theoretical insights and experimental guidance for advancing high-frequency, high-power GaN-based devices for emerging applications in communications and RF technologies.
{"title":"Analysis of leakage current mechanisms in AlInGaN/GaN metal-insulator-semiconductor capacitors","authors":"Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan","doi":"10.1016/j.sse.2025.109292","DOIUrl":"10.1016/j.sse.2025.109292","url":null,"abstract":"<div><div>For emerging 5G millimeter-wave base stations and automotive radar systems operating in the V/W bands, suppressing gate leakage currents in AlInGaN/GaN MIS capacitors is critical to mitigate energy losses exceeding 15 % and thermal runaway risks under high-power RF conditions. This study systematically investigates the leakage mechanisms in AlInGaN/GaN Metal-Insulator-Semiconductor (MIS) capacitors, focusing on the influence of electrode geometry. We analyze the factors governing leakage behavior by fabricating devices with a series of electrode dimensions and spacings, and conducting comprehensive current–voltage (I-V) and capacitance–voltage (C-V) measurements. The results demonstrate that reducing electrode spacing intensifies local electric field concentration, enhancing trap-assisted tunneling at the interface and thereby increasing leakage current density. Conversely, increasing electrode size and spacing improves the uniformity of the electric field distribution and significantly mitigates the leakage currents. In addition, C-V measurement shows that the Si<sub>3</sub>N<sub>4</sub> passivation process can effectively suppress the defects of the heterojunction interface. After passivation, the interface state density decreases to 6.1 × 10<sup>11</sup> cm<sup>−2</sup> eV<sup>−1</sup>. Further analysis elucidates the voltage-dependent nature of leakage mechanisms: ohmic conduction dominates in low-field regions, while Schottky emission and Frenkel-Poole emission contribute in medium-to-high fields, with Fowler-Nordheim tunneling prevails under high electric fields. These findings emphasize the critical role of optimizing electrode geometries and interface passivation strategies in enhancing device reliability. This work provides theoretical insights and experimental guidance for advancing high-frequency, high-power GaN-based devices for emerging applications in communications and RF technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109292"},"PeriodicalIF":1.4,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1016/j.sse.2025.109290
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances (). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.
{"title":"In-depth DC characterization of asymmetric vertical nanowire Accumulation-Mode junctionless GAA pMOSFETs on SOI from 300 K to 400 K","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109290","DOIUrl":"10.1016/j.sse.2025.109290","url":null,"abstract":"<div><div>In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances (<span><math><mrow><msub><mi>R</mi><mi>S</mi></msub><mspace></mspace><mo>></mo><mspace></mspace><msub><mi>R</mi><mi>D</mi></msub></mrow></math></span>). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109290"},"PeriodicalIF":1.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The impact of Ionizing Radiation (IR) dose on interface trap state generation is critical to consider in Ultra-Thin (UT) Silicon-on-Insulator (SOI) MOS devices, where these radiation-induced interface traps are likely to have a significant effect on the reliability of these devices. Additionally, in these devices, the effect of Quantum Confinement also needs to be properly considered to ensure an accurate analysis of device tolerance to radiation. Therefore, in this work, we present a band structure-based simulation approach to accurately quantify the maximum extent of radiation-induced (, proton, , X-rays) interface traps and their degradation on these devices for various SOI channel thicknesses. Through this analysis, we then determine the practical radiation tolerance of these devices for various IR, with the consideration of partial recovery when subjected to continuous stress, and show the impact of QCEs on key electrostatic parameters such as threshold voltage and gate capacitance.
{"title":"Band structure-based methodology for analysis of radiation-induced interface traps on reliability of UTB MOS devices","authors":"Nalin Vilochan Mishra, Yogesh Dhote, Aditya Sankar Medury","doi":"10.1016/j.sse.2025.109289","DOIUrl":"10.1016/j.sse.2025.109289","url":null,"abstract":"<div><div>The impact of Ionizing Radiation (IR) dose on interface trap state generation is critical to consider in Ultra-Thin (UT) Silicon-on-Insulator (SOI) MOS devices, where these radiation-induced interface traps are likely to have a significant effect on the reliability of these devices. Additionally, in these devices, the effect of Quantum Confinement also needs to be properly considered to ensure an accurate analysis of device tolerance to radiation. Therefore, in this work, we present a band structure-based simulation approach to accurately quantify the maximum extent of radiation-induced (<span><math><mi>α</mi></math></span>, proton, <span><math><mi>γ</mi></math></span>, X-rays) interface traps and their degradation on these devices for various SOI channel thicknesses. Through this analysis, we then determine the practical radiation tolerance of these devices for various IR, with the consideration of partial recovery when subjected to continuous stress, and show the impact of QCEs on key electrostatic parameters such as threshold voltage and gate capacitance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109289"},"PeriodicalIF":1.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1016/j.sse.2025.109287
Tiexin Zhang , Fanyu Liu , Lei Shu , Bo Li , Zhengsheng Han , Tianchun Ye
Based on SOI Pseudo-MOS, an equivalent circuit model of non-equilibrium body potential (Vneq) is proposed. The non-equilibrium majority carriers cannot be neglected to interpret the mechanism of Vneq. An accurate mathematical Vneq is determined through bringing non-equilibrium majority carriers into the discrete Poisson equation, which is validated by TCAD simulations.
{"title":"A mathematical model for non-equilibrium body potential of SOI Pseudo-MOS and physical mechanism analysis","authors":"Tiexin Zhang , Fanyu Liu , Lei Shu , Bo Li , Zhengsheng Han , Tianchun Ye","doi":"10.1016/j.sse.2025.109287","DOIUrl":"10.1016/j.sse.2025.109287","url":null,"abstract":"<div><div>Based on SOI Pseudo-MOS, an equivalent circuit model of non-equilibrium body potential (<em>V</em><sub>neq</sub>) is proposed. The non-equilibrium majority carriers cannot be neglected to interpret the mechanism of <em>V</em><sub>neq.</sub> An accurate mathematical <em>V</em><sub>neq</sub> is determined through bringing non-equilibrium majority carriers into the discrete Poisson equation, which is validated by TCAD simulations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109287"},"PeriodicalIF":1.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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