Pub Date : 2026-02-01Epub Date: 2025-11-30DOI: 10.1016/j.sse.2025.109307
D. Barge , M. Gallard , J.-M. Hartmann , F. Fournel , V. Loup , F. Mazen , E. Nolot , P. Hauchecorne , J. Sturm , V.H. Le , I. Huyet , D. Delprat , F. Boedt , F. Servant
This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.
{"title":"300 Mm sSOI engineering with ultra thin buried oxide","authors":"D. Barge , M. Gallard , J.-M. Hartmann , F. Fournel , V. Loup , F. Mazen , E. Nolot , P. Hauchecorne , J. Sturm , V.H. Le , I. Huyet , D. Delprat , F. Boedt , F. Servant","doi":"10.1016/j.sse.2025.109307","DOIUrl":"10.1016/j.sse.2025.109307","url":null,"abstract":"<div><div>This paper presents the fabrication of 300 mm tensile-strained silicon-on-insulator (sSOI) wafers designed for next-generation fully depleted silicon-on-insulator (FD-SOI) CMOS devices. The wafers feature a 25 nm thick buried oxide (BOX) and a 12 nm thick tensile-strained top silicon layer. The integration scheme involved growing a thin silicon layer on a relaxed SiGe thick graded buffer, followed by partial transfer to a base wafer using the Smart Cut™ process. The tensile stress in the top silicon layer was successfully modulated from 0.6 GPa to 1.8 GPa by adjusting the germanium content in the SiGe thick graded buffer underneath. Transmission electron microscopy and Raman spectroscopy confirmed the high crystalline quality and uniform strain distribution across the wafers. The study demonstrates the potential for achieving different levels of strain to optimize the performance of nMOS devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109307"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-04DOI: 10.1016/j.sse.2025.109296
Alan Blumenstein , Eduardo Pérez , Christian Wenger , Nadine Dersch , Alexander Kloes , Benjamín Iñíguez , Mike Schwarz
This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network’s robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.
{"title":"Exploring variability and quantization effects in artificial neural networks using the MNIST dataset","authors":"Alan Blumenstein , Eduardo Pérez , Christian Wenger , Nadine Dersch , Alexander Kloes , Benjamín Iñíguez , Mike Schwarz","doi":"10.1016/j.sse.2025.109296","DOIUrl":"10.1016/j.sse.2025.109296","url":null,"abstract":"<div><div>This paper investigates the impact of introducing variability to trained neural networks and examines the effects of variability and quantization on network accuracy. The study utilizes the MNIST dataset to evaluate various Multi-Layer Perceptron configurations: a baseline model with a Single-Layer Perceptron and an extended model with multiple hidden nodes. The effects of Cycle-to-Cycle variability on network accuracy are explored by varying parameters such as the standard deviation to simulate dynamic changes in network weights. In particular, the performance differences between the Single-Layer Perceptron and the Multi-Layer Perceptron with hidden layers are analyzed, highlighting the network’s robustness to stochastic perturbations. These results provide insights into the effects of quantization and network architecture on accuracy under varying levels of variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109296"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-11-25DOI: 10.1016/j.sse.2025.109284
Tomáš Hadámek , Viktor Sverdlov
A fully 3D model coupling spin, charge, magnetization, and temperature dynamics has been employed to study the two-terminal spin–orbit-torque magnetoresistive random-access memory (2T-SOT-MRAM). To account for heating from tunneling electrons, we applied an asymmetric heating model near the tunnel barrier, revealing that symmetric model can underestimate free layer temperature increase by over 25%. We further employ the model to simulate switching of the 2T-SOT-MRAM under different voltage pulse shapes and show that the pulse-shaping strategies can not only reduce power consumption by more than 30%, but also significantly reduce peak temperature of the device during writing.
{"title":"Temperature modeling and pulse shaping strategies for energy optimization in 2T-SOT-MRAM","authors":"Tomáš Hadámek , Viktor Sverdlov","doi":"10.1016/j.sse.2025.109284","DOIUrl":"10.1016/j.sse.2025.109284","url":null,"abstract":"<div><div>A fully 3D model coupling spin, charge, magnetization, and temperature dynamics has been employed to study the two-terminal spin–orbit-torque magnetoresistive random-access memory (2T-SOT-MRAM). To account for heating from tunneling electrons, we applied an asymmetric heating model near the tunnel barrier, revealing that symmetric model can underestimate free layer temperature increase by over 25%. We further employ the model to simulate switching of the 2T-SOT-MRAM under different voltage pulse shapes and show that the pulse-shaping strategies can not only reduce power consumption by more than 30%, but also significantly reduce peak temperature of the device during writing.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109284"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.
{"title":"A methodology for process design kit re-centering using TCAD and experimental data for cryogenic temperatures","authors":"Tapas Dutta , Fikru Adamu-Lema , Djamel Bensouiah , Asen Asenov","doi":"10.1016/j.sse.2025.109306","DOIUrl":"10.1016/j.sse.2025.109306","url":null,"abstract":"<div><div>In this work, we describe and demonstrate a novel Technology Computer Aided Design (TCAD) driven methodology to re-center room-temperature Process Design Kits (PDKs) for cryogenic operation using a limited set of experimental measurements. Unlike previous approaches that relied on direct fitting of sparse measurements, our technique accounts for process-induced deviations by calibrating TCAD models to both room-temperature and cryogenic data. Compact models for all process corners are extracted from TCAD-generated target characteristics, enabling accurate cryogenic modeling without dedicated foundry support. This scalable, technology-independent method provides a practical path for cryogenic circuit design.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109306"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145683774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-20DOI: 10.1016/j.sse.2025.109316
Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen
This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μeff) calculated from the ratio ID/(VG–VT) at low drain voltage; field-effect mobility (μFE) obtained from the transconductance in the linear regime; low-field mobility (μo) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of gm. The results consistently followed the trend μeff > μFE > μo, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (VT), subthreshold swing (SS), transconductance (gm), DIBL, output conductance (gD), Early voltage (VEA), and intrinsic gain (AV) were also evaluated, confirming that temperature and geometry critically influence device performance.
{"title":"Geometrical and thermal effects on mobility and analog parameters of AlGaN/GaN HEMTs on silicon substrates","authors":"Maria Glória Caño de Andrade , Braz Baptista Júnior , Eduardo Canga Panzo , Rodrigo T. Doria , Renan Trevisoli , Eddy Simoen","doi":"10.1016/j.sse.2025.109316","DOIUrl":"10.1016/j.sse.2025.109316","url":null,"abstract":"<div><div>This work investigates how temperature and channel geometry affect the analog performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon. Devices with varying lengths and widths were characterized across a temperature range from −35 °C to 25 °C. Four different methods were used to extract the carrier mobility: effective mobility (μ<sub>eff</sub>) calculated from the ratio I<sub>D</sub>/(V<sub>G</sub>–V<sub>T</sub>) at low drain voltage; field-effect mobility (μ<sub>FE</sub>) obtained from the transconductance in the linear regime; low-field mobility (μ<sub>o</sub>) estimated from the drift–diffusion model; and peak transconductance mobility derived from the maximum value of g<sub>m</sub>. The results consistently followed the trend μ<sub>eff</sub> > μ<sub>FE</sub> > μ<sub>o</sub>, and all mobilities showed degradation with increasing temperature due to enhanced phonon scattering. Key parameters such as threshold voltage (V<sub>T</sub>), subthreshold swing (SS), transconductance (g<sub>m</sub>), DIBL, output conductance (g<sub>D</sub>), Early voltage (V<sub>EA</sub>), and intrinsic gain (A<sub>V</sub>) were also evaluated, confirming that temperature and geometry critically influence device performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109316"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145840714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-01Epub Date: 2025-12-18DOI: 10.1016/j.sse.2025.109315
Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui
This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.
{"title":"1T-DRAM with retrograde doping","authors":"Maki Ulla , MD Yasir Bashir , Mohammad Jawaid Siddiqui","doi":"10.1016/j.sse.2025.109315","DOIUrl":"10.1016/j.sse.2025.109315","url":null,"abstract":"<div><div>This work presents a 1T-DRAM design based on a double-gate junctionless (DGJL) transistor with retrograde doping (RD), aimed at improving charge storage and scaling. The retrograde doping profile changes the carrier distribution in the channel, creating a strong electric field gradient near the drain when voltage is applied. This strong electric field causes sharp band bending, which reduces the tunneling barrier width and increases lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) current. As a result, efficient holes generated in the channel at lower write voltages with a retention time of up to 80 ms at ultra short gate length of 20 nm. The proposed DGJL RD-based 1T-DRAM is analyzed using well calibrated 2D TCAD simulation. Furthermore, the effects of work function, gate length, temperature, and doping level on retention time and sense margin are also studied, showing the potential of this design for low-power and highly scalable memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109315"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145840715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.
在这项工作中，我们提出了一种基于紧密结合方法（TBM）的算法，通过在紧密结合（TB）哈密顿量中包含与掺杂相关的自能校正项，来考虑通道掺杂对超薄体（UTB）双栅（DG）绝缘体上硅（SOI） MOS器件的能带结构和带隙的影响。首先，我们以现有的带隙缩小（BGN）模型为参考，确定室温下厚度和本征SOI通道（43 nm，量子约束效应可以忽略）的紧密结合哈密顿量中包含的自能量修正项，以确保n和p型掺杂的影响可以准确考虑。通过使用相同的自能校正项，同时也包括温度相关的带隙校正，然后我们量化了在大范围的器件温度（15 K - 300 K）、沟道厚度和掺杂密度下带隙缩小的程度。通过用泊松方程求解带结构的自洽解，进一步评价了这些器件的通道静电特性。此外，通过基于带结构的仿真方法，我们提出了考虑通道掺杂、厚度和器件温度变化的带隙模型。
{"title":"Unified approach for considering the effect of doping and device temperature on the band structure and electrostatics of UTB SOI DG MOS devices","authors":"Yogesh Dhote, Nalin Vilochan Mishra, Aditya Sankar Medury","doi":"10.1016/j.sse.2025.109313","DOIUrl":"10.1016/j.sse.2025.109313","url":null,"abstract":"<div><div>In this work, we present a tight-binding method (TBM) based algorithm to consider the effects of channel doping on the band structure and the band gap of an Ultra-Thin Body (UTB) Double Gate (DG) Silicon-on-Insulator (SOI) MOS device, through the inclusion of doping dependent self energy correction terms in the tight-binding (TB) Hamiltonian. Firstly, we use the existing Band gap Narrowing (BGN) models as a reference and determine the self-energy correction terms to be included in the Tight-Binding Hamiltonian of a thick and intrinsic SOI channel (43 nm, where quantum confinement effects are negligible) at room temperature, to ensure that the effects of n and p type doping can be accurately taken into account. By using the same self-energy correction terms, while also now including a temperature dependent band gap correction, we then quantify the extent of band gap narrowing for a wide range of device temperatures (15 K - 300 K), channel thicknesses and doping densities. We further evaluate the channel electrostatics of these devices through the self-consistent solution of the band structure with the Poisson’s equation. Also by using the band structure based simulation approach, we then propose a model for the band gap considering channel doping, thickness and device temperature variations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109313"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145738146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work employs a two-stage low temperature defect reduction annealing treatment for oxidation state modulation and defect reduction of stannous oxide (SnO) thin-film transistors (TFTs). With higher Sn2+ proportion and fewer defects, the device stability and carrier mobility of p-type SnO TFTs are improved. The SnO TFTs with two-stage low temperature defect reduction annealing exhibit an on/off ratio of 1.22 × 104, a field-effect mobility of 0.44 cm2/V·s, a 50.2 % reduction in IOFF, without subthreshold swing degradation. With the detailed material analysis, the internal physical mechanism of the defect reduction in of SnO is well discussed. The discoveries presented in this work are expected to provide technical methodologies for the high-performance TFTs.
{"title":"Oxidation state modulation for p-Type stannous oxide with Two-Stage low temperature defect reduction annealing","authors":"Zhibo Zeng , Kai-Jhih Gan , Wenjie Lei , Shiyu Zeng , Jialong Xiang , Bojun Zhang , Kuei-Shu Chang-Liao , Cheng-Chang Yu , Po-Chung Huang , Dun-Bao Ruan","doi":"10.1016/j.sse.2025.109308","DOIUrl":"10.1016/j.sse.2025.109308","url":null,"abstract":"<div><div>This work employs a two-stage low temperature defect reduction annealing treatment for oxidation state modulation and defect reduction of stannous oxide (SnO) thin-film transistors (TFTs). With higher Sn<sup>2+</sup> proportion and fewer defects, the device stability and carrier mobility of p-type SnO TFTs are improved. The SnO TFTs with two-stage low temperature defect reduction annealing exhibit an on/off ratio of 1.22 × 10<sup>4</sup>, a field-effect mobility of 0.44 cm<sup>2</sup>/V·s, a 50.2 % reduction in I<sub>OFF</sub>, without subthreshold swing degradation. With the detailed material analysis, the internal physical mechanism of the defect reduction in of SnO is well discussed. The discoveries presented in this work are expected to provide technical methodologies for the high-performance TFTs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"232 ","pages":"Article 109308"},"PeriodicalIF":1.4,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145652096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-11-05DOI: 10.1016/j.sse.2025.109288
Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński
In this work, we present the investigation of resistive switching properties in Ag/SiOx/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.
{"title":"Investigation of compliance current effect on resistive switching properties in Ag/SiOx/Cr RRAM devices","authors":"Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński","doi":"10.1016/j.sse.2025.109288","DOIUrl":"10.1016/j.sse.2025.109288","url":null,"abstract":"<div><div>In this work, we present the investigation of resistive switching properties in Ag/SiO<sub>x</sub>/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109288"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145517352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-01Epub Date: 2025-09-18DOI: 10.1016/j.sse.2025.109247
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
In this work, different Y-function methodologies for the extraction of the electrical MOSFET parameters permitting to model the current–voltage (I–V) transfer characteristics from weak to strong inversion in ohmic mode of operation are compared on ideal I–V characteristics analytically constructed. It is evidenced that even if important discrepancies between the values of the estimated parameters using these methodologies exist, the access resistances value may be predicted with good accuracy. It is demonstrated that if the inversion charge is calculated by combining its asymptotic laws in weak and in strong inversion, this approximation will lead to an about 20% model-induced error in the moderate inversion range.
It is proved that the Y-function strategy which permits the best agreement between the extracted parameter values and the reference ones may be a solution to foresee with lower error the inversion charge behavior from weak to strong inversion even without performing capacitance–voltage measurements.
{"title":"Model and parameter extraction strategy impact on the estimated values of MOSFET parameters in ohmic operation","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109247","DOIUrl":"10.1016/j.sse.2025.109247","url":null,"abstract":"<div><div>In this work, different Y-function methodologies for the extraction of the electrical MOSFET parameters permitting to model the current–voltage (I–V) transfer characteristics from weak to strong inversion in ohmic mode of operation are compared on ideal I–V characteristics analytically constructed. It is evidenced that even if important discrepancies between the values of the estimated parameters using these methodologies exist, the access resistances value may be predicted with good accuracy. It is demonstrated that if the inversion charge is calculated by combining its asymptotic laws in weak and in strong inversion, this approximation will lead to an about 20% model-induced error in the moderate inversion range.</div><div>It is proved that the Y-function strategy which permits the best agreement between the extracted parameter values and the reference ones may be a solution to foresee with lower error the inversion charge behavior from weak to strong inversion even without performing capacitance–voltage measurements.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109247"},"PeriodicalIF":1.4,"publicationDate":"2026-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145327383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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