Pub Date : 2025-11-15DOI: 10.1016/j.sse.2025.109293
M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska
This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.
{"title":"Effect of PN passivation on MOSFETs performance in 28 nm FD-SOI","authors":"M. Vanbrabant , M. Rack , A. Cathelin , J.-P. Raskin , V. Kilchytska","doi":"10.1016/j.sse.2025.109293","DOIUrl":"10.1016/j.sse.2025.109293","url":null,"abstract":"<div><div>This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109293"},"PeriodicalIF":1.4,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-11DOI: 10.1016/j.sse.2025.109292
Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan
For emerging 5G millimeter-wave base stations and automotive radar systems operating in the V/W bands, suppressing gate leakage currents in AlInGaN/GaN MIS capacitors is critical to mitigate energy losses exceeding 15 % and thermal runaway risks under high-power RF conditions. This study systematically investigates the leakage mechanisms in AlInGaN/GaN Metal-Insulator-Semiconductor (MIS) capacitors, focusing on the influence of electrode geometry. We analyze the factors governing leakage behavior by fabricating devices with a series of electrode dimensions and spacings, and conducting comprehensive current–voltage (I-V) and capacitance–voltage (C-V) measurements. The results demonstrate that reducing electrode spacing intensifies local electric field concentration, enhancing trap-assisted tunneling at the interface and thereby increasing leakage current density. Conversely, increasing electrode size and spacing improves the uniformity of the electric field distribution and significantly mitigates the leakage currents. In addition, C-V measurement shows that the Si3N4 passivation process can effectively suppress the defects of the heterojunction interface. After passivation, the interface state density decreases to 6.1 × 1011 cm−2 eV−1. Further analysis elucidates the voltage-dependent nature of leakage mechanisms: ohmic conduction dominates in low-field regions, while Schottky emission and Frenkel-Poole emission contribute in medium-to-high fields, with Fowler-Nordheim tunneling prevails under high electric fields. These findings emphasize the critical role of optimizing electrode geometries and interface passivation strategies in enhancing device reliability. This work provides theoretical insights and experimental guidance for advancing high-frequency, high-power GaN-based devices for emerging applications in communications and RF technologies.
{"title":"Analysis of leakage current mechanisms in AlInGaN/GaN metal-insulator-semiconductor capacitors","authors":"Guiyu Shen , Ying Wang , Yulong Fang , Yongchuan Tang , He Guan","doi":"10.1016/j.sse.2025.109292","DOIUrl":"10.1016/j.sse.2025.109292","url":null,"abstract":"<div><div>For emerging 5G millimeter-wave base stations and automotive radar systems operating in the V/W bands, suppressing gate leakage currents in AlInGaN/GaN MIS capacitors is critical to mitigate energy losses exceeding 15 % and thermal runaway risks under high-power RF conditions. This study systematically investigates the leakage mechanisms in AlInGaN/GaN Metal-Insulator-Semiconductor (MIS) capacitors, focusing on the influence of electrode geometry. We analyze the factors governing leakage behavior by fabricating devices with a series of electrode dimensions and spacings, and conducting comprehensive current–voltage (I-V) and capacitance–voltage (C-V) measurements. The results demonstrate that reducing electrode spacing intensifies local electric field concentration, enhancing trap-assisted tunneling at the interface and thereby increasing leakage current density. Conversely, increasing electrode size and spacing improves the uniformity of the electric field distribution and significantly mitigates the leakage currents. In addition, C-V measurement shows that the Si<sub>3</sub>N<sub>4</sub> passivation process can effectively suppress the defects of the heterojunction interface. After passivation, the interface state density decreases to 6.1 × 10<sup>11</sup> cm<sup>−2</sup> eV<sup>−1</sup>. Further analysis elucidates the voltage-dependent nature of leakage mechanisms: ohmic conduction dominates in low-field regions, while Schottky emission and Frenkel-Poole emission contribute in medium-to-high fields, with Fowler-Nordheim tunneling prevails under high electric fields. These findings emphasize the critical role of optimizing electrode geometries and interface passivation strategies in enhancing device reliability. This work provides theoretical insights and experimental guidance for advancing high-frequency, high-power GaN-based devices for emerging applications in communications and RF technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109292"},"PeriodicalIF":1.4,"publicationDate":"2025-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1016/j.sse.2025.109290
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances (). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.
{"title":"In-depth DC characterization of asymmetric vertical nanowire Accumulation-Mode junctionless GAA pMOSFETs on SOI from 300 K to 400 K","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109290","DOIUrl":"10.1016/j.sse.2025.109290","url":null,"abstract":"<div><div>In this article, we present an in-depth investigation of the direct current (DC) characteristics of asymmetric vertical nanowire (VNW) accumulation-mode junctionless (JL) gate-all-around (GAA) pMOSFETs fabricated on silicon-on-insulator (SOI) substrates. Measurements were performed over a temperature range from 300 K to 400 K in both linear and saturation regimes. Our results reveal significant temperature and polarization-dependent behaviors. It has been demonstrated that the nanowire diameter impacts the DC performance. A nanowire diameter larger than 20 nm leads to a significant increase in off-state leakage current and a higher on-state drive current compared to smaller diameters. Although a larger diameter improves the on-state current, it degrades the subthreshold swing (SS), indicating weaker electrostatic control. Furthermore, using the top electrode as either the drain (forward operation mode) or the source (reverse operation mode) significantly affects device performance due to their asymmetric architecture. In the forward mode, a higher off-state leakage current is observed, while in the reverse mode, the on-state saturation current is higher. This asymmetry may be attributed to asymmetric access resistances (<span><math><mrow><msub><mi>R</mi><mi>S</mi></msub><mspace></mspace><mo>></mo><mspace></mspace><msub><mi>R</mi><mi>D</mi></msub></mrow></math></span>). From high-temperature measurements, using different series-resistance-free parameter-extraction (Y-function-based) methodologies, it is observed that the series resistance of the devices remains unchanged, and the low-field mobility is mainly limited by Coulomb scattering. This study provides a better understanding of the behavior and performance of VNW accumulation-mode JL GAA pMOSFETs and paves the way for further optimization.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109290"},"PeriodicalIF":1.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The impact of Ionizing Radiation (IR) dose on interface trap state generation is critical to consider in Ultra-Thin (UT) Silicon-on-Insulator (SOI) MOS devices, where these radiation-induced interface traps are likely to have a significant effect on the reliability of these devices. Additionally, in these devices, the effect of Quantum Confinement also needs to be properly considered to ensure an accurate analysis of device tolerance to radiation. Therefore, in this work, we present a band structure-based simulation approach to accurately quantify the maximum extent of radiation-induced (, proton, , X-rays) interface traps and their degradation on these devices for various SOI channel thicknesses. Through this analysis, we then determine the practical radiation tolerance of these devices for various IR, with the consideration of partial recovery when subjected to continuous stress, and show the impact of QCEs on key electrostatic parameters such as threshold voltage and gate capacitance.
{"title":"Band structure-based methodology for analysis of radiation-induced interface traps on reliability of UTB MOS devices","authors":"Nalin Vilochan Mishra, Yogesh Dhote, Aditya Sankar Medury","doi":"10.1016/j.sse.2025.109289","DOIUrl":"10.1016/j.sse.2025.109289","url":null,"abstract":"<div><div>The impact of Ionizing Radiation (IR) dose on interface trap state generation is critical to consider in Ultra-Thin (UT) Silicon-on-Insulator (SOI) MOS devices, where these radiation-induced interface traps are likely to have a significant effect on the reliability of these devices. Additionally, in these devices, the effect of Quantum Confinement also needs to be properly considered to ensure an accurate analysis of device tolerance to radiation. Therefore, in this work, we present a band structure-based simulation approach to accurately quantify the maximum extent of radiation-induced (<span><math><mi>α</mi></math></span>, proton, <span><math><mi>γ</mi></math></span>, X-rays) interface traps and their degradation on these devices for various SOI channel thicknesses. Through this analysis, we then determine the practical radiation tolerance of these devices for various IR, with the consideration of partial recovery when subjected to continuous stress, and show the impact of QCEs on key electrostatic parameters such as threshold voltage and gate capacitance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109289"},"PeriodicalIF":1.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1016/j.sse.2025.109287
Tiexin Zhang , Fanyu Liu , Lei Shu , Bo Li , Zhengsheng Han , Tianchun Ye
Based on SOI Pseudo-MOS, an equivalent circuit model of non-equilibrium body potential (Vneq) is proposed. The non-equilibrium majority carriers cannot be neglected to interpret the mechanism of Vneq. An accurate mathematical Vneq is determined through bringing non-equilibrium majority carriers into the discrete Poisson equation, which is validated by TCAD simulations.
{"title":"A mathematical model for non-equilibrium body potential of SOI Pseudo-MOS and physical mechanism analysis","authors":"Tiexin Zhang , Fanyu Liu , Lei Shu , Bo Li , Zhengsheng Han , Tianchun Ye","doi":"10.1016/j.sse.2025.109287","DOIUrl":"10.1016/j.sse.2025.109287","url":null,"abstract":"<div><div>Based on SOI Pseudo-MOS, an equivalent circuit model of non-equilibrium body potential (<em>V</em><sub>neq</sub>) is proposed. The non-equilibrium majority carriers cannot be neglected to interpret the mechanism of <em>V</em><sub>neq.</sub> An accurate mathematical <em>V</em><sub>neq</sub> is determined through bringing non-equilibrium majority carriers into the discrete Poisson equation, which is validated by TCAD simulations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109287"},"PeriodicalIF":1.4,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145569166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.sse.2025.109288
Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński
In this work, we present the investigation of resistive switching properties in Ag/SiOx/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.
{"title":"Investigation of compliance current effect on resistive switching properties in Ag/SiOx/Cr RRAM devices","authors":"Piotr Wiśniewski , Piotr Jeżak , Aleksander Małkowski , Alicja Kądziela , Jakub Krzemiński , Robert Mroczyński","doi":"10.1016/j.sse.2025.109288","DOIUrl":"10.1016/j.sse.2025.109288","url":null,"abstract":"<div><div>In this work, we present the investigation of resistive switching properties in Ag/SiO<sub>x</sub>/Cr RRAM devices. We fabricate the devices and analyze the effect of compliance current on the device behavior. Electrical characterization reveals the bipolar and threshold switching depending on the value of compliance current. We use electrochemical impedance spectroscopy to obtain information about the forming process, exposing metal ions migration during the process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109288"},"PeriodicalIF":1.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145517352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.sse.2025.109291
Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian
This work is related to the analysis of Gate-All-Around Nanosheet (GAA-NSH) devices operating from 125 °C down to −100 °C, focusing on their analog potential. The Verilog-A model was developed using experimental data, and the two-stage operational transconductance amplifier (OTA) was designed for transistor efficiency (gm ⁄ IDS) of around 8 V−1 and supply voltage (VDD) of 1.8 V at room temperature. The OTA temperature influence was analyzed for different temperatures. When the temperature ranges from 125 °C to −100 °C, the OTA voltage gain improved from 63.2 to 72.4 dB and the gain bandwidth product (GBW) also improved from 354 to 460 MHz, considering that the bias circuit (ISS) is temperature-compensated (ISS and VCM are constant in the studied temperature range). The obtained results show that the nanosheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits in this temperature range.
{"title":"Nanosheet Transistor Applied in a Two-Stage Operational Transconductance Amplifier from 125 °C down to −100 °C","authors":"Thainá G. Guimarães , Welder F. Perina , Joao A. Martino , Paula G.D. Agopian","doi":"10.1016/j.sse.2025.109291","DOIUrl":"10.1016/j.sse.2025.109291","url":null,"abstract":"<div><div>This work is related to the analysis of Gate-All-Around Nanosheet (GAA-NSH) devices operating from 125 °C down to −100 °C, focusing on their analog potential. The Verilog-A model was developed using experimental data, and the two-stage operational transconductance amplifier (OTA) was designed for transistor efficiency (g<sub>m</sub> ⁄ I<sub>DS</sub>) of around 8 V<sup>−1</sup> and supply voltage (V<sub>DD</sub>) of 1.8 V at room temperature. The OTA temperature influence was analyzed for different temperatures. When the temperature ranges from 125 °C to −100 °C, the OTA voltage gain improved from 63.2 to 72.4 dB and the gain bandwidth product (GBW) also improved from 354 to 460 MHz, considering that the bias circuit (I<sub>SS</sub>) is temperature-compensated (I<sub>SS</sub> and V<sub>CM</sub> are constant in the studied temperature range). The obtained results show that the nanosheet can be used for analog circuits such as OTA, for application in mixed-signal integrated circuits in this temperature range.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109291"},"PeriodicalIF":1.4,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-02DOI: 10.1016/j.sse.2025.109283
Yitao Wang , Shuoxin Ji , Yang Wang
Due to the harsh working environments of Input/Output (I/O) pins, the electro-static discharge (ESD) protection devices of these ports often require high robustness. To design highly robust ESD protection devices with dual polarities, the Gate-controlled dual direction silicon controlled rectifier (GCDDSCR) and a DDSCR embedded with Schottky barrier diode (SBD-GCDDSCR) structures are designed and studied in this article as standalone devices for primary protection. The gate-controlled diodes and Schottky diodes are integrated into the simple DDSCR structure to enhance its robustness while reducing the on-resistance. The inclusion of gate diodes introduced an additional current path near the surface, improving space utilization in the longitudinal direction of the device, and the addition of Schottky junctions placed adjacent to the Anode and Cathode can provide additional electron extraction paths. Both methods contribute in a more uniform current distribution, improving the robustness of the device. Two-dimensional device simulation based on a classical set of equations was employed to investigate its electrical behavior during an ESD event. Based on the 0.18 μm CMOS process, all structures were fabricated into 6-finger devices with a finger length of 50 μm. The Transmission Line Pulse (TLP) testing method was used to evaluate their ESD characteristics, revealing that the addition of the gate-controlled diodes and Schottky shunt paths improved robustness. The proposed SBD-GCDDSCR structure demonstrated superior robustness under ESD stress, with a failure current exceeding 19 A in both forward and reverse directions, and its Vt2 in strong saturation regime is around 48 V.
{"title":"Design of high robustness DDSCR with embedded gate-controlled diodes and Schottky diodes","authors":"Yitao Wang , Shuoxin Ji , Yang Wang","doi":"10.1016/j.sse.2025.109283","DOIUrl":"10.1016/j.sse.2025.109283","url":null,"abstract":"<div><div>Due to the harsh working environments of Input/Output (I/O) pins, the electro-static discharge (ESD) protection devices of these ports often require high robustness. To design highly robust ESD protection devices with dual polarities, the Gate-controlled dual direction silicon controlled rectifier (GCDDSCR) and a DDSCR embedded with Schottky barrier diode (SBD-GCDDSCR) structures are designed and studied in this article as standalone devices for primary protection. The gate-controlled diodes and Schottky diodes are integrated into the simple DDSCR structure to enhance its robustness while reducing the on-resistance. The inclusion of gate diodes introduced an additional current path near the surface, improving space utilization in the longitudinal direction of the device, and the addition of Schottky junctions placed adjacent to the Anode and Cathode can provide additional electron extraction paths. Both methods contribute in a more uniform current distribution, improving the robustness of the device. Two-dimensional device simulation based on a classical set of equations was employed to investigate its electrical behavior during an ESD event. Based on the 0.18 μm CMOS process, all structures were fabricated into 6-finger devices with a finger length of 50 μm. The Transmission Line Pulse (TLP) testing method was used to evaluate their ESD characteristics, revealing that the addition of the gate-controlled diodes and Schottky shunt paths improved robustness. The proposed SBD-GCDDSCR structure demonstrated superior robustness under ESD stress, with a failure current exceeding 19 A in both forward and reverse directions, and its V<sub>t2</sub> in strong saturation regime is around 48 V.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109283"},"PeriodicalIF":1.4,"publicationDate":"2025-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01DOI: 10.1016/j.sse.2025.109270
Kosuke Yamaguchi, Satofumi Souma
We propose an efficient device-circuit co-simulation framework for phosphorene tunnel FETs, focusing on circuit-level impacts of structural imperfections such as grain boundaries and adsorption. A fast table-generation scheme based on the scattering matrix approach and a capacitance model enables physically grounded current and capacitance characteristics to be obtained across bias conditions. These tables are smoothly integrated into SPICE simulations via Verilog-A, naturally capturing effects such as DIBL and intrinsic capacitances. Using this framework, we demonstrate the sensitivity of inverter and ring oscillator performance to the magnitude and position of grain boundaries, highlighting their role as a major source of variability in 2D TFET circuits. Overall, the framework provides a practical and extensible platform for evaluating low-power 2D devices under realistic variability.
{"title":"Scattering matrix-based low computational cost model for the device and circuit co-simulation of phosphorene tunnel field-effect transistors","authors":"Kosuke Yamaguchi, Satofumi Souma","doi":"10.1016/j.sse.2025.109270","DOIUrl":"10.1016/j.sse.2025.109270","url":null,"abstract":"<div><div>We propose an efficient device-circuit co-simulation framework for phosphorene tunnel FETs, focusing on circuit-level impacts of structural imperfections such as grain boundaries and adsorption. A fast table-generation scheme based on the scattering matrix approach and a capacitance model enables physically grounded current and capacitance characteristics to be obtained across bias conditions. These tables are smoothly integrated into SPICE simulations via Verilog-A, naturally capturing effects such as DIBL and intrinsic capacitances. Using this framework, we demonstrate the sensitivity of inverter and ring oscillator performance to the magnitude and position of grain boundaries, highlighting their role as a major source of variability in 2D TFET circuits. Overall, the framework provides a practical and extensible platform for evaluating low-power 2D devices under realistic variability.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109270"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Schottky barrier photodetectors (SBPDs) have low-cost fabrication, CMOS compatibility, and scalability. This work presents a comparative analysis of Cu/n-Si Schottky photodetectors fabricated using two distinct copper deposition techniques: thermal evaporation and RF sputtering. Comparative analyses were conducted using field-emission scanning electron microscopy (FE-SEM), electrical I–V measurements, responsivity analysis, and time-resolved photocurrent studies. Morphological characterization revealed that thermally evaporated films formed larger, anisotropic grains, whereas RF-sputtered films exhibited finer and more uniform grain structures. Devices fabricated via RF sputtering exhibited superior electrical and optoelectronic performance with higher photocurrent, enhanced responsivity (up to 0.146 A/W under 532 nm illumination and 0.038 A/W under 650 nm illumination), and faster, more stable photoresponses—even under zero-bias conditions. These results demonstrate the significant role of deposition technique in tuning microstructure and optimizing photodetector efficiency for low-power sensing applications.
{"title":"Enhanced photoresponse in Cu/n-Si Schottky photodetectors via RF sputtering: A comparative study with thermal evaporation","authors":"Rajat Kumar Goyal , Madhuram Mishra , Pragya Kushwaha , Sunil Babu Eadi , Harshit Agarwal","doi":"10.1016/j.sse.2025.109268","DOIUrl":"10.1016/j.sse.2025.109268","url":null,"abstract":"<div><div>Schottky barrier photodetectors (SBPDs) have low-cost fabrication, CMOS compatibility, and scalability. This work presents a comparative analysis of Cu/n-Si Schottky photodetectors fabricated using two distinct copper deposition techniques: thermal evaporation and RF sputtering. Comparative analyses were conducted using field-emission scanning electron microscopy (FE-SEM), electrical I–V measurements, responsivity analysis, and time-resolved photocurrent studies. Morphological characterization revealed that thermally evaporated films formed larger, anisotropic grains, whereas RF-sputtered films exhibited finer and more uniform grain structures. Devices fabricated via RF sputtering exhibited superior electrical and optoelectronic performance with higher photocurrent, enhanced responsivity (up to 0.146 A/W under 532 nm illumination and 0.038 A/W under 650 nm illumination), and faster, more stable photoresponses—even under zero-bias conditions. These results demonstrate the significant role of deposition technique in tuning microstructure and optimizing photodetector efficiency for low-power sensing applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109268"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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