Pub Date : 2025-01-27DOI: 10.1016/j.sse.2025.109069
Lukas Wind , Stefan Preiß , Daniele Nazzari , Johannes Aberl , Enrique Prado Navarrete , Moritz Brehm , Lilian Vogl , Andrew M. Minor , Masiar Sistani , Walter M. Weber
We study the monolithic quasi-ohmic contact formation with single-elementary Al to GeSn channel devices with various Sn concentrations between 0.5 % and 4 %. Thereby we investigate the influence of increasing Sn content on the electrical transport properties in field-effect transistors for a wide temperature range between 77 K and 400 K. At low temperatures, the devices exhibit improved performance metrics, promising for cryo-CMOS applications. Compared to pure Ge control devices, the introduction of Sn into the channel leads to a 20 times increased on-current. In a multi-gate architecture, we analyze the decoupled influence of the carrier injection through the metal–semiconductor junction and the channel conduction.
{"title":"Si/Ge1−xSnx/Si transistors with highly transparent Al contacts","authors":"Lukas Wind , Stefan Preiß , Daniele Nazzari , Johannes Aberl , Enrique Prado Navarrete , Moritz Brehm , Lilian Vogl , Andrew M. Minor , Masiar Sistani , Walter M. Weber","doi":"10.1016/j.sse.2025.109069","DOIUrl":"10.1016/j.sse.2025.109069","url":null,"abstract":"<div><div>We study the monolithic quasi-ohmic contact formation with single-elementary Al to Ge<span><math><msub><mrow></mrow><mrow><mn>1</mn><mo>−</mo><mi>x</mi></mrow></msub></math></span>Sn<span><math><msub><mrow></mrow><mrow><mi>x</mi></mrow></msub></math></span> channel devices with various Sn concentrations between 0.5<!--> <!-->% and 4<!--> <!-->%. Thereby we investigate the influence of increasing Sn content on the electrical transport properties in field-effect transistors for a wide temperature range between 77<!--> <!-->K and 400<!--> <!-->K. At low temperatures, the devices exhibit improved performance metrics, promising for cryo-CMOS applications. Compared to pure Ge control devices, the introduction of Sn into the channel leads to a 20 times increased on-current. In a multi-gate architecture, we analyze the decoupled influence of the carrier injection through the metal–semiconductor junction and the channel conduction.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109069"},"PeriodicalIF":1.4,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cadmium oxide is among the most appealing materials since it may be utilized in a variety of applications, including photodetector. Al/La-Zn/co-doped CdO/p-type Si/Al photodetectors were fabricated using the sol–gel spin coat technique, with the CdO interface layer, varying concentrations of La (0.1, 0.5, 2, and 4 at%), and constant Zn (1 at%). Each film was grown on glass and silicon substrates so that their optical and electrical properties could be evaluated. Analyses were conducted on the morphological, optical, and electrical properties of transparent, co-doped CdO photodetectors. Using a field emission scanning electron microscope and energy dispersive X-ray, the morphological properties and elemental compositions of prepared materials The FESEM images revealed a 3-D micro/nanostructure of La/Zn-co-CdO form, characterized by the formation of microspheres by the use of nanoneedles. Additionally, the development rate of the films was observed to be inhibited by the co-doping of CdO with La-Zn. The transmittance measurements show that the prepared films exhibit a ranging from 40 to 70 % in the visible spectrum. The optical bandgap of prepared thin films measured by linear fitting where increases linearly with increasing La-Zn co-dopant concentration and was found in range between (2.07 and 2.27 eV). When CdO was co-doped with La (0.1 at%) and Zn (1 at%), the I-V properties of the produced photodetectors revealed high rectifying behavior. The photovoltaic and photoelectrical behaviors are shown, together with associated parameters. Additionally, the dopant concentration of (La 0.1 and Zn 1) at% has the highest photoresponse behavior at about 4085, surpassing findings in prior research. The highest photosensitivity of 6.3 × 10−4 has been determined for La 0.1 and Zn 1) at%. The strong rectifying characteristics, together with the photovoltaic, photoelectrical, and photoresponse properties, indicate that the fabricated (La 0.1 and Zn 1) at% co-doped CdO-based photodetector is suitable for optoelectronic applications, particularly in sensors and photodetectors.
{"title":"3D (micro/nano) CdO/p-Si co-doped Zn and La heterojunctions perform as solar light photodetectors","authors":"Bestoon Anwer Gozeh , Lary H. Slewa , Cheman Baker Ismael , Sarwar Ibrahim Saleh , Abdulkadir Yildiz , Fahrettin Yakuphanoglu","doi":"10.1016/j.sse.2025.109078","DOIUrl":"10.1016/j.sse.2025.109078","url":null,"abstract":"<div><div>Cadmium oxide is among the most appealing materials since it may be utilized in a variety of applications, including photodetector. Al/La-Zn/co-doped CdO/p-type Si/Al photodetectors were fabricated using the sol–gel spin coat technique, with the CdO interface layer, varying concentrations of La (0.1, 0.5, 2, and 4 at%), and constant Zn (1 at%). Each film was grown on glass and silicon substrates so that their optical and electrical properties could be evaluated. Analyses were conducted on the morphological, optical, and electrical properties of transparent, co-doped CdO photodetectors. Using a field emission scanning electron microscope and energy dispersive X-ray, the morphological properties and elemental compositions of prepared materials The FESEM images revealed a 3-D micro/nanostructure of La/Zn-co-CdO form, characterized by the formation of microspheres by the use of nanoneedles. Additionally, the development rate of the films was observed to be inhibited by the co-doping of CdO with La-Zn. The transmittance measurements show that the prepared films exhibit a ranging from 40 to 70 % in the visible spectrum. The optical bandgap of prepared thin films measured by linear fitting where increases linearly with increasing La-Zn co-dopant concentration and was found in range between (2.07 and 2.27 <!--> <!-->eV). When CdO was co-doped with La (0.1 at%) and Zn (1 at%), the I-V properties of the produced photodetectors revealed high rectifying behavior. The photovoltaic and photoelectrical behaviors are shown, together with associated parameters. Additionally, the dopant concentration of (La 0.1 and Zn 1) at% has the highest photoresponse behavior at about 4085, surpassing findings in prior research. The highest photosensitivity of 6.3 × 10<sup>−4</sup> has been determined for La 0.1 and Zn 1) at%. The strong rectifying characteristics, together with the photovoltaic, photoelectrical, and photoresponse properties, indicate that the fabricated (La 0.1 and Zn 1) at% co-doped CdO-based photodetector is suitable for optoelectronic applications, particularly in sensors and photodetectors.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109078"},"PeriodicalIF":1.4,"publicationDate":"2025-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1016/j.sse.2025.109076
Priya Terdalkar , Dhananjay D. Kumbhar , Somnath D. Pawar , Kiran A. Nirmal , Tae Geun Kim , Shaibal Mukherjee , Kishorkumar V. Khot , Tukaram D. Dongale
Complex information processing in neuromorphic systems relies on artificial neurons and synapses as fundamental components. Frequently, memristors are utilized as artificial synapses due to their straightforward configurations, capacity for gradual conductance modulation, and compatibility with high-density integration. The present study reports a novel Ag/Bi2S3/FTO memristor, fabricated using the arrested precipitation technique (APT) based solution processable method. Characterization techniques, including XRD, Raman scattering, and FESEM with EDS, were employed to evaluate the properties of Bi2S3. The device exhibited robust, forming-free, non-volatile resistive switching at low voltages (SET: −0.58 V and RESET: 0.42 V) with an endurance exceeding 6 x 103 cycles and retention times greater than 1.5 x 104 s. Moreover, switching variability was modeled using different statistical distribution techniques. It can mimic learning and forgetting behaviors and different forms of spike-timing-dependent plasticity, akin to its biological counterpart. The trap-filled SCLC mechanism dominated the charge transport in the device. This work introduces new material for investigating low-power consuming electronic devices which holds significant potential for future applications in artificial intelligence electronics and neuromorphic computing systems.
{"title":"Revealing switching statistics and artificial synaptic properties of Bi2S3 memristor","authors":"Priya Terdalkar , Dhananjay D. Kumbhar , Somnath D. Pawar , Kiran A. Nirmal , Tae Geun Kim , Shaibal Mukherjee , Kishorkumar V. Khot , Tukaram D. Dongale","doi":"10.1016/j.sse.2025.109076","DOIUrl":"10.1016/j.sse.2025.109076","url":null,"abstract":"<div><div>Complex information processing in neuromorphic systems relies on artificial neurons and synapses as fundamental components. Frequently, memristors are utilized as artificial synapses due to their straightforward configurations, capacity for gradual conductance modulation, and compatibility with high-density integration. The present study reports a novel Ag/Bi<sub>2</sub>S<sub>3</sub>/FTO memristor, fabricated using the arrested precipitation technique (APT) based solution processable method. Characterization techniques, including XRD, Raman scattering, and FESEM with EDS, were employed to evaluate the properties of Bi<sub>2</sub>S<sub>3</sub>. The device exhibited robust, forming-free, non-volatile resistive switching at low voltages (SET: −0.58 V and RESET: 0.42 V) with an endurance exceeding 6 x 10<sup>3</sup> cycles and retention times greater than 1.5 x 104 s. Moreover, switching variability was modeled using different statistical distribution techniques. It can mimic learning and forgetting behaviors and different forms of spike-timing-dependent plasticity, akin to its biological counterpart. The trap-filled SCLC mechanism dominated the charge transport in the device. This work introduces new material for investigating low-power consuming electronic devices which holds significant potential for future applications in artificial intelligence electronics and neuromorphic computing systems.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109076"},"PeriodicalIF":1.4,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-24DOI: 10.1016/j.sse.2025.109075
Yeting Tao, Yuying Wu, Yaotian Zhang, Jingsheng Wang, Youtian Tao
Two bipolar host materials, TCTA-3CN and TCTA-4CN, are developed by incorporating strong electron-withdrawing cyano groups at the 3- or 4-position of carbazole in classical hole-transport tris(4-carbazoyl-9-ylphenyl)amine (TCTA). Their HOMO/LUMO energy levels were significantly reduced to −5.56/−2.32 eV and −5.60/−2.48 eV, respectively, compared to −5.19/−1.92 eV for TCTA. This CN-modification results in a markedly improved carrier balance, as evidenced by a reduction in the hole/electron current ratio from >16,000 for TCTA to ∼45 for both TCTA-3CN and TCTA-4CN in the corresponding single-carrier devices at 4 V. When utilized as host materials for (ppy)2Ir(acac) based devices, a synergistic enhancement in luminescence and efficiency was observed.
{"title":"Balancing carrier injection/transport through CN-modification on classical hole-transport host for enhanced performance in phosphorescent OLEDs","authors":"Yeting Tao, Yuying Wu, Yaotian Zhang, Jingsheng Wang, Youtian Tao","doi":"10.1016/j.sse.2025.109075","DOIUrl":"10.1016/j.sse.2025.109075","url":null,"abstract":"<div><div>Two bipolar host materials, TCTA-3CN and TCTA-4CN, are developed by incorporating strong electron-withdrawing cyano groups at the 3- or 4-position of carbazole in classical hole-transport tris(4-carbazoyl-9-ylphenyl)amine (TCTA). Their HOMO/LUMO energy levels were significantly reduced to −5.56/−2.32 eV and −5.60/−2.48 eV, respectively, compared to −5.19/−1.92 eV for TCTA. This CN-modification results in a markedly improved carrier balance, as evidenced by a reduction in the hole/electron current ratio from >16,000 for TCTA to ∼45 for both TCTA-3CN and TCTA-4CN in the corresponding single-carrier devices at 4 V. When utilized as host materials for (ppy)<sub>2</sub>Ir(acac) based devices, a synergistic enhancement in luminescence and efficiency was observed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109075"},"PeriodicalIF":1.4,"publicationDate":"2025-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-23DOI: 10.1016/j.sse.2025.109072
Yeeun Kim , Jaejoong Jeong , Seul Ki Hong , Byung Jin Cho , Jong Kyung Park
This paper addresses the challenge of declining cell current in 3D NAND Flash memory. We propose a novel approach to deposit a positive fixed oxide charge on the backside adjacent to the filler oxide after forming a poly-Si channel, effectively improving the cell current flow within the entire string. Through TCAD simulations and experimental device fabrication, we demonstrate a significant enhancement in cell current by approximately 30%. Furthermore, we analyze the impact of positive fixed charge on channel current and investigate the influence of Poly-Si channel thickness and liner oxide thickness on current improvement. Our findings indicate promising avenues for improving 3D NAND Flash memory technology, contributing to its continued advancement in the future.
{"title":"Improving cell current in 3D NAND flash memory with fixed oxide charge","authors":"Yeeun Kim , Jaejoong Jeong , Seul Ki Hong , Byung Jin Cho , Jong Kyung Park","doi":"10.1016/j.sse.2025.109072","DOIUrl":"10.1016/j.sse.2025.109072","url":null,"abstract":"<div><div>This paper addresses the challenge of declining cell current in 3D NAND Flash memory. We propose a novel approach to deposit a positive fixed oxide charge on the backside adjacent to the filler oxide after forming a poly-Si channel, effectively improving the cell current flow within the entire string. Through TCAD simulations and experimental device fabrication, we demonstrate a significant enhancement in cell current by approximately 30%. Furthermore, we analyze the impact of positive fixed charge on channel current and investigate the influence of Poly-Si channel thickness and liner oxide thickness on current improvement. Our findings indicate promising avenues for improving 3D NAND Flash memory technology, contributing to its continued advancement in the future.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109072"},"PeriodicalIF":1.4,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1016/j.sse.2025.109067
C. Valdivieso, R. Rodriguez, A. Crespo-Yepes, J. Martin-Martinez, M. Nafria
Resistive Switching (RS) phenomenon, usually observed in two-terminal memristor devices, refers to the reversible change in resistance of a material under an external electric field. In this work, RS has been observed in N-type Fully Depleted Silicon-On-Insulator (FDSOI) Ω-gate nanowire field-effect transistors (NW-FETs). For the first time, partial recovery of the transistor’s ID-VD characteristics during the RS cycling is experimentally demonstrated, indicating the potential of the device to be used both as a transistor and a memristor. The effect of increasing the back gate voltage on the RS characteristics was also experimentally investigated. It was found that higher back gate voltages enhance the RS parameters, thereby establishing a direct relationship between back bias and device performance.
{"title":"Resistive Switching phenomenon in FD-SOI Ω-Gate FETs: Transistor performance recovery and back gate bias influence","authors":"C. Valdivieso, R. Rodriguez, A. Crespo-Yepes, J. Martin-Martinez, M. Nafria","doi":"10.1016/j.sse.2025.109067","DOIUrl":"10.1016/j.sse.2025.109067","url":null,"abstract":"<div><div>Resistive Switching (RS) phenomenon, usually observed in two-terminal memristor devices, refers to the reversible change in resistance of a material under an external electric field. In this work, RS has been observed in N-type Fully Depleted Silicon-On-Insulator (FDSOI) Ω-gate nanowire field-effect transistors (NW-FETs). For the first time, partial recovery of the transistor’s I<sub>D</sub>-V<sub>D</sub> characteristics during the RS cycling is experimentally demonstrated, indicating the potential of the device to be used both as a transistor and a memristor. The effect of increasing the back gate voltage on the RS characteristics was also experimentally investigated. It was found that higher back gate voltages enhance the RS parameters, thereby establishing a direct relationship between back bias and device performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109067"},"PeriodicalIF":1.4,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143402600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1016/j.sse.2025.109073
V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian
This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (AV) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, VEA and AV, in the reverse mode shows better gmsat, SSsat and fT. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (fT) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, AV = 28 dB and fT = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and fT = 3.7 GHz in reverse mode.
{"title":"Analog behavior of V-FET operating in forward and reverse mode","authors":"V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian","doi":"10.1016/j.sse.2025.109073","DOIUrl":"10.1016/j.sse.2025.109073","url":null,"abstract":"<div><div>This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (A<sub>V</sub>) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, V<sub>EA</sub> and A<sub>V</sub>, in the reverse mode shows better gm<sub>sat</sub>, SS<sub>sat</sub> and f<sub>T</sub>. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (f<sub>T</sub>) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, A<sub>V</sub> = 28 dB and f<sub>T</sub> = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and f<sub>T</sub> = 3.7 GHz in reverse mode.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109073"},"PeriodicalIF":1.4,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1016/j.sse.2025.109068
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
In this article, the performance of vertical nanowire Gate All Around (GAA) junction-less pMOSFETs on SOI having an asymmetric architecture was investigated experimentally based on an in-depth study of their electrical characteristics. Current-voltage I-V characteristics in linear operation regime in forward and reverse operation modes are analyzed in a wide range of temperatures from 80 K up to 340 K. In addition to that Low Frequency Noise (LFN) was also studied as a function of the temperature. The main DC and LFN results are presented, showing unusual low field mobility degradation and LFN enhancement for lower temperatures. A correlation was found between the low field mobility degradation and the low frequency noise increasing at low temperature operation, suggesting a strong impact of coulomb scattering on both parameters at low temperatures.
{"title":"Investigation of DC and low frequency noise parameters of junctionless GAA Si VNW pMOSFETs in the temperature range from 80 K to 340 K","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109068","DOIUrl":"10.1016/j.sse.2025.109068","url":null,"abstract":"<div><div>In this article, the performance of vertical nanowire Gate All Around (GAA) junction-less pMOSFETs on SOI having an asymmetric architecture was investigated experimentally based on an in-depth study of their electrical characteristics. Current-voltage I-V characteristics in linear operation regime in forward and reverse operation modes are analyzed in a wide range of temperatures from 80 K up to 340 K. In addition to that Low Frequency Noise (LFN) was also studied as a function of the temperature. The main DC and LFN results are presented, showing unusual low field mobility degradation and LFN enhancement for lower temperatures. A correlation was found between the low field mobility degradation and the low frequency noise increasing at low temperature operation, suggesting a strong impact of coulomb scattering on both parameters at low temperatures.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109068"},"PeriodicalIF":1.4,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-19DOI: 10.1016/j.sse.2025.109071
A. Tahiat , B. Cretu , A. Veloso , E. Simoen
A new Y-function methodology approach for the inversion charge over the gate capacitance ratio estimation from weak to strong inversion operation has been developed. Based on the drain current expression in the linear operation regime and classical mobility law, it is demonstrated that the inversion charge over the gate capacitance ratio may be estimated from weak to strong inversion operation without any approximation by solving a second-degree equation. This latter equation depends notably on the Y-function and on three parameters which are needed to be extracted, two in strong inversion (the gain factor GM and the second order mobility attenuation factor θ2) and one in subthreshold zone (the subthreshold swing SS). This easy-to-use Y-function approach permits accurate and physical meaning electrical parameter extraction confirmed by the very good agreement between the experimental and the model of the drain current and of the transconductance behavior of advanced transistors from weak to strong inversion operation regime.
{"title":"Novel Y-function methodology parameter estimation from weak to strong inversion operation","authors":"A. Tahiat , B. Cretu , A. Veloso , E. Simoen","doi":"10.1016/j.sse.2025.109071","DOIUrl":"10.1016/j.sse.2025.109071","url":null,"abstract":"<div><div>A new Y-function methodology approach for the inversion charge over the gate capacitance ratio estimation from weak to strong inversion operation has been developed. Based on the drain current expression in the linear operation regime and classical mobility law, it is demonstrated that the inversion charge over the gate capacitance ratio may be estimated from weak to strong inversion operation without any approximation by solving a second-degree equation. This latter equation depends notably on the Y-function and on three parameters which are needed to be extracted, two in strong inversion (the gain factor G<sub>M</sub> and the second order mobility attenuation factor θ<sub>2</sub>) and one in subthreshold zone (the subthreshold swing SS). This easy-to-use Y-function approach permits accurate and physical meaning electrical parameter extraction confirmed by the very good agreement between the experimental and the model of the drain current and of the transconductance behavior of advanced transistors from weak to strong inversion operation regime.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109071"},"PeriodicalIF":1.4,"publicationDate":"2025-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-19DOI: 10.1016/j.sse.2025.109070
Salvador Pinillos Gimenez , Marcello Marcelino Correia
This work proposes a simple change of the channel CMOS ICs manufacturing processes to implement FinFETs, focusing on boosting their capacity to drive electrical drain current (IDS) concerning the Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) manufacturing process. Called “Gate-in-Diagonal Fin Field Effect Transistor (GiD-FinFET)”, it was carefully designed to ensure its gate region is non-orthogonal to the Fin, as is observed in the standard Fin Field Effect Transistor (FinFET) counterpart. Three-dimensional (3D) numerical simulations were done using the Atlas Semiconductor Devices Simulator from Silvaco Co. to quantify the influence of the angle between the gate and Fin regions (β) in the drain to source current, compared to the one observed in the conventional FinFET counterpart, considering that these devices present the same Fin volumes. The main results found show that the GiD-FinFETs IDS with a β equal to 45° are 32 % (Triode Region: for VGS = 1.0 V and VDS equal to 0.5 V) and 33 % (Saturation Region: VGS equal to 1.2 V and VDS equal to 1.5 V), respectively, higher than those observed in the conventional FinFET counterpart. This can be justified mainly because the effective channel width of the GiD-FinFETs is 41.5 % larger than that observed in the traditional FinFET counterpart, which leads to better use of its Fin region for the conducting IDS concerning the one measured in the conventional FinFET. Therefore, based on these results, by changing the β between the gate and Fin regions, we can boost the FinFETs IDS and consequently their abilities to buffer electrical current, aiming the reduction of the number of Fins that must be put in parallel to define a specific IDS and their occupied die areas.
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