Solid-state Electronics最新文献

Ferroelectric Hf_0.5Zr_0.5O₂ (HZO) thin films are mostly deposited with a thickness of less than 10 nm by an atomic layer deposition (ALD) process. Since the oxygen source used in the ALD process affects the residues in the deposited HZO films, the choice of oxygen source can be one of the important factors to improve ferroelectricity. From this point of view, the ferroelectric properties of 10-nm-thick ALD-HZO films according to the oxygen source (O₃, H₂O, and D₂O) were comprehensively analyzed in this study. Heavy water (deuterium water, D₂O) was used as a tracer to pinpoint the origin of hydrogen that could be derived from unreacted metal precursors or unreacted hydroxyl groups. As a result, it was revealed that the decrease in ferroelectric polarization and increase in leakage current observed in the H₂O- and D₂O-based HZO capacitors compared to the O₃-based HZO capacitor were due to the oxygen source. These results highlight the importance of using O₃ as a hydrogen-free oxygen source in the ALD process to achieve better ferroelectricity.

The performance of conventional ZnSnO (ZTO) amorphous oxide semiconductor thin-film transistors deposited by atomic layer deposition was optimized at annealing temperatures greater than 500 °C, which is higher than the application temperature of flexible substrates (400 °C). Therefore, we deposited a ZTO thin film as a multilayered ZnO/SnO₂ structure to lower the process temperature to below 400 °C. To optimize the performance of the device with a multilayered structure, we examined the effects of cycles and growth temperatures. Finally, after performing 6 supercycles with 10 cycles of ZnO and 20 cycles of SnO₂, at a growth temperature of 180 °C and annealing at 350 °C for 1 h, the device achieved a saturation carrier mobility of 8.09 cm²/V·s, threshold voltage of 1.6 V, subthreshold swing of 0.58 V/dec, and on–off current ratio of 2.63 × 10⁷. The optimized multilayer-structured device performed better than the ZTO device annealed at 350 °C for 1 h, and even outperformed the device annealed at 500 °C for 1 h. X-ray photoelectron spectroscopy analysis was also conducted to analyze the properties of conventional ZTO and multilayered ZnO/SnO₂ thin films.

Extreme ultraviolet (EUV) pellicles are required for EUV defectivity management in high volume manufacturing (HVM). Theoretical analysis of EUV pellicles of nanometer thickness is helpful for these fabrications. In this paper, for maximum transverse deflection, an analytical–numerical method is contrasted against the finite element method (FEM) due to the ratio of thickness and width length of EUV pellicles. The difference was increased at a thickness of micron unit. Single- and multiple-variable methods of linear regression in deep learning were used to overcome the ANSYS limitation based on FEM, such as the meshing of more than 10 $\mu m$ thickness, and shear loading, an error in FEM resulting from the impact on the stiffness matrix caused by variations in the length-to-thickness ratio increases in the beam element, respectively.

In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency.

Source/drain electrical contact resistance has become a significant parasitic component that should be considered in scaled-down semiconductor devices fabricated with nano-structured channel layers. It is therefore crucial to evaluate the electrical contacts between electrodes and nano-scale thin semiconductor layers precisely. The conventional method for evaluating contacts is based on the transmission-line model (TLM), which extracts the contact parameters (specific contact resistance and transfer length) by assuming that the electrical properties of the semiconductor layer under the electrode are the same as the channel region between the electrodes. However, it is difficult to apply this method directly to modern scaled devices because the electrical properties of ultrathin semiconductor layers under the electrode are altered after metal contact formation. Here, we propose a bridge-contact resistance method that can be used for precise evaluation of the intrinsic contact parameters and the altered sheet resistance under electrodes by accounting for the change in electrical properties of an ultrathin semiconductor layer after contact formation. In this method, the intrinsic electrical contacts are accurately evaluated by analyzing the current distribution through an auxiliary electrically-floated electrode formed on the channel between the two contact electrodes. The effectiveness of the proposed characterization method was verified by evaluating electrical contacts on an ultrathin silicon layer (12 nm thickness). The results indicated that the specific contact resistance and transfer length were extracted to be approximately 20 % lower than those obtained using the conventional TLM method, which was due to the increased sheet resistance under the electrode after contact formation.

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (T_D) of the constituent material. In particular, the T_D of tungsten (T_D,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the T_D,W decreased, and the compressive stress on the tunneling oxide (T_ox) decreased. Consequently, the barrier height between T_ox and poly-Si, and the effective electron mass decreased as the electric field in the T_ox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in T_D,W improved the program efficiency at a lower program voltage (V_PGM). Therefore, a change in the mechanical stress based on decreasing T_D,W improved the program efficiency through a higher FN tunneling process.

This paper presents a simple solution for the pinning voltage of vertical pinned photodiode used in a dual-pixel configuration for phase-detection autofocus applications. Analytic solution of the conventional square deep photodiode has been presented elsewhere. However, this model cannot be adopted to dual pixel where a square pixel contains two rectangular photodiodes. Therefore, we propose a simple analytical model for the rectangular deep photodiode for dual pixels and validate its accuracy by TCAD simulations. The presented model accurately predicts the pinning voltage and potential inside the deep photodiode for dual pixels, thereby confirming its usefulness in the ab-initio design of the pixel as well as in the analysis of the photodiode design.

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (f_OSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of f_OSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.

Recent studies have shown that the sensing capabilities of NO₂ gas sensors can be enhanced by controlling the amount of oxygen vacancy (V_O) in the sensing layer. The sensing layer of the resistor-type sensor can be divided into two regions close to the surface and substrate interface. To control the amount of oxygen vacancy in the sensing layer, oxygen gas flow rate during sputtering is regulated. We fabricate the In₂O₃ gas sensor by vertically adjusting the oxygen vacancy. We place an oxygen vacancy-poor layer on the lower sensing layer and an oxygen vacancy-rich layer on the upper sensing layer. The resistance characteristics of the fabricated sensor are measured through the transmission line method. The NO₂ gas sensing performance of the double sensing layer sensor and the single sensing layer sensor is measured. The best response and fastest response time are observed in the sensor with oxygen vacancy controlled double sensing layer.

Multi-V_th CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device V_th’s are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low-V_th and ultra-high V_th pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability.