Pub Date : 2025-12-01Epub Date: 2025-09-10DOI: 10.1016/j.sse.2025.109240
K. Blanco , F. Mazen , T. Salvetat , D. Landru , F. Rieutord
The layer transfer of InP with the Smart Cut™ technology shows an original behavior, with the existence of a transition temperature, above which fracture occurs rapidly and below which it never spontaneously happens. Using microcracks observation and measurement of the amount of H2 inside cracks, we show that the existence of the two regimes is due to a competition between a trapping of implanted hydrogen inside the cracks and its out-diffusion into the bonded structure.
{"title":"An understanding of fracture kinetics during the layer transfer of InP","authors":"K. Blanco , F. Mazen , T. Salvetat , D. Landru , F. Rieutord","doi":"10.1016/j.sse.2025.109240","DOIUrl":"10.1016/j.sse.2025.109240","url":null,"abstract":"<div><div>The layer transfer of InP with the Smart Cut™ technology shows an original behavior, with the existence of a transition temperature, above which fracture occurs rapidly and below which it never spontaneously happens. Using microcracks observation and measurement of the amount of H<sub>2</sub> inside cracks, we show that the existence of the two regimes is due to a competition between a trapping of implanted hydrogen inside the cracks and its out-diffusion into the bonded structure.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109240"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-10-04DOI: 10.1016/j.sse.2025.109262
G. Vinuesa , T. del Val , K. Kalam , H. García , M.B. González , F. Campabadal , S. Dueñas , H. Castán
In this study, resistive switching in three structures with HfO, AlO, and bilayer (HfO + AlO) oxides is studied. Electrical characterization reveals differences in switching dynamics and performance across these configurations, highlighting the impact of oxide composition and structure on device behavior. The time needed to reset is defined and studied in detail, showing an exponential dependence with the applied voltage. Finally, an initial assessment of the effect that the set and reset transient has on the multilevel capabilities of the devices is made.
{"title":"Effect of set and reset dynamics on HfO2, Al2O3, and bilayer memristors","authors":"G. Vinuesa , T. del Val , K. Kalam , H. García , M.B. González , F. Campabadal , S. Dueñas , H. Castán","doi":"10.1016/j.sse.2025.109262","DOIUrl":"10.1016/j.sse.2025.109262","url":null,"abstract":"<div><div>In this study, resistive switching in three structures with HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>, Al<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>O<span><math><msub><mrow></mrow><mrow><mn>3</mn></mrow></msub></math></span>, and bilayer (HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> + Al<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>O<span><math><msub><mrow></mrow><mrow><mn>3</mn></mrow></msub></math></span>) oxides is studied. Electrical characterization reveals differences in switching dynamics and performance across these configurations, highlighting the impact of oxide composition and structure on device behavior. The time needed to reset is defined and studied in detail, showing an exponential dependence with the applied voltage. Finally, an initial assessment of the effect that the set and reset transient has on the multilevel capabilities of the devices is made.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109262"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article explores the digital and analog/RF figures of merit (FOMs), and circuit performances for finding the optimal design space targeted at sub-3 nm technology node for the Junctionless Forksheet FET (JL FS-FET). Within the sub-3 nm node, the gate length (Lg), width (WFS), and thickness (TFS) are varied between 6 nm–14 nm, 20 nm–40 nm, and 5 nm–9 nm respectively. An optimal design space of Lg = 6 nm − 12 nm can be chosen for digital and analog/RF applications in the sub-3 nm technology node and scaling of Lg > 12 nm is not suitable for designed JL-FSFET since it gives deteriorated Av and fT which are the primary performance metrics to boost the device performance. Additionally, lowering the WFS and TFS is an optimal choice for improving the digital and analog performance whereas higher WFS and TFS should be opted for better RF performance in the sub-3 nm technology node. Moreover, stacking the sheets is a good idea to enhance the analog/RF performance at the cost of compromised Av whereas an improper choice for digital performance. Further, the JL-FSFET based CMOS inverter layout cell for the optimal dimensions (Lg = 12 nm, TFS = 5 nm, WFS = 20 nm) provided better noise margins, gain of ∼9.82 V/V, and delay of ∼5.8 ps making the designed device to be adopted into digital ICs. These findings suggest that design space at sub-3 nm node hold significant potential for optimizing JL-FSFET performance for future device and circuit development.
{"title":"A 3 nm IRDS projection based design space variability and experimental feasibility in junctionless forksheet FET: implications for next-generation digital, analog/RF, and circuit applications","authors":"Kavya Mulaga , Mohan Siva Kumar Mattaparthi , Ramya Dalai , Sresta Valasa , Venkata Ramakrishna Kotha , Sunitha Bhukya , Narendar Vadthiya","doi":"10.1016/j.sse.2025.109231","DOIUrl":"10.1016/j.sse.2025.109231","url":null,"abstract":"<div><div>This article explores the digital and analog/RF figures of merit (FOMs), and circuit performances for finding the optimal design space targeted at sub-3 nm technology node for the Junctionless Forksheet FET (JL FS-FET). Within the sub-3 nm node, the gate length (L<sub>g</sub>), width (W<sub>FS</sub>), and thickness (T<sub>FS</sub>) are varied between 6 nm–14 nm, 20 nm–40 nm, and 5 nm–9 nm respectively. An optimal design space of L<sub>g</sub> = 6 nm − 12 nm can be chosen for digital and analog/RF applications in the sub-3 nm technology node and scaling of L<sub>g</sub> > 12 nm is not suitable for designed JL-FSFET since it gives deteriorated A<sub>v</sub> and f<sub>T</sub> which are the primary performance metrics to boost the device performance. Additionally, lowering the W<sub>FS</sub> and T<sub>FS</sub> is an optimal choice for improving the digital and analog performance whereas higher W<sub>FS</sub> and T<sub>FS</sub> should be opted for better RF performance in the sub-3 nm technology node. Moreover, stacking the sheets is a good idea to enhance the analog/RF performance at the cost of compromised A<sub>v</sub> whereas an improper choice for digital performance. Further, the JL-FSFET based CMOS inverter layout cell for the optimal dimensions (L<sub>g</sub> = 12 nm, T<sub>FS</sub> = 5 nm, W<sub>FS</sub> = 20 nm) provided better noise margins, gain of ∼9.82 V/V, and delay of ∼5.8 ps making the designed device to be adopted into digital ICs. These findings suggest that design space at sub-3 nm node hold significant potential for optimizing JL-FSFET performance for future device and circuit development.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109231"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144933520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-08-30DOI: 10.1016/j.sse.2025.109226
Ankit Dixit , Sandeep Kumar , Naveen Kumar , Deven H. Patil , S. Dasgupta , Navjeet Bagga , Luiz Felipe Aguinsky , Vihar Georgiev
This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the IDS-VGS curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (Vth) is used to predict the early aging of the devices.
{"title":"Assessing the impact of process and design variations on reliability of complementary FET","authors":"Ankit Dixit , Sandeep Kumar , Naveen Kumar , Deven H. Patil , S. Dasgupta , Navjeet Bagga , Luiz Felipe Aguinsky , Vihar Georgiev","doi":"10.1016/j.sse.2025.109226","DOIUrl":"10.1016/j.sse.2025.109226","url":null,"abstract":"<div><div>This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the I<sub>DS</sub>-V<sub>GS</sub> curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (V<sub>th</sub>) is used to predict the early aging of the devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109226"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-23DOI: 10.1016/j.sse.2025.109252
A.E. Mavropoulis , G. Pissanos , N. Vasileiadis , P. Normand , G.Ch. Sirakoulis , P. Dimitrakis
The microstructure of SiNx is strongly affected by its stoichiometry, x. The stoichiometry of SiNx thin films can be modified by adjusting the gas flow rates during LPCVD deposition. The deficiency or excess of Si atoms enhance the formation of defects such as nitrogen vacancies, silicon dangling bonds etc., and thus can enable performance tuning of the resulting MIS RRAM devices. DC electrical characterization, impedance spectroscopy and constant voltage stress measurements were carried out to investigate the properties of non-stoichiometric silicon nitride films as resistive switching material. The average SET time for each device was measured by applying voltage ramps. Improvement in the SET/RESET voltages and SET time is observed. Finally, the stoichiometric film exhibits the lowest breakdown acceleration factor, while the Si-rich film the highest.
{"title":"SiNx RRAMs performance with different stoichiometries","authors":"A.E. Mavropoulis , G. Pissanos , N. Vasileiadis , P. Normand , G.Ch. Sirakoulis , P. Dimitrakis","doi":"10.1016/j.sse.2025.109252","DOIUrl":"10.1016/j.sse.2025.109252","url":null,"abstract":"<div><div>The microstructure of SiN<sub>x</sub> is strongly affected by its stoichiometry, x. The stoichiometry of SiN<sub>x</sub> thin films can be modified by adjusting the gas flow rates during LPCVD deposition. The deficiency or excess of Si atoms enhance the formation of defects such as nitrogen vacancies, silicon dangling bonds etc., and thus can enable performance tuning of the resulting MIS RRAM devices. DC electrical characterization, impedance spectroscopy and constant voltage stress measurements were carried out to investigate the properties of non-stoichiometric silicon nitride films as resistive switching material. The average SET time for each device was measured by applying voltage ramps. Improvement in the SET/RESET voltages and SET time is observed. Finally, the stoichiometric film exhibits the lowest breakdown acceleration factor, while the Si-rich film the highest.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109252"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-08-23DOI: 10.1016/j.sse.2025.109216
Tommaso Ugolini, Elena Gnani
As the development of Dirac-Source Field-Effect Transistors (DS-FETs) progresses, there is an increasing need for a robust, flexible, and agile simulation framework capable of evaluating device performance across a range of operating conditions. This work addresses that need by coupling a two-dimensional (2D) Poisson solver with a quantum transport model under the ballistic transport regime. This simulation approach is employed to analyze the electrical characteristics of a DS-FET realized with the heterojunction of graphene and monolayer MoS. In addition, the impact of gate-to-channel alignment on device performance is systematically investigated. Simulation results underscore the critical role of full gate overlap with the semiconducting region and substantiate the feasibility of DS-FETs based on these two materials.
{"title":"Design guidelines for Gr-MoS2 based DS-FETs","authors":"Tommaso Ugolini, Elena Gnani","doi":"10.1016/j.sse.2025.109216","DOIUrl":"10.1016/j.sse.2025.109216","url":null,"abstract":"<div><div>As the development of Dirac-Source Field-Effect Transistors (DS-FETs) progresses, there is an increasing need for a robust, flexible, and agile simulation framework capable of evaluating device performance across a range of operating conditions. This work addresses that need by coupling a two-dimensional (2D) Poisson solver with a quantum transport model under the ballistic transport regime. This simulation approach is employed to analyze the electrical characteristics of a DS-FET realized with the heterojunction of graphene and monolayer MoS<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>. In addition, the impact of gate-to-channel alignment on device performance is systematically investigated. Simulation results underscore the critical role of full gate overlap with the semiconducting region and substantiate the feasibility of DS-FETs based on these two materials.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109216"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-08DOI: 10.1016/j.sse.2025.109244
Min-Hui Chuang , Sekhar Reddy Kola , Yiming Li
This study examines the impact of the bottom parasitic channel coverage ratio on the electrical characteristics of gate-all-around silicon nanosheet complementary FETs (GAA Si NS CFETs) optimized for sub-1-nm technology nodes. The coverage ratio, ranging from 60% to 100%, is analyzed in both n on p and p on n stacked configurations. Results reveal a strong inverse correlation between coverage ratio and bottom-device leakage current: devices with 60% coverage exhibit leakage currents up to 169× (p on n) and 140× (n on p) greater than those with full (100%) coverage. Additionally, the high-frequency behavior of a common-source amplifier shows that the cut-off frequency significantly improves in devices with a 100% bottom channel coverage ratio, highlighting the critical role of bottom-channel integrity in analog performance.
本研究考察了底部寄生通道覆盖率对栅极全硅纳米片互补场效应管（GAA Si NS cfet）电特性的影响，该互补场效应管优化用于亚1nm技术节点。在n on p和p on n堆叠两种配置下，分析了覆盖率，范围从60%到100%。结果显示，覆盖率与底部器件泄漏电流之间存在很强的负相关关系：60%覆盖率的器件的泄漏电流比完全（100%）覆盖率的器件的泄漏电流大169倍（p on n）和140倍（n on p）。此外，共源放大器的高频特性表明，在100%底通道覆盖率的设备中，截止频率显著提高，突出了底通道完整性在模拟性能中的关键作用。
{"title":"Impact of bottom channel coverage ratio on electrical characteristics of GAA Si NS CFETs for Sub-1-nm nodes","authors":"Min-Hui Chuang , Sekhar Reddy Kola , Yiming Li","doi":"10.1016/j.sse.2025.109244","DOIUrl":"10.1016/j.sse.2025.109244","url":null,"abstract":"<div><div>This study examines the impact of the bottom parasitic channel coverage ratio on the electrical characteristics of gate-all-around silicon nanosheet complementary FETs (GAA Si NS CFETs) optimized for sub-1-nm technology nodes. The coverage ratio, ranging from 60% to 100%, is analyzed in both <em>n</em> on <em>p</em> and <em>p</em> on <em>n</em> stacked configurations. Results reveal a strong inverse correlation between coverage ratio and bottom-device leakage current: devices with 60% coverage exhibit leakage currents up to 169× (<em>p</em> on <em>n</em>) and 140× (<em>n</em> on <em>p</em>) greater than those with full (100%) coverage. Additionally, the high-frequency behavior of a common-source amplifier shows that the cut-off frequency significantly improves in devices with a 100% bottom channel coverage ratio, highlighting the critical role of bottom-channel integrity in analog performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109244"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145019791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an experimental method to directly evaluate the oxide trap densities in TiN/Al:HfO/TiN capacitors from the low-field current hysteresis in voltage-ramp-stress (VRS) measurements. The extracted densities of deep electron traps are in the 1013 cm−2 range and virtually independent of the Al-doping concentration in HfO (ranging from 2% to 20%). These results indicate that the trapping sites are intrinsic and may be related to polaronic states in disordered HfO. Regarding reproducibility and stability, the measurements were consistent across all samples, except for those with low Al doping, which exhibited increased leakage and degradation likely due to partial crystallization. In degraded samples, conductive paths formed after electrical stress confine the leakage, limiting the sensitivity of the method to local trap densities adjacent to the leakage path.
{"title":"Extraction of trap densities in Al:HfO2 MIM capacitors using voltage ramp stress measurements","authors":"Corinna Fohn , Emmanuel Chery , Kristof Croes , Michele Stucchi , Valeri Afanas’ev","doi":"10.1016/j.sse.2025.109239","DOIUrl":"10.1016/j.sse.2025.109239","url":null,"abstract":"<div><div>We present an experimental method to directly evaluate the oxide trap densities in TiN/Al:HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>/TiN capacitors from the low-field current hysteresis in voltage-ramp-stress (VRS) measurements. The extracted densities of deep electron traps are in the 10<sup>13</sup> cm<sup>−2</sup> range and virtually independent of the Al-doping concentration in HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> (ranging from 2% to 20%). These results indicate that the trapping sites are intrinsic and may be related to polaronic states in disordered HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>. Regarding reproducibility and stability, the measurements were consistent across all samples, except for those with low Al doping, which exhibited increased leakage and degradation likely due to partial crystallization. In degraded samples, conductive paths formed after electrical stress confine the leakage, limiting the sensitivity of the method to local trap densities adjacent to the leakage path.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109239"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-06DOI: 10.1016/j.sse.2025.109243
Sahil Sharma , Kumaran Selva , Carlos A. Favela , Bo Yu , Venkat Selvamanickam
Use of solar energy for electric power has a huge potential to reduce the carbon footprint caused by greenhouse gases (GHG). While photovoltaics (PV) has been adopted in mainstream terrestrial applications, their implementation in the automotive sector, to make PV-powered vehicles, has been minimal. The existing PV-powered vehicles utilize low-efficiency solar cells, which limits the driving range to 20 miles/day. In this work, we present concentrated photovoltaic (CPV) devices using high-efficiency III-V solar cells for automobile application to realize longer driving range. We have developed inexpensive and flexible III-V PV on metal tapes and integrated them with a durable, flexible PDMS microlens for light concentration. The integrated device showed more than 9 times improvement in current density and power output compared to a solar device without a light concentrator at 1 sun. Use an array of microlens integrated with III-V PV could extend the driving range to 115 miles/day for a vehicle with an electric mileage of 10 miles/kWh. We have also investigated the effect of the light incident angle on device performance to evaluate the optimal tilt angle while mounting the PV module on the vehicle’s roof.
{"title":"Flexible & light-weight III-V concentrated photovoltaics for automobile application","authors":"Sahil Sharma , Kumaran Selva , Carlos A. Favela , Bo Yu , Venkat Selvamanickam","doi":"10.1016/j.sse.2025.109243","DOIUrl":"10.1016/j.sse.2025.109243","url":null,"abstract":"<div><div>Use of solar energy for electric power has a huge potential to reduce the carbon footprint caused by greenhouse gases (GHG). While photovoltaics (PV) has been adopted in mainstream terrestrial applications, their implementation in the automotive sector, to make PV-powered vehicles, has been minimal. The existing PV-powered vehicles utilize low-efficiency solar cells, which limits the driving range to 20 miles/day. In this work, we present concentrated photovoltaic (CPV) devices using high-efficiency III-V solar cells for automobile application to realize longer driving range. We have developed inexpensive and flexible III-V PV on metal tapes and integrated them with a durable, flexible PDMS microlens for light concentration. The integrated device showed more than 9 times improvement in current density and power output compared to a solar device without a light concentrator at 1 sun. Use an array of microlens integrated with III-V PV could extend the driving range to 115 miles/day for a vehicle with an electric mileage of 10 miles/kWh. We have also investigated the effect of the light incident angle on device performance to evaluate the optimal tilt angle while mounting the PV module on the vehicle’s roof.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109243"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-08-30DOI: 10.1016/j.sse.2025.109227
Jin Ho Park , Jae Woog Jung , Hyunwoo Kim
In the advancing sub-3 nm technology node, device evolution has progressed from FinFET to gate-all-around based nanosheet architectures (NSFETs). This transition addresses the limitations of FinFETs, where scaling down leads to a reduced number of fins, maintaining a quantized width and resulting in decreased current drivability. In contrast, NSFETs offer flexible width design similar to traditional planar structures and allow for multi-channel stacking, increasing current and making them an attractive candidate from a circuit design perspective. However, NSFETs also faces challenges in device performance due to increased parasitic RC components, despite improved gate controllability.
In this work, we analyzed parasitic RC components in NSFETs with different source/drain growth profiles using 3D TCAD simulations and then examined the RC delay to determine the source/drain growth profile that exhibits optimal device performance. Furthermore, we investigated self-heating effects (SHEs) to evaluate heat dissipation across different source/drain profiles, integrating these findings with RC delay analyses to propose the optimal growth profile.
{"title":"Optimization of lateral source/drain growth profile for improving RC delay in nanosheet field-effect transistor","authors":"Jin Ho Park , Jae Woog Jung , Hyunwoo Kim","doi":"10.1016/j.sse.2025.109227","DOIUrl":"10.1016/j.sse.2025.109227","url":null,"abstract":"<div><div>In the advancing sub-3 nm technology node, device evolution has progressed from FinFET to gate-all-around based nanosheet architectures (NSFETs). This transition addresses the limitations of FinFETs, where scaling down leads to a reduced number of fins, maintaining a quantized width and resulting in decreased current drivability. In contrast, NSFETs offer flexible width design similar to traditional planar structures and allow for multi-channel stacking, increasing current and making them an attractive candidate from a circuit design perspective. However, NSFETs also faces challenges in device performance due to increased parasitic RC components, despite improved gate controllability.</div><div>In this work, we analyzed parasitic RC components in NSFETs with different source/drain growth profiles using 3D TCAD simulations and then examined the RC delay to determine the source/drain growth profile that exhibits optimal device performance. Furthermore, we investigated self-heating effects (SHEs) to evaluate heat dissipation across different source/drain profiles, integrating these findings with RC delay analyses to propose the optimal growth profile.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109227"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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