We present an experimental method to directly evaluate the oxide trap densities in TiN/Al:HfO/TiN capacitors from the low-field current hysteresis in voltage-ramp-stress (VRS) measurements. The extracted densities of deep electron traps are in the 1013 cm−2 range and virtually independent of the Al-doping concentration in HfO (ranging from 2% to 20%). These results indicate that the trapping sites are intrinsic and may be related to polaronic states in disordered HfO. Regarding reproducibility and stability, the measurements were consistent across all samples, except for those with low Al doping, which exhibited increased leakage and degradation likely due to partial crystallization. In degraded samples, conductive paths formed after electrical stress confine the leakage, limiting the sensitivity of the method to local trap densities adjacent to the leakage path.
{"title":"Extraction of trap densities in Al:HfO2 MIM capacitors using voltage ramp stress measurements","authors":"Corinna Fohn , Emmanuel Chery , Kristof Croes , Michele Stucchi , Valeri Afanas’ev","doi":"10.1016/j.sse.2025.109239","DOIUrl":"10.1016/j.sse.2025.109239","url":null,"abstract":"<div><div>We present an experimental method to directly evaluate the oxide trap densities in TiN/Al:HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>/TiN capacitors from the low-field current hysteresis in voltage-ramp-stress (VRS) measurements. The extracted densities of deep electron traps are in the 10<sup>13</sup> cm<sup>−2</sup> range and virtually independent of the Al-doping concentration in HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> (ranging from 2% to 20%). These results indicate that the trapping sites are intrinsic and may be related to polaronic states in disordered HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>. Regarding reproducibility and stability, the measurements were consistent across all samples, except for those with low Al doping, which exhibited increased leakage and degradation likely due to partial crystallization. In degraded samples, conductive paths formed after electrical stress confine the leakage, limiting the sensitivity of the method to local trap densities adjacent to the leakage path.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109239"},"PeriodicalIF":1.4,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-08DOI: 10.1016/j.sse.2025.109244
Min-Hui Chuang , Sekhar Reddy Kola , Yiming Li
This study examines the impact of the bottom parasitic channel coverage ratio on the electrical characteristics of gate-all-around silicon nanosheet complementary FETs (GAA Si NS CFETs) optimized for sub-1-nm technology nodes. The coverage ratio, ranging from 60% to 100%, is analyzed in both n on p and p on n stacked configurations. Results reveal a strong inverse correlation between coverage ratio and bottom-device leakage current: devices with 60% coverage exhibit leakage currents up to 169× (p on n) and 140× (n on p) greater than those with full (100%) coverage. Additionally, the high-frequency behavior of a common-source amplifier shows that the cut-off frequency significantly improves in devices with a 100% bottom channel coverage ratio, highlighting the critical role of bottom-channel integrity in analog performance.
本研究考察了底部寄生通道覆盖率对栅极全硅纳米片互补场效应管（GAA Si NS cfet）电特性的影响，该互补场效应管优化用于亚1nm技术节点。在n on p和p on n堆叠两种配置下，分析了覆盖率，范围从60%到100%。结果显示，覆盖率与底部器件泄漏电流之间存在很强的负相关关系：60%覆盖率的器件的泄漏电流比完全（100%）覆盖率的器件的泄漏电流大169倍（p on n）和140倍（n on p）。此外，共源放大器的高频特性表明，在100%底通道覆盖率的设备中，截止频率显著提高，突出了底通道完整性在模拟性能中的关键作用。
{"title":"Impact of bottom channel coverage ratio on electrical characteristics of GAA Si NS CFETs for Sub-1-nm nodes","authors":"Min-Hui Chuang , Sekhar Reddy Kola , Yiming Li","doi":"10.1016/j.sse.2025.109244","DOIUrl":"10.1016/j.sse.2025.109244","url":null,"abstract":"<div><div>This study examines the impact of the bottom parasitic channel coverage ratio on the electrical characteristics of gate-all-around silicon nanosheet complementary FETs (GAA Si NS CFETs) optimized for sub-1-nm technology nodes. The coverage ratio, ranging from 60% to 100%, is analyzed in both <em>n</em> on <em>p</em> and <em>p</em> on <em>n</em> stacked configurations. Results reveal a strong inverse correlation between coverage ratio and bottom-device leakage current: devices with 60% coverage exhibit leakage currents up to 169× (<em>p</em> on <em>n</em>) and 140× (<em>n</em> on <em>p</em>) greater than those with full (100%) coverage. Additionally, the high-frequency behavior of a common-source amplifier shows that the cut-off frequency significantly improves in devices with a 100% bottom channel coverage ratio, highlighting the critical role of bottom-channel integrity in analog performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109244"},"PeriodicalIF":1.4,"publicationDate":"2025-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145019791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-06DOI: 10.1016/j.sse.2025.109243
Sahil Sharma , Kumaran Selva , Carlos A. Favela , Bo Yu , Venkat Selvamanickam
Use of solar energy for electric power has a huge potential to reduce the carbon footprint caused by greenhouse gases (GHG). While photovoltaics (PV) has been adopted in mainstream terrestrial applications, their implementation in the automotive sector, to make PV-powered vehicles, has been minimal. The existing PV-powered vehicles utilize low-efficiency solar cells, which limits the driving range to 20 miles/day. In this work, we present concentrated photovoltaic (CPV) devices using high-efficiency III-V solar cells for automobile application to realize longer driving range. We have developed inexpensive and flexible III-V PV on metal tapes and integrated them with a durable, flexible PDMS microlens for light concentration. The integrated device showed more than 9 times improvement in current density and power output compared to a solar device without a light concentrator at 1 sun. Use an array of microlens integrated with III-V PV could extend the driving range to 115 miles/day for a vehicle with an electric mileage of 10 miles/kWh. We have also investigated the effect of the light incident angle on device performance to evaluate the optimal tilt angle while mounting the PV module on the vehicle’s roof.
{"title":"Flexible & light-weight III-V concentrated photovoltaics for automobile application","authors":"Sahil Sharma , Kumaran Selva , Carlos A. Favela , Bo Yu , Venkat Selvamanickam","doi":"10.1016/j.sse.2025.109243","DOIUrl":"10.1016/j.sse.2025.109243","url":null,"abstract":"<div><div>Use of solar energy for electric power has a huge potential to reduce the carbon footprint caused by greenhouse gases (GHG). While photovoltaics (PV) has been adopted in mainstream terrestrial applications, their implementation in the automotive sector, to make PV-powered vehicles, has been minimal. The existing PV-powered vehicles utilize low-efficiency solar cells, which limits the driving range to 20 miles/day. In this work, we present concentrated photovoltaic (CPV) devices using high-efficiency III-V solar cells for automobile application to realize longer driving range. We have developed inexpensive and flexible III-V PV on metal tapes and integrated them with a durable, flexible PDMS microlens for light concentration. The integrated device showed more than 9 times improvement in current density and power output compared to a solar device without a light concentrator at 1 sun. Use an array of microlens integrated with III-V PV could extend the driving range to 115 miles/day for a vehicle with an electric mileage of 10 miles/kWh. We have also investigated the effect of the light incident angle on device performance to evaluate the optimal tilt angle while mounting the PV module on the vehicle’s roof.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109243"},"PeriodicalIF":1.4,"publicationDate":"2025-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-06DOI: 10.1016/j.sse.2025.109230
Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich
In this study, we fabricated high-quality, liquid gate-all-around silicon nanowire (NW) field-effect transistor (FET) biosensors with a gold bowtie antenna using a silicon-on-insulator (SOI) wafer. The electrical and noise properties of these novel NW FETs were investigated under 940 nm light-emitting diode (LED) optical excitation in different solutions. A two-level signal (TLS) that is useful for biosensing was successfully activated at the light excitation only. The detection of repeatable fluctuations in current, manifested as minor peaks in the I–V curves under infrared illumination, confirms the activation of a TLS in the biosensors. The TLS demonstrates a linear dependence of its amplitude in relation to intensity. Moreover, we performed TLS studies in MgCl2 solutions of different concentrations. The results indicate that the FET devices incorporating a gold antenna have considerable potential for the excitation of TLS, thus allowing the sensitivity of the biosensors to be about 300 % enhanced.
{"title":"Silicon nanowire field-effect transistor biosensors with bowtie antenna","authors":"Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich","doi":"10.1016/j.sse.2025.109230","DOIUrl":"10.1016/j.sse.2025.109230","url":null,"abstract":"<div><div>In this study, we fabricated high-quality, liquid gate-all-around silicon nanowire (NW) field-effect transistor (FET) biosensors with a gold bowtie antenna using a silicon-on-insulator (SOI) wafer. The electrical and noise properties of these novel NW FETs were investigated under 940 nm light-emitting diode (LED) optical excitation in different solutions. A two-level signal (TLS) that is useful for biosensing was successfully activated at the light excitation only. The detection of repeatable fluctuations in current, manifested as minor peaks in the I–V curves under infrared illumination, confirms the activation of a TLS in the biosensors. The TLS demonstrates a linear dependence of its amplitude in relation to intensity. Moreover, we performed TLS studies in MgCl<sub>2</sub> solutions of different concentrations. The results indicate that the FET devices incorporating a gold antenna have considerable potential for the excitation of TLS, thus allowing the sensitivity of the biosensors to be about 300 % enhanced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109230"},"PeriodicalIF":1.4,"publicationDate":"2025-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-03DOI: 10.1016/j.sse.2025.109238
Nadine Dersch , Eduardo Perez , Christian Wenger , Mike Schwarz , Benjamin Iniguez , Alexander Kloes
This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.
{"title":"A closed-form model for programming of oxide-based resistive random access memory cells derived from the Stanford model","authors":"Nadine Dersch , Eduardo Perez , Christian Wenger , Mike Schwarz , Benjamin Iniguez , Alexander Kloes","doi":"10.1016/j.sse.2025.109238","DOIUrl":"10.1016/j.sse.2025.109238","url":null,"abstract":"<div><div>This paper presents a closed-form model for pulse-based programming of oxide-based resistive random access memory devices. The Stanford model is used as a basis and solved in a closed-form for the programming cycle. A constant temperature is set for this solution. With the closed-form model, the state of the device after programming or the required programming settings for achieving a specific device conductance can be calculated directly and quickly. The Stanford model requires time-consuming iterative calculations for high accuracy in transient analysis, which is not necessary for the closed-form model. The closed-form model is scalable across different programming pulse widths and voltages.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109238"},"PeriodicalIF":1.4,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145010667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article explores the digital and analog/RF figures of merit (FOMs), and circuit performances for finding the optimal design space targeted at sub-3 nm technology node for the Junctionless Forksheet FET (JL FS-FET). Within the sub-3 nm node, the gate length (Lg), width (WFS), and thickness (TFS) are varied between 6 nm–14 nm, 20 nm–40 nm, and 5 nm–9 nm respectively. An optimal design space of Lg = 6 nm − 12 nm can be chosen for digital and analog/RF applications in the sub-3 nm technology node and scaling of Lg > 12 nm is not suitable for designed JL-FSFET since it gives deteriorated Av and fT which are the primary performance metrics to boost the device performance. Additionally, lowering the WFS and TFS is an optimal choice for improving the digital and analog performance whereas higher WFS and TFS should be opted for better RF performance in the sub-3 nm technology node. Moreover, stacking the sheets is a good idea to enhance the analog/RF performance at the cost of compromised Av whereas an improper choice for digital performance. Further, the JL-FSFET based CMOS inverter layout cell for the optimal dimensions (Lg = 12 nm, TFS = 5 nm, WFS = 20 nm) provided better noise margins, gain of ∼9.82 V/V, and delay of ∼5.8 ps making the designed device to be adopted into digital ICs. These findings suggest that design space at sub-3 nm node hold significant potential for optimizing JL-FSFET performance for future device and circuit development.
{"title":"A 3 nm IRDS projection based design space variability and experimental feasibility in junctionless forksheet FET: implications for next-generation digital, analog/RF, and circuit applications","authors":"Kavya Mulaga , Mohan Siva Kumar Mattaparthi , Ramya Dalai , Sresta Valasa , Venkata Ramakrishna Kotha , Sunitha Bhukya , Narendar Vadthiya","doi":"10.1016/j.sse.2025.109231","DOIUrl":"10.1016/j.sse.2025.109231","url":null,"abstract":"<div><div>This article explores the digital and analog/RF figures of merit (FOMs), and circuit performances for finding the optimal design space targeted at sub-3 nm technology node for the Junctionless Forksheet FET (JL FS-FET). Within the sub-3 nm node, the gate length (L<sub>g</sub>), width (W<sub>FS</sub>), and thickness (T<sub>FS</sub>) are varied between 6 nm–14 nm, 20 nm–40 nm, and 5 nm–9 nm respectively. An optimal design space of L<sub>g</sub> = 6 nm − 12 nm can be chosen for digital and analog/RF applications in the sub-3 nm technology node and scaling of L<sub>g</sub> > 12 nm is not suitable for designed JL-FSFET since it gives deteriorated A<sub>v</sub> and f<sub>T</sub> which are the primary performance metrics to boost the device performance. Additionally, lowering the W<sub>FS</sub> and T<sub>FS</sub> is an optimal choice for improving the digital and analog performance whereas higher W<sub>FS</sub> and T<sub>FS</sub> should be opted for better RF performance in the sub-3 nm technology node. Moreover, stacking the sheets is a good idea to enhance the analog/RF performance at the cost of compromised A<sub>v</sub> whereas an improper choice for digital performance. Further, the JL-FSFET based CMOS inverter layout cell for the optimal dimensions (L<sub>g</sub> = 12 nm, T<sub>FS</sub> = 5 nm, W<sub>FS</sub> = 20 nm) provided better noise margins, gain of ∼9.82 V/V, and delay of ∼5.8 ps making the designed device to be adopted into digital ICs. These findings suggest that design space at sub-3 nm node hold significant potential for optimizing JL-FSFET performance for future device and circuit development.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109231"},"PeriodicalIF":1.4,"publicationDate":"2025-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144933520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-30DOI: 10.1016/j.sse.2025.109226
Ankit Dixit , Sandeep Kumar , Naveen Kumar , Deven H. Patil , S. Dasgupta , Navjeet Bagga , Luiz Felipe Aguinsky , Vihar Georgiev
This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the IDS-VGS curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (Vth) is used to predict the early aging of the devices.
{"title":"Assessing the impact of process and design variations on reliability of complementary FET","authors":"Ankit Dixit , Sandeep Kumar , Naveen Kumar , Deven H. Patil , S. Dasgupta , Navjeet Bagga , Luiz Felipe Aguinsky , Vihar Georgiev","doi":"10.1016/j.sse.2025.109226","DOIUrl":"10.1016/j.sse.2025.109226","url":null,"abstract":"<div><div>This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the I<sub>DS</sub>-V<sub>GS</sub> curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (V<sub>th</sub>) is used to predict the early aging of the devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109226"},"PeriodicalIF":1.4,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-30DOI: 10.1016/j.sse.2025.109227
Jin Ho Park , Jae Woog Jung , Hyunwoo Kim
In the advancing sub-3 nm technology node, device evolution has progressed from FinFET to gate-all-around based nanosheet architectures (NSFETs). This transition addresses the limitations of FinFETs, where scaling down leads to a reduced number of fins, maintaining a quantized width and resulting in decreased current drivability. In contrast, NSFETs offer flexible width design similar to traditional planar structures and allow for multi-channel stacking, increasing current and making them an attractive candidate from a circuit design perspective. However, NSFETs also faces challenges in device performance due to increased parasitic RC components, despite improved gate controllability.
In this work, we analyzed parasitic RC components in NSFETs with different source/drain growth profiles using 3D TCAD simulations and then examined the RC delay to determine the source/drain growth profile that exhibits optimal device performance. Furthermore, we investigated self-heating effects (SHEs) to evaluate heat dissipation across different source/drain profiles, integrating these findings with RC delay analyses to propose the optimal growth profile.
{"title":"Optimization of lateral source/drain growth profile for improving RC delay in nanosheet field-effect transistor","authors":"Jin Ho Park , Jae Woog Jung , Hyunwoo Kim","doi":"10.1016/j.sse.2025.109227","DOIUrl":"10.1016/j.sse.2025.109227","url":null,"abstract":"<div><div>In the advancing sub-3 nm technology node, device evolution has progressed from FinFET to gate-all-around based nanosheet architectures (NSFETs). This transition addresses the limitations of FinFETs, where scaling down leads to a reduced number of fins, maintaining a quantized width and resulting in decreased current drivability. In contrast, NSFETs offer flexible width design similar to traditional planar structures and allow for multi-channel stacking, increasing current and making them an attractive candidate from a circuit design perspective. However, NSFETs also faces challenges in device performance due to increased parasitic RC components, despite improved gate controllability.</div><div>In this work, we analyzed parasitic RC components in NSFETs with different source/drain growth profiles using 3D TCAD simulations and then examined the RC delay to determine the source/drain growth profile that exhibits optimal device performance. Furthermore, we investigated self-heating effects (SHEs) to evaluate heat dissipation across different source/drain profiles, integrating these findings with RC delay analyses to propose the optimal growth profile.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109227"},"PeriodicalIF":1.4,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-30DOI: 10.1016/j.sse.2025.109225
Yu Yan , Cunhua Dou , Xuan Zhang , Weijia Song , Zhiyu Tang , Binhong Li , Jing Wan , Huabin Sun , Xing Zhao , Yun Wang , Yong Xu , Sorin Cristoloveanu
The universal burden of series resistance in short-channel MOSFETs is even more critical in ultrathin transistors where the sheet resistance of source and drain terminals is high. However, FD-SOI devices benefit from the back-gate action which can also modulate the series resistance. Several methods for series resistance extraction are examined. Unlike an advanced FD-SOI MOSFET with highly-doped raised terminals, the junctionless transistors (with either conventional or core–shell architecture) exhibit higher series resistance, strongly dependent on back-gate voltage.
{"title":"Impact of back-biasing on the series resistance in ultrathin SOI devices","authors":"Yu Yan , Cunhua Dou , Xuan Zhang , Weijia Song , Zhiyu Tang , Binhong Li , Jing Wan , Huabin Sun , Xing Zhao , Yun Wang , Yong Xu , Sorin Cristoloveanu","doi":"10.1016/j.sse.2025.109225","DOIUrl":"10.1016/j.sse.2025.109225","url":null,"abstract":"<div><div>The universal burden of series resistance in short-channel MOSFETs is even more critical in ultrathin transistors where the sheet resistance of source and drain terminals is high. However, FD-SOI devices benefit from the back-gate action which can also modulate the series resistance. Several methods for series resistance extraction are examined. Unlike an advanced FD-SOI MOSFET with highly-doped raised terminals, the junctionless transistors (with either conventional or core–shell architecture) exhibit higher series resistance, strongly dependent on back-gate voltage.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109225"},"PeriodicalIF":1.4,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-29DOI: 10.1016/j.sse.2025.109222
Hyo-Joung Kim , Walid Amir , Surajit Chakraborty , Ju-Won Shin , Ki-Young Shin , Hyuk-Min Kwon , Tae-Woo Kim
In GaN-based High-Electron Mobility Transistors (HEMTs), the carrier transport properties of the 2-Dimensional Electron Gas (2DEG), specifically the saturation velocity (υsat) and effective mobility (μn_eff,), are critical determinants of device performance. To enhance these properties, we conducted structural optimizations, which included reducing the Al mole fraction in the AlxGa1-xN barrier and introducing an AlGaN back barrier. Recognizing the limitations of traditional extraction techniques, we employed transconductance modeling to accurately extract effective mobility and saturation velocity values. The implementation of the AlGaN back barrier resulted in an effective mobility enhancement to 748 cm2/V·s. Additionally, reducing the Al mole fraction in the AlxGa1-xN top barrier led to an effective mobility improvement of 484 cm2/V·s. These findings provide valuable insights into the design of epitaxial structures for AlGaN/GaN HEMTs aimed at achieving superior performance in future applications.
{"title":"Enhancing carrier transport in AlGaN/GaN HEMTs through structural optimization and transconductance modeling","authors":"Hyo-Joung Kim , Walid Amir , Surajit Chakraborty , Ju-Won Shin , Ki-Young Shin , Hyuk-Min Kwon , Tae-Woo Kim","doi":"10.1016/j.sse.2025.109222","DOIUrl":"10.1016/j.sse.2025.109222","url":null,"abstract":"<div><div>In GaN-based High-Electron Mobility Transistors (HEMTs), the carrier transport properties of the 2-Dimensional Electron Gas (2DEG), specifically the saturation velocity (<em>υ<sub>sat</sub></em>) and effective mobility (<em>μ<sub>n_eff</sub></em>,), are critical determinants of device performance. To enhance these properties, we conducted structural optimizations, which included reducing the Al mole fraction in the Al<sub>x</sub>Ga<sub>1-x</sub>N barrier and introducing an AlGaN back barrier. Recognizing the limitations of traditional extraction techniques, we employed transconductance modeling to accurately extract effective mobility and saturation velocity values. The implementation of the AlGaN back barrier resulted in an effective mobility enhancement to 748 cm<sup>2</sup>/V·s. Additionally, reducing the Al mole fraction in the Al<sub>x</sub>Ga<sub>1-x</sub>N top barrier led to an effective mobility improvement of 484 cm<sup>2</sup>/V·s. These findings provide valuable insights into the design of epitaxial structures for AlGaN/GaN HEMTs aimed at achieving superior performance in future applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109222"},"PeriodicalIF":1.4,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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