Pub Date : 2025-01-09DOI: 10.1016/j.sse.2025.109064
Dong-Sik Park , Ji-Hoon Chang , Su-Ho Shin , Chang-Sik Kim , Yongsoo Ahn , Byoungdeog Choi
This paper focuses on investigating the origin of the vulnerability and proposing improvement strategies for gate oxide (Gox) breakdown in the core area of dynamic random access memory (DRAM) products. The shallow trench isolation (STI) area in 15-nm DRAM intricately comprises a triple-layer structure: sidewall oxide, nitride liner, and trench oxide. The existing structure had a high protrusion of the nitride liner, disrupting the gas flow during Gox deposition and resulting in a relatively thin thickness at the active corners. Additionally, when the gate voltage is applied, the angular shape of the active Si area led to a concentration of the electric field in the corner area. These two structural characteristics were recognized as the causes that render the active corner area vulnerable to Gox breakdown failure. By developing new wet-etching processes for the active and STI structures, we can significantly improve Gox breakdown. We applied a phosphoric acid process to improve the high protrusion structure of the nitride liner and used a new solution process to make the active corner more rounded. We validated the enhancement through the application to actual products and verified it by electrical results. Ultimately, this approach serves as a crucial clue for the continued scaling of DRAM core transistors.
{"title":"Improvement of gate oxide breakdown through STI structure Modification in DRAM","authors":"Dong-Sik Park , Ji-Hoon Chang , Su-Ho Shin , Chang-Sik Kim , Yongsoo Ahn , Byoungdeog Choi","doi":"10.1016/j.sse.2025.109064","DOIUrl":"10.1016/j.sse.2025.109064","url":null,"abstract":"<div><div>This paper focuses on investigating the origin of the vulnerability and proposing improvement strategies for gate oxide (G<sub>ox</sub>) breakdown in the core area of dynamic random access memory (DRAM) products. The shallow trench isolation (STI) area in 15-nm DRAM intricately comprises a triple-layer structure: sidewall oxide, nitride liner, and trench oxide. The existing structure had a high protrusion of the nitride liner, disrupting the gas flow during G<sub>ox</sub> deposition and resulting in a relatively thin thickness at the active corners. Additionally, when the gate voltage is applied, the angular shape of the active Si area led to a concentration of the electric field in the corner area. These two structural characteristics were recognized as the causes that render the active corner area vulnerable to G<sub>ox</sub> breakdown failure. By developing new wet-etching processes for the active and STI structures, we can significantly improve G<sub>ox</sub> breakdown. We applied a phosphoric acid process to improve the high protrusion structure of the nitride liner and used a new solution process to make the active corner more rounded. We validated the enhancement through the application to actual products and verified it by electrical results. Ultimately, this approach serves as a crucial clue for the continued scaling of DRAM core transistors.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109064"},"PeriodicalIF":1.4,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-09DOI: 10.1016/j.sse.2024.109053
Xiangdong Xu , Zhongzhong Luo , Huabin Sun , Yong Xu , Li Gao , Zhihao Yu
In the era of data-centric computing, the quantity of data is expected to increase exponentially. The physical separation of memory and processing units in traditional computers results in a considerable amount of unnecessary energy loss and time delay in the process of data calculation and storage. Devices based on ferroelectric materials possess the advantage of integrated data storage and computing. Nevertheless, research in the field of advanced computing has been constrained due to the incompatibility of traditional ferroelectrics (e.g., perovskites) with complementary metal oxide semiconductor (CMOS) technology and poor scalability. In recent years, research and innovation in hafnium (Hf)-based ferroelectrics have reignited interest in this field. The inherent CMOS compatibility, high coercive field (Ec), and high energy band gap of Hf-based ferroelectrics make their devices highly suitable for data storage. Moreover, the negative capacitance field-effect transistor (NCFET) based on Hf-based ferroelectrics can be utilized as a representative logic computing device. In addition, the multi-level weights of biological synapses can be accurately simulated by adjusting the controllable multi-domain polarization switching in Hf-based ferroelectric films, which indicates that Hf-based ferroelectrics will also have general advantages in the field of neuromorphic computing. However, the basic mechanisms and research progress of Hf-based ferroelectrics in these advanced computing fields have not been systematically summarized and sorted out. In this paper, we summarize the latest research results of Hf-based ferroelectrics in advanced computing. We review the history of ferroelectric materials and the numerous advantages of Hf-based ferroelectrics, focusing on the working principles, research progress, and circuit applications of Hf-based ferroelectric logic and memory devices. Additionally, we review the basic concepts of neuromorphic computing, especially discussing the research progress of Hf-based ferroelectric neuromorphic devices and the circuit applications of hardware neural networks. Finally, we made a positive outlook on this field.
{"title":"A review of hafnium-based ferroelectrics for advanced computing","authors":"Xiangdong Xu , Zhongzhong Luo , Huabin Sun , Yong Xu , Li Gao , Zhihao Yu","doi":"10.1016/j.sse.2024.109053","DOIUrl":"10.1016/j.sse.2024.109053","url":null,"abstract":"<div><div>In the era of data-centric computing, the quantity of data is expected to increase exponentially. The physical separation of memory and processing units in traditional computers results in a considerable amount of unnecessary energy loss and time delay in the process of data calculation and storage. Devices based on ferroelectric materials possess the advantage of integrated data storage and computing. Nevertheless, research in the field of advanced computing has been constrained due to the incompatibility of traditional ferroelectrics (e.g., perovskites) with complementary metal oxide semiconductor (CMOS) technology and poor scalability. In recent years, research and innovation in hafnium (Hf)-based ferroelectrics have reignited interest in this field. The inherent CMOS compatibility, high coercive field (E<sub>c</sub>), and high energy band gap of Hf-based ferroelectrics make their devices highly suitable for data storage. Moreover, the negative capacitance field-effect transistor (NCFET) based on Hf-based ferroelectrics can be utilized as a representative logic computing device. In addition, the multi-level weights of biological synapses can be accurately simulated by adjusting the controllable multi-domain polarization switching in Hf-based ferroelectric films, which indicates that Hf-based ferroelectrics will also have general advantages in the field of neuromorphic computing. However, the basic mechanisms and research progress of Hf-based ferroelectrics in these advanced computing fields have not been systematically summarized and sorted out. In this paper, we summarize the latest research results of Hf-based ferroelectrics in advanced computing. We review the history of ferroelectric materials and the numerous advantages of Hf-based ferroelectrics, focusing on the working principles, research progress, and circuit applications of Hf-based ferroelectric logic and memory devices. Additionally, we review the basic concepts of neuromorphic computing, especially discussing the research progress of Hf-based ferroelectric neuromorphic devices and the circuit applications of hardware neural networks. Finally, we made a positive outlook on this field.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109053"},"PeriodicalIF":1.4,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1016/j.sse.2024.109055
Andreas Fuchsberger , Lukas Wind , Daniele Nazzari , Johannes Aberl , Enrique Prado Navarrete , Moritz Brehm , Jean-Michel Hartmann , Frank Fournel , Lilian Vogl , Peter Schweizer , Andrew M. Minor , Masiar Sistani , Walter M. Weber
Integrating Ge onto SOI should enhance the drive currents and switching speeds of transistors. However, Ge on insulator platforms have fallen short of providing these benefits and are additionally facing processing issues and high fabrication costs. To cope with these issues, we use an ultra-low-temperature molecular-beam epitaxy growth of Ge layers on SOI and strained SOI substrates, as device prototyping platforms. Thereof, we obtain symmetric IV-on-states in Ge based reconfigurable transistors, enabling to investigate the temperature-dependent gating capabilities and identify the dominant transport mechanisms. In this respect, to give a comprehensive picture of the influence of different parameters on transport mechanisms, temperature-dependent gate- and bias-dependent current–voltage data was evaluated constructing 2-D colormap representations.
{"title":"Temperature-dependent electronic transport in reconfigurable transistors based on Ge on SOI and strained SOI platforms","authors":"Andreas Fuchsberger , Lukas Wind , Daniele Nazzari , Johannes Aberl , Enrique Prado Navarrete , Moritz Brehm , Jean-Michel Hartmann , Frank Fournel , Lilian Vogl , Peter Schweizer , Andrew M. Minor , Masiar Sistani , Walter M. Weber","doi":"10.1016/j.sse.2024.109055","DOIUrl":"10.1016/j.sse.2024.109055","url":null,"abstract":"<div><div>Integrating Ge onto SOI should enhance the drive currents and switching speeds of transistors. However, Ge on insulator platforms have fallen short of providing these benefits and are additionally facing processing issues and high fabrication costs. To cope with these issues, we use an ultra-low-temperature molecular-beam epitaxy growth of Ge layers on SOI and strained SOI substrates, as device prototyping platforms. Thereof, we obtain symmetric IV-on-states in Ge based reconfigurable transistors, enabling to investigate the temperature-dependent gating capabilities and identify the dominant transport mechanisms. In this respect, to give a comprehensive picture of the influence of different parameters on transport mechanisms, temperature-dependent gate- and bias-dependent current–voltage data was evaluated constructing 2-D colormap representations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109055"},"PeriodicalIF":1.4,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143464296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the effect of incorporating gold nanoparticles (Au NPs) into the poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) active layer of organic solar cells (OSCs). GPVDM simulation software was used to analyze the power conversion efficiency (PCE) along with other photovoltaic properties, including open-circuit voltage (Voc), short-circuit current density (Jsc), and fill factor (FF), in both conventional and inverted architectures. The addition of a 5% concentration of Au NPs led to a significant increase in PCE, with a maximum value of 6.46% in specific buffer layer configurations, compared to 4.65% in devices without Au NPs. The effect of varying hole blocking layer (HBL) materials, such as BPhen, ZnO, and TiOx, was also examined, revealing improvements in device performance, with BPhen achieving the highest efficiency among the tested materials.
{"title":"Gold nanoparticles in P3HT: PCBM active layer: A simulation of new organic solar cell designs","authors":"Noureddine Benaya , Mohammed Madani Taouti , Khalid Bougnina , Bahri Deghfel , Abdelhalim Zoukel","doi":"10.1016/j.sse.2025.109056","DOIUrl":"10.1016/j.sse.2025.109056","url":null,"abstract":"<div><div>This study investigates the effect of incorporating gold nanoparticles (Au NPs) into the poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) active layer of organic solar cells (OSCs). GPVDM simulation software was used to analyze the power conversion efficiency (PCE) along with other photovoltaic properties, including open-circuit voltage (Voc), short-circuit current density (Jsc), and fill factor (FF), in both conventional and inverted architectures. The addition of a 5% concentration of Au NPs led to a significant increase in PCE, with a maximum value of 6.46% in specific buffer layer configurations, compared to 4.65% in devices without Au NPs. The effect of varying hole blocking layer (HBL) materials, such as BPhen, ZnO, and TiOx, was also examined, revealing improvements in device performance, with BPhen achieving the highest efficiency among the tested materials.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109056"},"PeriodicalIF":1.4,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-02DOI: 10.1016/j.sse.2024.109054
Minhyun Jin
In this paper, heat-path layout technique to mitigate the self-heating effects in transistors are presented. As process nodes continue to shrink, managing heat dissipation becomes increasingly crucial. A heat-path layout technique is introduced to improve heat dissipation, which enhances thermal conductivity by stacking dummy metals and vias in the drain region which is a hot spot. This approach effectively reduces both thermal resistance and thermal capacitance. Experiments were conducted using various process nodes to evaluate the effects of different types and placements of heat paths on heat generation and mitigation. The results demonstrate that the proposed heat-path layout technique become increasingly effective as process nodes scale down, providing valuable insights for thermal and electrical optimization in circuit design using next-generation devices.
{"title":"Heat-path layout technique for thermal mitigation in advanced CMOS technologies","authors":"Minhyun Jin","doi":"10.1016/j.sse.2024.109054","DOIUrl":"10.1016/j.sse.2024.109054","url":null,"abstract":"<div><div>In this paper, heat-path layout technique to mitigate the self-heating effects in transistors are presented. As process nodes continue to shrink, managing heat dissipation becomes increasingly crucial. A heat-path layout technique is introduced to improve heat dissipation, which enhances thermal conductivity by stacking dummy metals and vias in the drain region which is a hot spot. This approach effectively reduces both thermal resistance and thermal capacitance. Experiments were conducted using various process nodes to evaluate the effects of different types and placements of heat paths on heat generation and mitigation. The results demonstrate that the proposed heat-path layout technique become increasingly effective as process nodes scale down, providing valuable insights for thermal and electrical optimization in circuit design using next-generation devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109054"},"PeriodicalIF":1.4,"publicationDate":"2025-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143131528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1016/j.sse.2024.109033
N. Ghenzi , C. Acha
Mn/TiO2/Mn devices, prepared by reactive sputtering and photolithography techniques, were characterized by analyzing their current–voltage (I-V) dependence, non-volatile memory properties, and artificial synapse behavior. The detailed study of its I-V characteristics allowed for highlighting the main conduction mechanisms involved in the electrical transport through the Mn-TiO2 junctions and determining an equivalent circuit model. These results show that the oxidation of metallic Mn electrodes and the application of electrical pulses produce a complex scenario associated with a highly inhomogeneous oxygen vacancy distribution. The resistance hysteresis switching loops were determined, as well as the synaptic-like weight depreciation and potentiation, revealing a linear dependence of the reset voltage as a function of the amplitude of the set voltage and a quasi-linear variation of the conductance with the number of applied pulses. Simulations based on spiking neural network architecture, considering different updates of the synaptic weights, were trained to learn handwriting patterns. Notably, those based on the linear learning rule of the Mn/TiO2/Mn devices outperformed others with increasing non-linear behavior, demonstrating both high recognition and noise tolerance factors, further highlighting the robustness of this approach.
{"title":"Exploring the synaptic response of reactive Mn electrodes based TiO2 resistive switches","authors":"N. Ghenzi , C. Acha","doi":"10.1016/j.sse.2024.109033","DOIUrl":"10.1016/j.sse.2024.109033","url":null,"abstract":"<div><div>Mn/TiO<sub>2</sub>/Mn devices, prepared by reactive sputtering and photolithography techniques, were characterized by analyzing their current–voltage (I-V) dependence, non-volatile memory properties, and artificial synapse behavior. The detailed study of its I-V characteristics allowed for highlighting the main conduction mechanisms involved in the electrical transport through the Mn-TiO<sub>2</sub> junctions and determining an equivalent circuit model. These results show that the oxidation of metallic Mn electrodes and the application of electrical pulses produce a complex scenario associated with a highly inhomogeneous oxygen vacancy distribution. The resistance hysteresis switching loops were determined, as well as the synaptic-like weight depreciation and potentiation, revealing a linear dependence of the reset voltage as a function of the amplitude of the set voltage and a quasi-linear variation of the conductance with the number of applied pulses. Simulations based on spiking neural network architecture, considering different updates of the synaptic weights, were trained to learn handwriting patterns. Notably, those based on the linear learning rule of the Mn/TiO<sub>2</sub>/Mn devices outperformed others with increasing non-linear behavior, demonstrating both high recognition and noise tolerance factors, further highlighting the robustness of this approach.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109033"},"PeriodicalIF":1.4,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142744360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-24DOI: 10.1016/j.sse.2024.109034
Hengbo Hou , Jiansong Yue , Zhankai Li , Ning Hu , Qiang Wei
Pulsed lasers are employed to simulate Single Event Effects (SEEs) on Earth, with their feasibility empirically validated. In practical applications, it is necessary to correlate laser test results with high-energy particle measurements to accurately predict spatial SEE rates. Most of the current methods rely on charge collection RPP models or nested RPP models for laser-energy particle correlation. These models have not yet accounted for the effect of ionization trace differences. In this paper, ionization traces with different radial dimensions are obtained at different depths inside a bipolar device operational amplifier LM324 by adjusting the defocusing amount of the laser. This study compares charge collection generated by the laser with different characteristic ionization traces and analyzes experimental error factors and the charge collection mechanism. The results indicate that the radial size of the ionization traces inside the device is the main factor affecting the charge collection. Larger radial size of ionization traces on the surface area of the device results in greater charge collection, while smaller radial size of ionization traces in the depletion area and the substrate layer leads to increased charge collection. Additionally, efforts should be made to minimize the effects of movement accuracy errors and off-axis angle errors on the quantitative characterization of the test.
{"title":"Exploration of single-event effects under defocused laser irradiation: Analysis of charge collection in bipolar devices","authors":"Hengbo Hou , Jiansong Yue , Zhankai Li , Ning Hu , Qiang Wei","doi":"10.1016/j.sse.2024.109034","DOIUrl":"10.1016/j.sse.2024.109034","url":null,"abstract":"<div><div>Pulsed lasers are employed to simulate Single Event Effects (SEEs) on Earth, with their feasibility empirically validated. In practical applications, it is necessary to correlate laser test results with high-energy particle measurements to accurately predict spatial SEE rates. Most of the current methods rely on charge collection RPP models or nested RPP models for laser-energy particle correlation. These models have not yet accounted for the effect of ionization trace differences. In this paper, ionization traces with different radial dimensions are obtained at different depths inside a bipolar device operational amplifier LM324 by adjusting the defocusing amount of the laser. This study compares charge collection generated by the laser with different characteristic ionization traces and analyzes experimental error factors and the charge collection mechanism. The results indicate that the radial size of the ionization traces inside the device is the main factor affecting the charge collection. Larger radial size of ionization traces on the surface area of the device results in greater charge collection, while smaller radial size of ionization traces in the depletion area and the substrate layer leads to increased charge collection. Additionally, efforts should be made to minimize the effects of movement accuracy errors and off-axis angle errors on the quantitative characterization of the test.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109034"},"PeriodicalIF":1.4,"publicationDate":"2024-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142744359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-24DOI: 10.1016/j.sse.2024.109036
Jihye Hwang, Ilgu Yun
The characteristic comparison of the capacitor-less DRAMs in the structural form variation is investigated. Based on the simulation results of the three basic structures, such as circular, square, and rectangular nanosheets, the gate length (Lg), channel thickness (Tsi), and width of the nanosheet (Wsi) are considered as the main factors in design and the characteristic variations are verified according to the junctionless (JL) gate-all-around (GAA) geometry factors. The channel thickness is a major factor that has a major influence on the sensing margin and the retention time, which are important characteristics of DRAM. The thinner the thickness, the more deteriorated the sensing margin is confirmed. Retention time is due to the influence of the electric field distribution of the JL GAA structure, resulting in differences in structure. Finally, the rectangular type nanosheet is implemented in the stacked structure. As the number of stacks increases, the effective channel width increases compared to the layout footprint. In addition, by stacking vertically, the area where holes can be stored increases. Therefore, the sensing margin tends to increase as the number of stacks increases. However, the difference in diffusion due to the difference in the initially stored hole density, the retention time deteriorates as the number of stacks increases.
{"title":"Comparative analysis of capacitorless DRAM performance according to stacked junctionless gate-all-around structures","authors":"Jihye Hwang, Ilgu Yun","doi":"10.1016/j.sse.2024.109036","DOIUrl":"10.1016/j.sse.2024.109036","url":null,"abstract":"<div><div>The characteristic comparison of the capacitor-less DRAMs in the structural form variation is investigated. Based on the simulation results of the three basic structures, such as circular, square, and rectangular nanosheets, the gate length (L<sub>g</sub>), channel thickness (T<sub>si</sub>), and width of the nanosheet (W<sub>si</sub>) are considered as the main factors in design and the characteristic variations are verified according to the junctionless (JL) gate-all-around (GAA) geometry factors. The channel thickness is a major factor that has a major influence on the sensing margin and the retention time, which are important characteristics of DRAM. The thinner the thickness, the more deteriorated the sensing margin is confirmed. Retention time is due to the influence of the electric field distribution of the JL GAA structure, resulting in differences in structure. Finally, the rectangular type nanosheet is implemented in the stacked structure. As the number of stacks increases, the effective channel width increases compared to the layout footprint. In addition, by stacking vertically, the area where holes can be stored increases. Therefore, the sensing margin tends to increase as the number of stacks increases. However, the difference in diffusion due to the difference in the initially stored hole density, the retention time deteriorates as the number of stacks increases.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109036"},"PeriodicalIF":1.4,"publicationDate":"2024-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142744472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-24DOI: 10.1016/j.sse.2024.109031
R. Maji , T. Rollo , S. Gangopadhyay , E. Luppi , E. Degoli , F. Nardi , L. Larcher , M. Pešić
With increasing demand for essential components in the field of electronic devices, enabling advancements in display technology, flexible electronics, and various industrial applications, thin-film transistors (TFTs) are significant. Their versatility and compatibility with low-temperature fabrication processes make them a vital element in advanced electronic systems. The use of polycrystalline silicon (Poly-Si) as the channel material is specific to TFT applications unlike single-crystal/epitaxial Si in high-performance integrated circuit transistors. Poly-Si is characterized by the presence of defects such as voids, grain boundaries (GBs), and dislocations, that exert detrimental influence on electrical conductivity and then on device performance. Understanding of these would help engineer the novel TFT devices with superior reliability. In this context, Fundamental properties of the GBs are calculated using density functional theory (DFT) and their impact on poly-Si TFTs performance and figures of merit is assessed using the Ginestra® simulation platform. To account the process contaminations, the impact of known lighter impurities on GBs is comprehensively studied. In this paper we show how material properties from DFT can be effectively virtualized to predict electronic device performance, enable fast and reliable evaluation of device sensitivity to material changes, and how outputs of this multi-scale modelling process agree with experiments.
{"title":"Defects in polysilicon channel: Insight from first principles and multi-scale modelling","authors":"R. Maji , T. Rollo , S. Gangopadhyay , E. Luppi , E. Degoli , F. Nardi , L. Larcher , M. Pešić","doi":"10.1016/j.sse.2024.109031","DOIUrl":"10.1016/j.sse.2024.109031","url":null,"abstract":"<div><div>With increasing demand for essential components in the field of electronic devices, enabling advancements in display technology, flexible electronics, and various industrial applications, thin-film transistors (TFTs) are significant. Their versatility and compatibility with low-temperature fabrication processes make them a vital element in advanced electronic systems. The use of polycrystalline silicon (Poly-Si) as the channel material is specific to TFT applications unlike single-crystal/epitaxial Si in high-performance integrated circuit transistors. Poly-Si is characterized by the presence of defects such as voids, grain boundaries (GBs), and dislocations, that exert detrimental influence on electrical conductivity and then on device performance. Understanding of these would help engineer the novel TFT devices with superior reliability. In this context, Fundamental properties of the GBs are calculated using density functional theory (DFT) and their impact on poly-Si TFTs performance and figures of merit is assessed using the Ginestra® simulation platform. To account the process contaminations, the impact of known lighter impurities on GBs is comprehensively studied. In this paper we show how material properties from DFT can be effectively virtualized to predict electronic device performance, enable fast and reliable evaluation of device sensitivity to material changes, and how outputs of this multi-scale modelling process agree with experiments.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109031"},"PeriodicalIF":1.4,"publicationDate":"2024-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142744473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-23DOI: 10.1016/j.sse.2024.109026
Ning Yang, Guoting Cheng, Jing Guo
Ferroelectric (FE) AlScN materials have been experimentally explored for memory and neuromorphic computing device applications. Here a computational study is performed to simulate the device characteristics and assess the performance potential of a ferroelectric tunnel junction (FTJ) based on AlScN. We parameterize an efficient kp Hamiltonian from the complex band structure of AlScN from ab initio density-functional theory calculations to enable efficient quantum transport simulations of the FTJ device. Using a metal–FE–graphene structure enhances the barrier height modulation and the tunneling electroresistance (TER) ratio, compared to a metal–FE–semiconductor FTJ device structure. The barrier height modulation between ON and OFF states can reach 0.7eV with a FE polarization of 25 C/cm2. Reducing the AlScN tunnel layer thickness is important for increasing the device ON current and reducing the read latency. The results indicate the importance of contact designs and FE layer thickness in the design of AlScN-based FTJ devices, and highlight the potential of AlScN FTJ for future memory device technology applications.
{"title":"A computational study of AlScN-based ferroelectric tunnel junction","authors":"Ning Yang, Guoting Cheng, Jing Guo","doi":"10.1016/j.sse.2024.109026","DOIUrl":"10.1016/j.sse.2024.109026","url":null,"abstract":"<div><div>Ferroelectric (FE) AlScN materials have been experimentally explored for memory and neuromorphic computing device applications. Here a computational study is performed to simulate the device characteristics and assess the performance potential of a ferroelectric tunnel junction (FTJ) based on AlScN. We parameterize an efficient k<span><math><mi>⋅</mi></math></span>p Hamiltonian from the complex band structure of AlScN from <em>ab initio</em> density-functional theory calculations to enable efficient quantum transport simulations of the FTJ device. Using a metal–FE–graphene structure enhances the barrier height modulation and the tunneling electroresistance (TER) ratio, compared to a metal–FE–semiconductor FTJ device structure. The barrier height modulation between ON and OFF states can reach <span><math><mo>∼</mo></math></span> 0.7eV with a FE polarization of 25 <span><math><mi>μ</mi></math></span>C/cm<sup>2</sup>. Reducing the AlScN tunnel layer thickness is important for increasing the device ON current and reducing the read latency. The results indicate the importance of contact designs and FE layer thickness in the design of AlScN-based FTJ devices, and highlight the potential of AlScN FTJ for future memory device technology applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"223 ","pages":"Article 109026"},"PeriodicalIF":1.4,"publicationDate":"2024-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142719881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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