Pub Date : 2025-10-27DOI: 10.1016/j.sse.2025.109286
Quoc Tuan Tran , Nguyen Phuong Tran
The deployment of fast-charging infrastructure for electric vehicles (EVs) demands power conversion systems that are compact, efficient, and capable of delivering high power. Silicon Carbide (SiC) MOSFETs offer substantial advantages over conventional Silicon (Si) devices, particularly in switching speed and thermal performance. This study evaluates AC–DC and DC–DC converters employing SiC MOSFETs for fast EV charging applications. Simulation analyses compare SiC-based designs with IGBT-based systems and examine multiple fast-charging topologies. The investigation, for different topologies of SiC converters, addresses losses, efficiency, total harmonic distortion (THD), control strategies, and ancillary services enabled by EVs, including voltage regulation, dynamic response, and vehicle-to-grid (V2G) functionality.
{"title":"Performance evaluation of SiC MOSFET-based converter for EV fast charging systems","authors":"Quoc Tuan Tran , Nguyen Phuong Tran","doi":"10.1016/j.sse.2025.109286","DOIUrl":"10.1016/j.sse.2025.109286","url":null,"abstract":"<div><div>The deployment of fast-charging infrastructure for electric vehicles (EVs) demands power conversion systems that are compact, efficient, and capable of delivering high power. Silicon Carbide (SiC) MOSFETs offer substantial advantages over conventional Silicon (Si) devices, particularly in switching speed and thermal performance. This study evaluates AC–DC and DC–DC converters employing SiC MOSFETs for fast EV charging applications. Simulation analyses compare SiC-based designs with IGBT-based systems and examine multiple fast-charging topologies. The investigation, for different topologies of SiC converters, addresses losses, efficiency, total harmonic distortion (THD), control strategies, and ancillary services enabled by EVs, including voltage regulation, dynamic response, and vehicle-to-grid (V2G) functionality.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109286"},"PeriodicalIF":1.4,"publicationDate":"2025-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-26DOI: 10.1016/j.sse.2025.109271
Junseong Park , Haesung Kim , Sung-Jin Choi , Dae Hwan Kim , Dong Myong Kim , Jong-Ho Bae
Amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs) are highly promising for applications such as embedded memory in CMOS BEOL 2T-DRAM due to their low leakage current and high field-effective mobility. This study systematically analyzes the a-IGZO TFTs, focusing on their low-frequency noise (LFN) characteristics with varying contact metals. We fabricated the staggered a-IGZO TFTs utilizing gate, source and drain metals with different work functions (Mo ∼ 4.6 eV and Pd ∼ 5.1 eV) to investigate the impact of electrode materials on device performance. The findings demonstrate distinct LFN characteristics influenced by the contact properties. Specifically, the device with Mo source and drain exhibits behavior consistent with carrier mobility fluctuation (CMF), while the device with Pd shows Schottky barrier height fluctuation in low current regions and carrier number fluctuation (CNF) in high current regions. This differentiation in noise characteristics is crucial for understanding and optimizing the device operation mechanism, performance and reliability in advanced memory applications. The result highlights the importance of selecting appropriate contact materials to minimize noise and enhance device performance, providing valuable insights for the design and development of high-performance a-IGZO TFT-based memory technologies.
{"title":"Exploring low-frequency noise dynamics in a-IGZO TFTs: Unveiling the impact of contact metal variations for advanced semiconductor applications","authors":"Junseong Park , Haesung Kim , Sung-Jin Choi , Dae Hwan Kim , Dong Myong Kim , Jong-Ho Bae","doi":"10.1016/j.sse.2025.109271","DOIUrl":"10.1016/j.sse.2025.109271","url":null,"abstract":"<div><div>Amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs) are highly promising for applications such as embedded memory in CMOS BEOL 2T-DRAM due to their low leakage current and high field-effective mobility. This study systematically analyzes the a-IGZO TFTs, focusing on their low-frequency noise (LFN) characteristics with varying contact metals. We fabricated the staggered a-IGZO TFTs utilizing gate, source and drain metals with different work functions (Mo ∼ 4.6 eV and Pd ∼ 5.1 eV) to investigate the impact of electrode materials on device performance. The findings demonstrate distinct LFN characteristics influenced by the contact properties. Specifically, the device with Mo source and drain exhibits behavior consistent with carrier mobility fluctuation (CMF), while the device with Pd shows Schottky barrier height fluctuation in low current regions and carrier number fluctuation (CNF) in high current regions. This differentiation in noise characteristics is crucial for understanding and optimizing the device operation mechanism, performance and reliability in advanced memory applications. The result highlights the importance of selecting appropriate contact materials to minimize noise and enhance device performance, providing valuable insights for the design and development of high-performance a-IGZO TFT-based memory technologies.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109271"},"PeriodicalIF":1.4,"publicationDate":"2025-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-25DOI: 10.1016/j.sse.2025.109269
Eric Vandermolen , Philippe Ferrandis , Frédéric Allibert , Emmanuel Augendre , Massinissa Nabet , Martin Rack , Jean-Pierre Raskin , Mikaël Cassé
In this work, radio-frequency and traps properties of unintentionally doped polycrystalline silicon (polySi) deposited by low pressure chemical vapor deposition (LPCVD) on high resistivity silicon (HR-Si) substrate are characterized. Both volume (i.e. inside polySi) and interface traps (i.e. near polySi/HR-Si) are detected by photo-induced current transient spectroscopy (PICTS). A thermal budget of 900 °C during 2 h is sufficient to observe trap densities reduction near the polySi/HR-Si interface, affecting the RF performance of the fabricated substrates.
{"title":"Traps and radio-frequency characterization of polysilicon layer on high resistivity silicon substrate","authors":"Eric Vandermolen , Philippe Ferrandis , Frédéric Allibert , Emmanuel Augendre , Massinissa Nabet , Martin Rack , Jean-Pierre Raskin , Mikaël Cassé","doi":"10.1016/j.sse.2025.109269","DOIUrl":"10.1016/j.sse.2025.109269","url":null,"abstract":"<div><div>In this work, radio-frequency and traps properties of unintentionally doped polycrystalline silicon (polySi) deposited by low pressure chemical vapor deposition (LPCVD) on high resistivity silicon (HR-Si) substrate are characterized. Both volume (i.e. inside polySi) and interface traps (i.e. near polySi/HR-Si) are detected by photo-induced current transient spectroscopy (PICTS). A thermal budget of 900 °C during 2 h is sufficient to observe trap densities reduction near the polySi/HR-Si interface, affecting the RF performance of the fabricated substrates.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109269"},"PeriodicalIF":1.4,"publicationDate":"2025-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145467747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-21DOI: 10.1016/j.sse.2025.109267
Kamil Ber , Piotr Wiśniewski
This work presents the modeling and analysis of PUFs based on Resistive Random-Access Memory (RRAM) devices. Empirical data is utilized to identify statistical distributions that best replicate the stochastic nature of RRAM cells. Parameters for random variables simulating SET/RESET voltages and Low/High Resistance State (LRS/HRS) currents are extracted from current-voltage (I-V) measurements. This simplified behavioral model is subsequently used to evaluate the potential of a given manufacturing technology as a basis for developing energy-efficient hardware PUFs [1,2].
{"title":"Modeling of RRAM based PUF: a case study","authors":"Kamil Ber , Piotr Wiśniewski","doi":"10.1016/j.sse.2025.109267","DOIUrl":"10.1016/j.sse.2025.109267","url":null,"abstract":"<div><div>This work presents the modeling and analysis of PUFs based on Resistive Random-Access Memory (RRAM) devices. Empirical data is utilized to identify statistical distributions that best replicate the stochastic nature of RRAM cells. Parameters for random variables simulating SET/RESET voltages and Low/High Resistance State (LRS/HRS) currents are extracted from current-voltage (I-V) measurements. This simplified behavioral model is subsequently used to evaluate the potential of a given manufacturing technology as a basis for developing energy-efficient hardware PUFs [<span><span>1</span></span>,<span><span>2</span></span>].</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109267"},"PeriodicalIF":1.4,"publicationDate":"2025-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-11DOI: 10.1016/j.sse.2025.109264
C. Fenouillet-Beranger, O. Rozeau, R. Chouk, O. Cueto, A-S. Royet, M. Charbonneau, B. Mohamad, L. Brévard, Z. Chalupa, A. Bond, F. Baudin, L. Brunet, P. Rodriguez, R. Gassilloud, T. Mota-Frutuoso, P. Pimenta-Barros, S. Beaurepaire, V. Lapras, J. Kanyandekwe, E. Petitprez, D. Noguet
This paper will review the device specifications and the key technological boosters that are targeted in view of pursuing the FD-SOI roadmap down to the 10 nm and 7 nm nodes. In order to achieve the electrical specifications for both 10 nm and 7 nm FD-SOI devices the mobility improvement is key. Thanks to the combination of global (at wafer level) and local strain boosters (at device level), the reduction of parasitic (by introduction of low-k spacers) and two original technological options for design flexibility, the targeted performances should be reached.
{"title":"Pursuing the FD-SOI roadmap down to 10 nm and 7 nm nodes for high energy efficient, low power and RF/mmWave applications","authors":"C. Fenouillet-Beranger, O. Rozeau, R. Chouk, O. Cueto, A-S. Royet, M. Charbonneau, B. Mohamad, L. Brévard, Z. Chalupa, A. Bond, F. Baudin, L. Brunet, P. Rodriguez, R. Gassilloud, T. Mota-Frutuoso, P. Pimenta-Barros, S. Beaurepaire, V. Lapras, J. Kanyandekwe, E. Petitprez, D. Noguet","doi":"10.1016/j.sse.2025.109264","DOIUrl":"10.1016/j.sse.2025.109264","url":null,"abstract":"<div><div>This paper will review the device specifications and the key technological boosters that are targeted in view of pursuing the FD-SOI roadmap down to the 10 nm and 7 nm nodes. In order to achieve the electrical specifications for both 10 nm and 7 nm FD-SOI devices the mobility improvement is key. Thanks to the combination of global (at wafer level) and local strain boosters (at device level), the reduction of parasitic (by introduction of low-k spacers) and two original technological options for design flexibility, the targeted performances should be reached.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"231 ","pages":"Article 109264"},"PeriodicalIF":1.4,"publicationDate":"2025-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145419421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to its excellent electrical performance and compatibility with CMOS processing, polycrystalline silicon TFT has been applied in AMOLED display backplane. As short channel length can potentially benefit current density and cutoff frequency, polycrystalline silicon vertical TFT can be applied in conventional 2-transistor and 1-capcitor (2T1C) pixel unit. The fabrication of polycrystalline silicon vertical TFT was introduced, and the electrical characteristics of the fabricated device was demonstrated. Thereafter, the electrical parameters of the vertical TFT were analyzed and compared under different electrical stress durations, which interprets the inherent mechanism of the stress instability. The total density of states (DOS) and interface DOS of the fabricated devices also indicate that the stress instability is due to charge trapping in gate dielectric layer. The electrical instability is simulated by using high-k gate dielectric layer, and the reduced electrical field in the gate dielectric layer can potentially improve the electrical stability. Finally, 2T1C configuration of AMOLED pixel unit shows the influence of gate dielectric layer on the stress stability, the TFTs with high-k gate dielectric layer shows higher stress stability and lower error rate of OLED current.
{"title":"Interpretation of electrical instability for polycrystalline silicon vertical TFT","authors":"Peng Zhang , Emmanuel Jacques , Régis Rogel , Laurent Pichon , Olivier Bonnaud","doi":"10.1016/j.sse.2025.109263","DOIUrl":"10.1016/j.sse.2025.109263","url":null,"abstract":"<div><div>Due to its excellent electrical performance and compatibility with CMOS processing, polycrystalline silicon TFT has been applied in AMOLED display backplane. As short channel length can potentially benefit current density and cutoff frequency, polycrystalline silicon vertical TFT can be applied in conventional 2-transistor and 1-capcitor (2T1C) pixel unit. The fabrication of polycrystalline silicon vertical TFT was introduced, and the electrical characteristics of the fabricated device was demonstrated. Thereafter, the electrical parameters of the vertical TFT were analyzed and compared under different electrical stress durations, which interprets the inherent mechanism of the stress instability. The total density of states (DOS) and interface DOS of the fabricated devices also indicate that the stress instability is due to charge trapping in gate dielectric layer. The electrical instability is simulated by using high-<em>k</em> gate dielectric layer, and the reduced electrical field in the gate dielectric layer can potentially improve the electrical stability. Finally, 2T1C configuration of AMOLED pixel unit shows the influence of gate dielectric layer on the stress stability, the TFTs with high-<em>k</em> gate dielectric layer shows higher stress stability and lower error rate of OLED current.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109263"},"PeriodicalIF":1.4,"publicationDate":"2025-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145320062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-10DOI: 10.1016/j.sse.2025.109257
Pierpaolo Palestri , Luca Sayadi , Andrea Minetto , Gerhard Prechtl , Luca Selmi , Oliver Häberlen
We investigate the injection of hot electrons in the passivation layer above the drift region of GaN HEMTs by means of Monte-Carlo transport simulations. We find that the lateral component of the electric field in the AlGaN layer delivers a non-negligible kinetic energy to the electrons, thus enhancing injection in the passivation at the top, an effect that is not captured by the standard hot-carrier injection models developed for Si devices that requires the development of ad-hoc hot-carrier injection models for GaN devices. The implications of our calculations for the understanding of reliability and dynamic- are also briefly discussed.
{"title":"Monte Carlo analysis of hot electron injection in the passivation layer of GaN HEMTs","authors":"Pierpaolo Palestri , Luca Sayadi , Andrea Minetto , Gerhard Prechtl , Luca Selmi , Oliver Häberlen","doi":"10.1016/j.sse.2025.109257","DOIUrl":"10.1016/j.sse.2025.109257","url":null,"abstract":"<div><div>We investigate the injection of hot electrons in the passivation layer above the drift region of GaN HEMTs by means of Monte-Carlo transport simulations. We find that the lateral component of the electric field in the AlGaN layer delivers a non-negligible kinetic energy to the electrons, thus enhancing injection in the passivation at the top, an effect that is not captured by the standard hot-carrier injection models developed for Si devices that requires the development of ad-hoc hot-carrier injection models for GaN devices. The implications of our calculations for the understanding of reliability and dynamic-<span><math><msub><mrow><mi>R</mi></mrow><mrow><mi>o</mi><mi>n</mi></mrow></msub></math></span> are also briefly discussed.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109257"},"PeriodicalIF":1.4,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145320063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-09DOI: 10.1016/j.sse.2025.109258
Geon Kim , Jin So , Eungi Hwang , Jun Lee , Garam Kim
As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.
{"title":"Design and analysis of source-side raised SiGe storage for improved sensing margin in 1T DRAM","authors":"Geon Kim , Jin So , Eungi Hwang , Jun Lee , Garam Kim","doi":"10.1016/j.sse.2025.109258","DOIUrl":"10.1016/j.sse.2025.109258","url":null,"abstract":"<div><div>As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109258"},"PeriodicalIF":1.4,"publicationDate":"2025-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the performance of monolithic on-chip planar transformers implemented on high-resistivity substrates incorporating a trap-rich layer (HR-Si + TR), using both experimental measurements and electromagnetic simulations. Two transformer topologies, i.e., interleaved and concentric, were fabricated, measured, and simulated on both standard silicon (Std-Si) and HR-Si + TR to assess the impact of substrate losses. Key figures of merit, including self-resonant frequency (SRF), mutual inductance, reactive and resistive coupling factors, and maximum power-transfer efficiency, were extracted and compared. Results show that the HR-Si + TR substrate markedly enhances both topologies: for the interleaved transformer, the SRF increases by 3.8 % from 3.66 to 3.80 GHz, while the peak power-transfer efficiency nearly doubles from 0.33 at 1.42 GHz to 0.63 at 2.26 GHz; for the concentric transformer, the SRF rises by over 31 % from 3.12 to 4.10 GHz, and the efficiency increases more than threefold from 0.06 at 1.48 GHz to 0.22 at 2.15 GHz. These improvements arise from the HR-Si + TR substrate’s ability to substantially reduce the resistive mutual coupling factor by minimizing eddy current losses in the substrate and raising the impedance of the RC leakage path to ground, thereby limiting trace crosstalk and power leakage between traces. The benefits are particularly pronounced in the concentric topology, where the larger winding separation amplifies the impact of reduced substrate-induced losses.
{"title":"Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics","authors":"Najeh Zeidi , Farès Tounsi , Jean-Pierre Raskin , Denis Flandre","doi":"10.1016/j.sse.2025.109261","DOIUrl":"10.1016/j.sse.2025.109261","url":null,"abstract":"<div><div>This paper investigates the performance of monolithic on-chip planar transformers implemented on high-resistivity substrates incorporating a trap-rich layer (HR-Si + TR), using both experimental measurements and electromagnetic simulations. Two transformer topologies, i.e., interleaved and concentric, were fabricated, measured, and simulated on both standard silicon (Std-Si) and HR-Si + TR to assess the impact of substrate losses. Key figures of merit, including self-resonant frequency (SRF), mutual inductance, reactive and resistive coupling factors, and maximum power-transfer efficiency, were extracted and compared. Results show that the HR-Si + TR substrate markedly enhances both topologies: for the interleaved transformer, the SRF increases by 3.8 % from 3.66 to 3.80 GHz, while the peak power-transfer efficiency nearly doubles from 0.33 at 1.42 GHz to 0.63 at 2.26 GHz; for the concentric transformer, the SRF rises by over 31 % from 3.12 to 4.10 GHz, and the efficiency increases more than threefold from 0.06 at 1.48 GHz to 0.22 at 2.15 GHz. These improvements arise from the HR-Si + TR substrate’s ability to substantially reduce the resistive mutual coupling factor by minimizing eddy current losses in the substrate and raising the impedance of the RC leakage path to ground, thereby limiting trace crosstalk and power leakage between traces. The benefits are particularly pronounced in the concentric topology, where the larger winding separation amplifies the impact of reduced substrate-induced losses.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109261"},"PeriodicalIF":1.4,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-04DOI: 10.1016/j.sse.2025.109262
G. Vinuesa , T. del Val , K. Kalam , H. García , M.B. González , F. Campabadal , S. Dueñas , H. Castán
In this study, resistive switching in three structures with HfO, AlO, and bilayer (HfO + AlO) oxides is studied. Electrical characterization reveals differences in switching dynamics and performance across these configurations, highlighting the impact of oxide composition and structure on device behavior. The time needed to reset is defined and studied in detail, showing an exponential dependence with the applied voltage. Finally, an initial assessment of the effect that the set and reset transient has on the multilevel capabilities of the devices is made.
{"title":"Effect of set and reset dynamics on HfO2, Al2O3, and bilayer memristors","authors":"G. Vinuesa , T. del Val , K. Kalam , H. García , M.B. González , F. Campabadal , S. Dueñas , H. Castán","doi":"10.1016/j.sse.2025.109262","DOIUrl":"10.1016/j.sse.2025.109262","url":null,"abstract":"<div><div>In this study, resistive switching in three structures with HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>, Al<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>O<span><math><msub><mrow></mrow><mrow><mn>3</mn></mrow></msub></math></span>, and bilayer (HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> + Al<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>O<span><math><msub><mrow></mrow><mrow><mn>3</mn></mrow></msub></math></span>) oxides is studied. Electrical characterization reveals differences in switching dynamics and performance across these configurations, highlighting the impact of oxide composition and structure on device behavior. The time needed to reset is defined and studied in detail, showing an exponential dependence with the applied voltage. Finally, an initial assessment of the effect that the set and reset transient has on the multilevel capabilities of the devices is made.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109262"},"PeriodicalIF":1.4,"publicationDate":"2025-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
扫码关注我们
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号