Solid-state Electronics最新文献_第5页

A computational study of AlScN-based ferroelectric tunnel junction 基于 AlScN 的铁电隧道结的计算研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-23 DOI: 10.1016/j.sse.2024.109026

Ning Yang, Guoting Cheng, Jing Guo

Ferroelectric (FE) AlScN materials have been experimentally explored for memory and neuromorphic computing device applications. Here a computational study is performed to simulate the device characteristics and assess the performance potential of a ferroelectric tunnel junction (FTJ) based on AlScN. We parameterize an efficient k

\cdot

p Hamiltonian from the complex band structure of AlScN from ab initio density-functional theory calculations to enable efficient quantum transport simulations of the FTJ device. Using a metal–FE–graphene structure enhances the barrier height modulation and the tunneling electroresistance (TER) ratio, compared to a metal–FE–semiconductor FTJ device structure. The barrier height modulation between ON and OFF states can reach

\sim

0.7eV with a FE polarization of 25

μ

C/cm². Reducing the AlScN tunnel layer thickness is important for increasing the device ON current and reducing the read latency. The results indicate the importance of contact designs and FE layer thickness in the design of AlScN-based FTJ devices, and highlight the potential of AlScN FTJ for future memory device technology applications.

铁电（FE）AlScN 材料已在存储器和神经形态计算设备应用方面进行了实验探索。在此，我们进行了一项计算研究，以模拟基于 AlScN 的铁电隧道结 (FTJ) 的器件特性并评估其性能潜力。我们根据原子序数密度泛函理论计算得出的 AlScN 复杂能带结构，为高效的 k⋅p 哈密顿参数设置了参数，从而实现了 FTJ 器件的高效量子输运模拟。与金属-FE-半导体 FTJ 器件结构相比，金属-FE-石墨烯结构增强了势垒高度调制和隧穿电阻（TER）比。在 25 μC/cm2 的 FE 极化条件下，导通态和关断态之间的势垒高度调制可达 0.7eV。减小 AlScN 隧道层厚度对于增加器件导通电流和减少读取延迟非常重要。这些结果表明了接触设计和 FE 层厚度在基于 AlScN 的 FTJ 器件设计中的重要性，并凸显了 AlScN FTJ 在未来存储器件技术应用中的潜力。

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引用次数: 0

Effect of Al2O3 on the operation of SiNX-based MIS RRAMs Al2O3对sinx基MIS rram运行的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-22 DOI: 10.1016/j.sse.2024.109035

A.E. Mavropoulis , N. Vasileiadis , P. Normand , C. Theodorou , G. Ch. Sirakoulis , S. Kim , P. Dimitrakis

The role of a 3 nm Al₂O₃ layer on top of stoichiometric LPCVD SiN_x MIS RRAM cells is investigated by using various electrical characterization techniques. The conductive filament formation is explained, and a compact model is used to fit the current–voltage curves and find its evolution during each operation cycle. The conduction in SiN_x is also studied.

通过使用各种电表征技术，研究了化学计量LPCVD SiNx MIS RRAM电池上3nm Al2O3层的作用。解释了导电灯丝的形成过程，并建立了一个紧凑的模型来拟合电流-电压曲线，并求出其在每个运行周期内的演变。研究了SiNx中的传导。

引用次数: 0

Characterization of LDMOS down to cryogenic temperatures and modeling with PSPHV 低至低温的 LDMOS 特性及 PSPHV 建模

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-19 DOI: 10.1016/j.sse.2024.109029

Yili Wang , Kejun Xia , Guofu Niu , Michael Hamilton , Xu Cheng

This article presents a detailed characterization and analysis of a 45 V LDMOS device from production technology across a wide temperature range from 33 to 385 K. For the first time, quasi-saturation behavior is consistently observed throughout the entire temperature range studied. Compared to prior published data, this device shows some notable differences, including a substantially higher saturation temperature of around 200 K for threshold voltage and subthreshold swing due to band tail and a typical low on-resistance down to 33 K, free of freezeout. To account for the observed temperature dependencies, we propose improved semi-empirical temperature scaling equations for the PSPHV model. We extend its applicable temperature range down to 33 K from the previous lower limit of 240 K. The enhancement models the temperature behaviors of key device parameters, including threshold voltage, subthreshold swing, mobility, velocity saturation, drift resistance, and quasi-saturation effects. These results provide new insights into the low-temperature behavior of LDMOS devices for cryogenic electronics applications.

本文详细描述和分析了采用生产技术的 45 V LDMOS 器件在 33 至 385 K 宽温度范围内的特性。与之前公布的数据相比，该器件显示出一些显著差异，包括由于带尾效应，阈值电压和阈下摆动的饱和温度大大高于 200 K 左右，以及典型的低导通电阻（低至 33 K），无冻结现象。为了解释观察到的温度依赖性，我们为 PSPHV 模型提出了改进的半经验温度比例方程。我们将其适用的温度范围从以前的下限 240 K 扩展到 33 K。改进后的模型可模拟关键器件参数的温度行为，包括阈值电压、亚阈值摆幅、迁移率、速度饱和、漂移电阻和准饱和效应。这些结果为低温电子应用中 LDMOS 器件的低温行为提供了新的见解。

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引用次数: 0

A multi-level cell for ultra-scaled STT-MRAM realized by back-hopping 通过后跳实现超大规模 STT-MRAM 的多级单元

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-16 DOI: 10.1016/j.sse.2024.109027

M. Bendra , R.L. de Orio , S. Selberherr , W. Goes , V. Sverdlov

The development of advanced magnetic tunnel junctions with a footprint in the single-digit nanometer range can be achieved using structures with an elongated and composite ferromagnetic free layer. Using advanced modeling techniques, we investigated the back-hopping effect in ultra-scaled STT-MRAM devices, defined as the unintended switching of the last part of the free layer, leading to an undesired magnetization state of the free layer. To understand the switching of the free layer, the torque acting on both parts of the composite-free layer must be studied in detail. A reduction in the size of MRAM components to increase the memory density may lead to back-hopping. However, the observed back-hopping effect can also be exploited for the realization of multi-level cells. For this purpose, we have carefully investigated the switching behavior of a device with several tunnel barrier interfaces and a few nanometers in diameter. Our studies on ultra-scaled STT-MRAM devices highlight the significant back-hopping effect which, when harnessed, can enable multi-bit cells with four distinct states, enhancing storage and functionality. These insights are pivotal for the design and optimization of future miniaturized spintronics devices.

利用具有拉长和复合铁磁自由层的结构，可以开发出尺寸在个位数纳米范围内的先进磁隧道结。利用先进的建模技术，我们研究了超大规模 STT-MRAM 器件中的后跳效应，这种效应被定义为自由层最后部分的意外切换，导致自由层出现不希望的磁化状态。要了解自由层的切换，必须详细研究作用于无复合层两部分的扭矩。缩小 MRAM 元件尺寸以提高存储器密度可能会导致反跳现象。不过，观察到的反跳效应也可用于实现多级单元。为此，我们仔细研究了一个具有多个隧道势垒接口、直径只有几个纳米的器件的开关行为。我们对超尺度 STT-MRAM 器件的研究凸显了显著的后跳效应，利用这种效应可以实现具有四种不同状态的多位单元，从而增强存储和功能。这些见解对于未来微型化自旋电子器件的设计和优化至关重要。

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引用次数: 0

Temperature influence on experimental analog behavior of MISHEMTs 温度对 MISHEMT 模拟实验行为的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-13 DOI: 10.1016/j.sse.2024.109028

Welder F. Perina , Joao A. Martino , Eddy Simoen , Uthayasankaran Peralagu , Nadine Collaert , Paula G.D. Agopian

This work presents an analysis on experimental analog behavior of MISHEMTs operating in the temperature range from 450 K down to 200 K. The drain current (I_DS) presented a slight anomaly, especially for temperatures lower than 400 K. In the transconductance it is possible to visualize a second peak, suggesting a second conduction. As shown, the transconductance presented a low dependence on gate length, and an anomaly was observed for the devices at 350 K. The output conductance and transistor efficiency behavior suggest a competition between the effects of the MOS and HEMT conductions, present in the device. A new kink was observed in the output characteristic (I_DSxV_DS) at room temperature, which is caused by the HEMT and MOS conductions interaction, and it is even more noticeable for higher overdrive voltages (V_GT). This effect is called MISHEMT kink effect (MH-kink) in this work. The MH-kink shifts toward higher V_DS for higher overdrive voltage, showing the stronger influence of the MOS conduction on the total drain current. The unity gain frequency (f_t) increases from 800 MHz (450 K) to 1.8 GHz (200 K), while the A_V goes in opposite direction from 43 dB (450 K) to 38 dB (200 K). Considering that the intrinsic voltage gain is good enough even at low temperatures, the MISHEMT can be identified as a good candidate for analog applications.

这项研究分析了在 450 K 至 200 K 温度范围内工作的 MISHEMT 的模拟实验行为。漏极电流（IDS）出现了轻微异常，尤其是在低于 400 K 的温度下。如图所示，跨导对栅极长度的依赖性较低，在 350 K 时器件出现异常。输出电导和晶体管效率行为表明，器件中存在 MOS 和 HEMT 传导效应之间的竞争。在室温下的输出特性（IDSxVDS）中观察到了一种新的扭结，这是 HEMT 和 MOS 导体相互作用造成的，在过驱动电压 (VGT) 较高时更为明显。这种效应在本文中称为 MISHEMT 扭结效应（MH-kink）。当过驱动电压升高时，MH-kink 会向更高的 VDS 方向移动，这表明 MOS 导通对漏极总电流的影响更大。统一增益频率 (ft) 从 800 MHz (450 K) 上升到 1.8 GHz (200 K)，而 AV 则相反，从 43 dB (450 K) 下降到 38 dB (200 K)。考虑到即使在低温条件下，MISHEMT 的固有电压增益也足够好，因此可以确定它是模拟应用的理想候选器件。

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引用次数: 0

A novel method used to prepare PN junction by plasmon generated under pulsed laser irradiation on silicon chip 利用脉冲激光照射硅芯片产生的等离子体制备 PN 结的新方法

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-08 DOI: 10.1016/j.sse.2024.109023

Wei-Qi Huang , Yin-Lian Li , Zhong-Mei Huang , Hao-Ze Wang , Shi-Rong Liu

We prepare the PN junction on silicon chip by a novel method with surface plasmon generated under pulsed laser irradiation. It is found that the interaction between laser photons and plasma produces a plasmon layer, in which the faster electrons take resonance with photons to generate surface electron gas. It is interesting that the electron gas in high vacuum and the plasmon polarized in various atmosphere are directly observed by the Talbot reflect image with outstanding challenge. It is demonstrated that injection and diffusion can be completed quickly to form higher quality PN region on interface between ions layer and substrate while the plasmon dipole makes resonance with phonon, where the quantum energy of plasmon is closed to the phonon energy in silicon crystal. In this novel way, the PN junction structure can be built by coherent photons on silicon chip at first, and the different preparing processes are explored comparatively by using the I-V curves measured with nonlinear characteristic of PN junction for application in optic-electronic integration field.

我们采用一种在脉冲激光照射下产生表面等离子体的新方法，在硅芯片上制备了 PN 结。研究发现，激光光子和等离子体之间的相互作用产生了等离子体层，其中速度较快的电子与光子发生共振，从而产生表面电子气。有趣的是，塔尔博特反射图像可以直接观测到高真空中的电子气和各种大气中的等离子体极化，具有很高的挑战性。实验证明，注入和扩散可以快速完成，从而在离子层和衬底之间的界面上形成更高质量的 PN 区域，同时等离子体偶极子与声子产生共振，而等离子体的量子能与硅晶体中的声子能接近。通过这种新颖的方法，相干光子可以在硅芯片上首先构建 PN 结结构，并利用测量到的 PN 结非线性特性的 I-V 曲线比较探讨了不同的制备过程，从而将其应用于光电子集成领域。

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引用次数: 0

Influence of Ag-Bi2S3 nanocomposites for highly sensitive and selective Cl2 gas sensors: Synthesis, characterization, and gas sensing performance Ag-Bi2S3 纳米复合材料对高灵敏度和选择性 Cl2 气体传感器的影响：合成、表征和气体传感性能

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-02 DOI: 10.1016/j.sse.2024.109024

Gangadhar Bandewad , Chetan Kamble , Sunil Pawar

The gas sensing capabilities of Bi₂S₃ chalcogenide have been actively enhanced and explored revealing its potential for high-performance Cl₂ gas detection under different environmental conditions and sensing configurations. This work successfully synthesized Bi₂S₃ material via the SILAR method and further enhanced its sensing capabilities by fabricating Ag-Bi₂S₃ nanocomposite. Both pristine Bi₂S₃ and Ag-Bi₂S₃ nanocomposite films underwent comprehensive characterization utilizing techniques such as FESEM, EDX, XRD, XPS, and RAMAN to analyze their morphological, structural, and chemical properties. Gas sensing capabilities were evaluated across a temperature range of 26–350 °C and varying Cl₂ gas concentrations (0.1–50 ppm). The findings reveal that the Ag-Bi₂S₃ sensor demonstrates notably superior Cl₂ sensing response, particularly at an operational temperature of 150 °C, suggesting its promising potential for Cl₂ detection. The LOD has been calculated for Ag-Bi₂S₃ sensor showing results of 0.150 better than pristine Bi₂S_3. HOMO-LUMO and PCA analysis for sensors has been studied to understand their capabilities with different gas sensing.

Bi2S3 Chalcogenide 的气体传感能力得到了积极的提升和探索，揭示了其在不同环境条件和传感配置下进行高性能 Cl2 气体检测的潜力。这项研究通过 SILAR 方法成功合成了 Bi2S3 材料，并通过制备 Ag-Bi2S3 纳米复合材料进一步增强了其传感能力。利用 FESEM、EDX、XRD、XPS 和 RAMAN 等技术对原始 Bi2S3 和 Ag-Bi2S3 纳米复合薄膜进行了全面表征，分析其形态、结构和化学特性。在 26-350 °C 的温度范围和不同的 Cl2 气体浓度（0.1-50 ppm）下，对其气体传感能力进行了评估。研究结果表明，Ag-Bi2S3 传感器的 Cl2 传感响应明显优于其他传感器，尤其是在 150 ℃ 的工作温度下，这表明它在 Cl2 检测方面具有很大的潜力。计算得出的 Ag-Bi2S3 传感器的 LOD 值比原始 Bi2S3 高 0.150。对传感器的 HOMO-LUMO 和 PCA 分析进行了研究，以了解它们对不同气体的传感能力。

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引用次数: 0

Achieving 15.75% efficiency in solar cells: Advanced surface engineering using Tetra-Tert-Butyl-Tercarbazol-Benzonitrile and organic layer integration in n-type silicon wafer and hybrid Planar-Si systems 实现 15.75% 的太阳能电池效率：使用四叔丁基三咔唑-苯腈的先进表面工程以及 n 型硅晶片和混合平面硅系统中的有机层集成

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-02 DOI: 10.1016/j.sse.2024.109025

Fahim Ullah , Kamran Hasrat , Sami Iqbal , Shuang Wang

This study investigates the progress in n-type solar cells utilizing implanted Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) front surface fields and diffused Ag rear emitters. The n-type structure utilizes a systematic approach involving surface passivation, localized laser ablation, and screen printing, similar to commercial p-type solar cells. This design enables the conversion from p-type to n-type cell production. Ion implantation allows for accurate management of doping profiles, improving processing sequences and increasing efficiency. Analysis indicates that reduced post-implant annealing durations lead to a shallower doping profile, enhancing short-wavelength response. Its results in efficiencies reaching up to 15.75 % on large-area 200 cm2 n-type wafers. The study also examines hybrid planar-Si/organic heterojunction solar cells, emphasizing Tetra-Tert-Butyl-Tercarbazol-Benzonitrile (TTB-TB-BNZ) to improve photovoltaic efficiency. UV–visible and fluorescence spectroscopy indicate a maximum absorption wavelength of 360 nm and an emission wavelength of 420 nm. The concentration of TTB-TB-BNZ in (4,4′-di(9H-carbazol-9-yl)-1,1′-biphenyl) (CBP) films reaches its peak effectiveness at 40–50 %, leading to notable enhancements in light absorption and charge transport. The Si/PEDOT: PSS heterojunction solar cells incorporating TTB-TB-BNZ demonstrate a power conversion efficiency (PCE) of 15.75 %. This result underscores the potential for scalable fabrication methods to improve photovoltaic performance.

本研究探讨了利用植入式四叔丁基三咔唑-苯腈（TTB-TB-BNZ）前表面场和扩散式银后发射器的 n 型太阳能电池的研究进展。这种 n 型结构采用了与商用 p 型太阳能电池类似的系统方法，包括表面钝化、局部激光烧蚀和丝网印刷。这种设计实现了从 p 型电池到 n 型电池的生产转换。离子注入可实现对掺杂曲线的精确管理，改进加工顺序并提高效率。分析表明，缩短植入后退火持续时间可使掺杂剖面更浅，从而增强短波长响应。这使得 200 平方厘米大面积 n 型晶片的效率高达 15.75%。研究还考察了混合平面硅/有机异质结太阳能电池，强调利用四叔丁基三咔唑-苯腈（TTB-TB-BNZ）来提高光伏效率。紫外可见光谱和荧光光谱显示，其最大吸收波长为 360 纳米，发射波长为 420 纳米。在（4,4′-二（9H-咔唑-9-基）-1,1′-联苯）（CBP）薄膜中，TTB-TB-BNZ 的浓度在 40-50 % 时达到峰值效果，从而显著提高了光吸收和电荷传输能力。Si/PEDOT：PSS 异质结太阳能电池的功率转换效率 (PCE) 达到 15.75%。这一结果凸显了可扩展制造方法在提高光伏性能方面的潜力。

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引用次数: 0

Spiro-OMeTAD Anchoring perovskite for gradual homojunction in stable perovskite solar cells 在稳定的过氧化物太阳能电池中逐步实现同质结的螺氨过氧化物锚定过氧化物

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-11-01 DOI: 10.1016/j.sse.2024.109003

Ziyi Wang , Bobo Yuan , Yiheng Gao, Rui Wu, Shuping Xiao, Wuchen Xiang, Xueli Yu, Pingli Qin

The role of interface energetics-modification in interface-defect passivation and optimal interface energy-level matching is assumed to be a crucial aspect. Enhancing the performance and durability of perovskite solar cells (PSCs) can be achieved through this strategy. Here, spiro-OMeTAD [2,2′,7,7′-tetrakis (N, N-di-p-methoxyphenylamine)-9,9′-spirobifluorene] has been pipetted onto the spinning perovskite precursor film via a chlorobenzene anti-solvent strategy. It is found that spiro-OMeTAD serves as not only the filler at grain boundaries, but also the coverage on perovskite’s grain, and then forms the gradual homojunction interface from perovskite to spiro-OMeTAD hole transport layer, which can make spiro-OMeTAD anchor perovskite via the reaction between Pb²⁺ and C-O groups to decrease the interface barrier and obtain the optimal interface energy-level match between them for hole −migration and −collection. Moreover, these fillers or coverages can prevent moisture invading perovskite. Consequently, the counterpart PSC achieves a champion efficiency of 24.46 %, and has retained more than 88 % of the initial efficiency after 224 days of storage.

界面能量修饰在界面缺陷钝化和最佳界面能级匹配中的作用被认为是一个至关重要的方面。通过这种策略可以提高过氧化物太阳能电池（PSCs）的性能和耐用性。在这里，螺-OMeTAD [2,2′,7,7′-四（N,N-二对甲氧基苯胺）-9,9′-螺二芴] 通过氯苯反溶剂策略被吸附到旋转的过氧化物前驱体薄膜上。研究发现，螺-OMeTAD 不仅可以作为晶界的填充物，还可以覆盖在透辉石的晶粒上，进而形成透辉石与螺-OMeTAD 孔传输层的渐变同结界面，这可以使螺-OMeTAD 通过 Pb2+ 与 C-O 基团之间的反应锚定透辉石，从而降低界面势垒，使二者之间获得最佳的界面能级匹配，以实现孔的迁移和收集。此外，这些填充物或覆盖物还能防止水分侵入包晶。因此，对应的 PSC 实现了 24.46% 的冠军效率，并在储存 224 天后保持了超过 88% 的初始效率。

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引用次数: 0

Silicon-based integrated passive device stack for III-V/Si monolithic 3D circuits operating on RF band 用于射频波段 III-V/Si 单片 3D 电路的硅基集成无源器件堆栈

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2024-10-22 DOI: 10.1016/j.sse.2024.109012

Minsik Park , Minkyoung Seong , Jaeyong Jeong , Seungin Lee , Jonghyun Song , Hyoungho Ko , Ga-Won Lee , Woo-Suk Sul , Won-Chul Lee , Sanghyeon Kim , Jongwon Lee

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was −0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as −5.5 μm. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from −12.6 to + 10.7 μm).

在这项研究中，我们展示了一种基于硅（Si）的集成无源器件（IPD）堆栈，用于支持在射频（RF）频段工作的 III-V/Si 单片 3D (M3D) 集成电路。该 IPD 堆栈基于 8 英寸 CMOS 工艺线制造，并通过 M3D 与 InGaAs HEMT 层集成。为了同时最大限度地降低射频损耗和晶圆弯曲，在 IPD 中建立了富阱层和埋入氧化层的工艺条件。通过该工艺条件，共面波导在 30 GHz 时的射频损耗为 -0.631 dB/mm，低于 CMOS 代工厂的水平，而叠层的晶圆弯曲则低至 -5.5 μm。与迄今报道的在射频频段工作的其他基于 CMOS 代工工艺的电感器相比，电感器的最大品质因数显示出良好的数值。为了获得 IPD 叠层的压缩轮廓（这是将 III-V 有源层推进到晶圆到晶圆级 3D 粘合的最重要要求之一），开发了一种用于 IPD 最后 IMD 层的工艺方法，从而使 IPD 从拉伸轮廓变为压缩轮廓（相应的晶圆弯曲值从 -12.6 μm 到 +10.7 μm）。

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引用次数: 0