Solid-state Electronics最新文献

A density functional analysis of oxide dipole layers used to set the threshold voltages in high-K/metal CMOS gate stacks is given in terms of the band alignments and chemical trends of these component oxide layers. The oxides SrO, La₂O₃, HfO₂ and Al₂O₃ are found to have similar band gaps and form a ‘staircase’ of band alignments, allowing them to shift the metal electrode Fermi level in both n-type and p-type directions. This analysis supersedes previous largely empirical models based on metal oxide ion densities or electronegativity scales.

The threshold voltage definition and measurement in ultrathin FD-SOI MOS transistors are revisited by comparing theoretical and pragmatic extraction techniques, including novel approaches. The respective merits and limitations of methods based on the monitoring of the potential, mobile charge, gate-to-channel capacitance and drain current are emphasized. Back-gate biasing, thickness-induced quantization, potential fluctuations and surface roughness can enhance the disparity between various extraction methods. The origin of these deviations is clarified.

A new Double-BOX structure is introduced to reveal the electrical properties of undoped polysilicon used to enhance the performance of radio frequency SOI substrates. A plateau is clearly observed in the capacitance–voltage (C-V) characteristics, which is due to the influence of the potential barrier formed at the grain boundary. A tangential approximation method based on a three-element circuit model is proposed for correcting the measured C-V curve. With the corrected C-V curve, the effective trap density distribution in polysilicon is determined for each frequency.

Excessive forward leakage currents in GaN p-i-n diodes were investigated. Traditional diffusion mechanism dominates at V_F > 2 V. The effective band gap is derived to be ∼2.21 eV, which is much lower than 3.4 eV and attributed to a band fluctuation caused by dislocations; At 1.35 V < V_F < 2 V, a trap-assisted tunneling process becomes important, whose ideality factor is still larger than 4.1 at T = 400 K; Two distinct power-law relationships were observed at lower biases, separated at V_F = 0.8 V, whose exponents are extracted to be ∼8 and ∼4, respectively. The behavior is in a good agreement with the space-charge-limited model, featuring an exponentially decaying distribution of trap states below the conduction band.

This work reports the impact of gate oxide thickness on flicker noise (1/f) in 45-nm RFSOI NFET devices. In addition, the effect of finger width scaling on 1/f noise parameters is studied in linear region. The dominant source of 1/f noise is also analyzed. It is observed that thin oxide devices show carrier number fluctuation; however, for thick oxide devices, correlated number-mobility govern the noise. Extracted trap densities using 1/f noise show higher volume trap densities in thin oxide devices. Moreover, trap distribution behavior is analyzed using frequency exponent. Further, GLOBALFOUNDRIES PDK is utilized to model 1/f noise behavior of the devices.

In different environments, high concentration of n-butanol will have certain harm to the human senses and nervous system, meanwhile the electrochemical sensor limits its widespread use due to its high power consumption, so it is very meaningful to develop a semiconductor n-butanol sensor with low energy consumption. In this paper, α-Fe₂O₃ nanorods were prepared by one-step hydrothermal method and then assembled into a n-butanol sensor capable of detecting n-butanol, and the effects of two different calcination temperatures on the performance of the sensor were investigated. Due to its higher Fe³⁺ content, higher oxygen vacancy content and larger specific surface area, S1-250 provided more active sites for gas adsorption, which making the response of S1-250 to 100 ppm n-butanol at 215 °C reached to 88.4. Finally, the effect of the calcination temperature on the sensor and the response mechanism were discussed. This paper offers promising applications for low-energy n-butanol sensors assembled from a single material α −Fe₂O₃.

In this paper, InP Double-Heterojunction Bipolar Transistors (DHBTs) on a 3-inch InP substrate is demonstrated through stepper-based photolithography. The performance of the fabricated InP DHBTs such as DC characteristics, high-frequency characteristics, and uniformity of the 3-inch wafer is investigated to verify the stepper-based fabrication process. To improve the high-frequency characteristics, the self-aligned base-emitter contact is realized by using the high height-to-width ratio and vertical sidewall emitter profile of the Au electroplating process. The fabricated DHBTs with W_E = 0.6 μm and L_E = 15 μm exhibits current gain (β) = 50 at V_CE = 1.0 V and an open-base common-emitter breakdown voltage (BV_CEO) of 5.7 V at J_C = 0.01 mA/µm² and 7.5 V at J_C = 0.1 mA/µm², respectively. Moreover, the fabricated DHBTs with W_E = 0.6 μm and L_E = 15 μm show excellent f_T of 244 GHz and f_max of 221 GHz at J_C = 4.4 mA/μm² and V_CE = 1.6 V. In order to evaluate the uniformity of the fabricated DHBTs, we measure current gain (β) and high-frequency characteristics with W_E = 0.6 μm and L_E = 15 μm and the average values and standard deviation of the β, f_T, and f_max are β = 49.3 ± 1.9, f_T = 241.4 ± 3.8 GHz, and f_max = 221.5 ± 4.0 GHz, respectively. Thanks to the optimized stepper-based fabrication process, the fabricated InP DHBTs exhibit well-balanced high-frequency characteristics and excellent uniformity.

In this study, a neural network (NN) was proposed for predicting the V_T characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The V_T distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate V_T distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the V_T distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the V_T distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects.

Despite the significant potential of ferroelectric devices in overcoming the challenges faced by conventional high-k-based CMOS devices owing to the scaling of CMOS processes, most ferroelectric devices are not implemented in practical circuits yet. For practical application, integrating them into a circuit is essential, and the development of a reliable etching process is crucial for the integration of individual devices into circuits. Therefore, this study proposes a process for etching hafnium zirconium oxide (HZO)-based gate stacks to fabricate a gate structure and integrate HZO-based devices into circuits. First, poly-Si/TiN/HZO/TiN/SiO₂ was deposited on a Si substrate and etched via Cl₂ and BCl₃/Cl₂ plasma etchings. Cl₂ plasma etching was found to be less effective, whereas BCl₃/Cl₂ plasma etching exhibited a higher etching rate. The optimal etching time for the BCl₃/Cl₂ plasma at which the entire stack was successfully removed was 50 s. Furthermore, the optimal ratio of Ar:Cl₂:BCl₃ that resulted in minimal damage to the Si surface was determined to be 1:1:3. These results led to the successful formation of an HZO-based gate structure and provided the potential to integrate ferroelectric devices into the circuit, thereby enabling their practical utilization.

The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.