Pub Date : 2025-11-01Epub Date: 2025-08-19DOI: 10.1016/j.sse.2025.109219
Jinyi Wang , Yian Yin , Qiao Sun , Chunxiao Zhao , Qian Zeng , Jiahao Du , Yele Qu , Tiankai Wang , Nan Jiang
All-GaN Cascode devices have been shown to have higher switching speeds than standalone E-mode devices. However, during the switching process of the device, the breakdown voltage drops significantly, this will greatly reduce the reliability of the device, especially in the presence of voltage overshoot. In this paper, an All-GaN Cascode structure with integrated plane-parallel capacitor structure is proposed, and the breakdown voltage in the switching process is referred to as the dynamic breakdown voltage. The test results show that the dynamic breakdown voltage is increased from 497 V to 639 V compared with the conventional structure. In addition, a dual-pulse test circuit is set up to test the switching performance of All-GaN Cascode devices under different conditions, it is proved that the series structure of All-GaN Cascode device can reduce the deterioration of switching performance caused by the increase of capacitance. The above results indicate that All-GaN Cascode devices may have great application potential in high speed and high voltage switching circuits.
{"title":"An All-GaN cascode device with integrated plane-parallel capacitor with high dynamic breakdown voltage and high switching performance","authors":"Jinyi Wang , Yian Yin , Qiao Sun , Chunxiao Zhao , Qian Zeng , Jiahao Du , Yele Qu , Tiankai Wang , Nan Jiang","doi":"10.1016/j.sse.2025.109219","DOIUrl":"10.1016/j.sse.2025.109219","url":null,"abstract":"<div><div>All-GaN Cascode devices have been shown to have higher switching speeds than standalone E-mode devices. However, during the switching process of the device, the breakdown voltage drops significantly, this will greatly reduce the reliability of the device, especially in the presence of voltage overshoot. In this paper, an All-GaN Cascode structure with integrated plane-parallel capacitor structure is proposed, and the breakdown voltage in the switching process is referred to as the dynamic breakdown voltage. The test results show that the dynamic breakdown voltage is increased from 497 V to 639 V compared with the conventional structure. In addition, a dual-pulse test circuit is set up to test the switching performance of All-GaN Cascode devices under different conditions, it is proved that the series structure of All-GaN Cascode device can reduce the deterioration of switching performance caused by the increase of capacitance. The above results indicate that All-GaN Cascode devices may have great application potential in high speed and high voltage switching circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109219"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-06-23DOI: 10.1016/j.sse.2025.109162
A. Sanchez-Soares , T. Kelly , S.-K. Su , E. Chen , G. Fagas , J.C. Greer
Two-dimensional (2D) materials have attracted considerable interest for use as channel material in field-effect transistors (FETs) due to their potential for high packing densities and efficient electrostatic control. However, achieving low contact resistances remains a significant challenge for integrated circuit manufacture. This study presents a methodology that enables device simulations explicitly including the effects of contact stacks within a quantum mechanical framework. A means for optimizing device structures including contact effects is demonstrated and validated against experimental and ab initio data for metal–semimetal–semiconductor contacts for optimizing source/drain resistance in monolayer molybdenum disulfide (ML-MoS2) FETs.
{"title":"Quantum simulations of MoS2 field effect transistors including contact effects","authors":"A. Sanchez-Soares , T. Kelly , S.-K. Su , E. Chen , G. Fagas , J.C. Greer","doi":"10.1016/j.sse.2025.109162","DOIUrl":"10.1016/j.sse.2025.109162","url":null,"abstract":"<div><div>Two-dimensional (2D) materials have attracted considerable interest for use as channel material in field-effect transistors (FETs) due to their potential for high packing densities and efficient electrostatic control. However, achieving low contact resistances remains a significant challenge for integrated circuit manufacture. This study presents a methodology that enables device simulations explicitly including the effects of contact stacks within a quantum mechanical framework. A means for optimizing device structures including contact effects is demonstrated and validated against experimental and <em>ab initio</em> data for metal–semimetal–semiconductor contacts for optimizing source/drain resistance in monolayer molybdenum disulfide (ML-MoS<sub>2</sub>) FETs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109162"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144631986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-08-12DOI: 10.1016/j.sse.2025.109207
Michelly de Souza , Marcelo A. Pavanello , Mikaël Cassé , Sylvain Barraud
This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.
{"title":"Experimental investigation of 7-level stacked nanosheet nMOSFETs for high-temperature applications","authors":"Michelly de Souza , Marcelo A. Pavanello , Mikaël Cassé , Sylvain Barraud","doi":"10.1016/j.sse.2025.109207","DOIUrl":"10.1016/j.sse.2025.109207","url":null,"abstract":"<div><div>This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109207"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144885395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-08-15DOI: 10.1016/j.sse.2025.109214
X. Pérez , R. Picos , J. Suñé , E. Miranda
In this letter, a fully behavioral SPICE model for M × N memristive crosspoint arrays (CPAs) is presented. The proposed approach incorporates the current–voltage characteristics of the memdiode model for resistive switching devices, which can account for both the linear (low-voltage) and nonlinear (high-voltage) transport regimes of memristors. At low voltages, the model coincides with the conventional linear formulation based on matrix–vector multiplication (MVM) method. At high voltages, however, this algebraic operation is no longer valid. The model supports two operation modes depending on the requirements of the surrounding circuitry: voltage-controlled current source (VCCS) and voltage-controlled voltage source (VCVS). Current-controlled modes are also feasible for specific applications. Basic guidelines for applying these different modes are provided.
{"title":"Behavioral SPICE model for memristive crosspoint arrays operating in the nonlinear transport regime","authors":"X. Pérez , R. Picos , J. Suñé , E. Miranda","doi":"10.1016/j.sse.2025.109214","DOIUrl":"10.1016/j.sse.2025.109214","url":null,"abstract":"<div><div>In this letter, a fully behavioral SPICE model for <em>M</em> × <em>N</em> memristive crosspoint arrays (CPAs) is presented. The proposed approach incorporates the current–voltage characteristics of the memdiode model for resistive switching devices, which can account for both the linear (low-voltage) and nonlinear (high-voltage) transport regimes of memristors. At low voltages, the model coincides with the conventional linear formulation based on matrix–vector multiplication (MVM) method. At high voltages, however, this algebraic operation is no longer valid. The model supports two operation modes depending on the requirements of the surrounding circuitry: voltage-controlled current source (VCCS) and voltage-controlled voltage source (VCVS). Current-controlled modes are also feasible for specific applications. Basic guidelines for applying these different modes are provided.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109214"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144867289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-08-12DOI: 10.1016/j.sse.2025.109205
G.A. Elbaz , J. Pelloux-Prayer , K. Gruel , P. Torresani , R. Lethiecq , P.L. Julliard , C. Suarez-Segovia , F. Arnaud , E. Nowak , T. Meunier , B.C. Paz
Using known industrial fabrication methods, we repurpose W vias and, with a single contact patterning step, integrate both gates to define the electrochemical potential of quantum dots (QDs) and vias to define their coupling barriers in CMOS-based, linear qubit arrays. We show both simulated and experimental results of individual coupling control of QDs in arrays that were fully fabricated in a foundry on the 28 nm FD-SOI platform. We show detailed wafer-level transfer characteristics for each barrier implemented on a 1x3 linear array, at room temperature and at 2 K, which demonstrate that the vias are well-behaved MOSFET gates with electrostatic control over the Si channel.
{"title":"Integration of W vias for individual coupling control in 28 nm FD-SOI qubit arrays","authors":"G.A. Elbaz , J. Pelloux-Prayer , K. Gruel , P. Torresani , R. Lethiecq , P.L. Julliard , C. Suarez-Segovia , F. Arnaud , E. Nowak , T. Meunier , B.C. Paz","doi":"10.1016/j.sse.2025.109205","DOIUrl":"10.1016/j.sse.2025.109205","url":null,"abstract":"<div><div>Using known industrial fabrication methods, we repurpose W vias and, with a single contact patterning step, integrate both gates to define the electrochemical potential of quantum dots (QDs) and vias to define their coupling barriers in CMOS-based, linear qubit arrays. We show both simulated and experimental results of individual coupling control of QDs in arrays that were fully fabricated in a foundry on the 28 nm FD-SOI platform. We show detailed wafer-level transfer characteristics for each barrier implemented on a 1x3 linear array, at room temperature and at 2 K, which demonstrate that the vias are well-behaved MOSFET gates with electrostatic control over the Si channel.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109205"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144879307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-06-03DOI: 10.1016/j.sse.2025.109160
Lishuang Wu , Huiwen Xu , Jinghong Zhang , Chandong Wang , Zhijun Wu , Huishan Yang
We have developed a highly efficient phosphorescent organic light-emitting device (OLED) utilizing a bipolar host incorporating both donor and acceptor moieties, specifically triphenylamine and phenanthroimidazole. The optimized device demonstrated exceptional performance, achieving a maximum external quantum efficiency of 18.95 % and a luminance of 122,300 cd/m2. These results represent a significant enhancement compared to the reference device, which exhibited a maximum EQE of 9.43 % and a luminance of 25,450 cd/m2. Additionally, the efficiency roll-off was markedly reduced in the device incorporating the bipolar host material. Through various investigative techniques, including time-resolved photoluminescence, transient electroluminescence, and capacitance–voltage measurements, we identified that the fundamental factor for the enhanced efficiency of the optimized device is the reduction of triplet–polaron annihilation, resulting from decreased carrier trapping within the emitting layer. Conversely, the reference device, utilizing a unipolar host, exhibited significant carrier trapping, leading to severe triplet–polaron annihilation and consequently inferior efficiency. These findings demonstrate the critical role of mitigating triplet–polaron annihilation in achieving superior device performance. The results provide valuable insights into the design of advanced organic light-emitting devices and highlight the potential of bipolar hosts in achieving high-performance organic electroluminescent applications.
{"title":"Investigation of performance enhancement in high-efficiency organic light-emitting device based on a bipolar host","authors":"Lishuang Wu , Huiwen Xu , Jinghong Zhang , Chandong Wang , Zhijun Wu , Huishan Yang","doi":"10.1016/j.sse.2025.109160","DOIUrl":"10.1016/j.sse.2025.109160","url":null,"abstract":"<div><div>We have developed a highly efficient phosphorescent organic light-emitting device (OLED) utilizing a bipolar host incorporating both donor and acceptor moieties, specifically triphenylamine and phenanthroimidazole. The optimized device demonstrated exceptional performance, achieving a maximum external quantum efficiency of 18.95 % and a luminance of 122,300 cd/m<sup>2</sup>. These results represent a significant enhancement compared to the reference device, which exhibited a maximum EQE of 9.43 % and a luminance of 25,450 cd/m<sup>2</sup>. Additionally, the efficiency roll-off was markedly reduced in the device incorporating the bipolar host material. Through various investigative techniques, including time-resolved photoluminescence, transient electroluminescence, and capacitance–voltage measurements, we identified that the fundamental factor for the enhanced efficiency of the optimized device is the reduction of triplet–polaron annihilation, resulting from decreased carrier trapping within the emitting layer. Conversely, the reference device, utilizing a unipolar host, exhibited significant carrier trapping, leading to severe triplet–polaron annihilation and consequently inferior efficiency. These findings demonstrate the critical role of mitigating triplet–polaron annihilation in achieving superior device performance. The results provide valuable insights into the design of advanced organic light-emitting devices and highlight the potential of bipolar hosts in achieving high-performance organic electroluminescent applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109160"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144222040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-06-29DOI: 10.1016/j.sse.2025.109187
Wen-Teng. Chang , Liang-I. Cai , Hung-Hsi Chen , Jen-Chien Li , Yao-Jen Lee
In conventional long-channel MOSFETs, the most significant hot carrier degradation at inversion-mode junctions typically occurs when the gate voltage (VGS) is approximately half the drain voltage (VDS). This work investigates the impact of different VGS/VDS ratios (1:2, 1:1, and 2:1) on the electrical stress behavior of Junctionless Gate-All-Around (JLGAA) nMOSFETs. Unlike inversion-mode devices, JLGAA transistors exhibit more pronounced threshold voltage (Vt) shifts under VGS/VDS ratios of 1:1 and 2:1 compared to 1:2, especially over longer stress durations. Interestingly, the 1:2 stress condition reveals a Vt turnaround effect during the early stages of stress. TCAD simulations support these observations, showing that a 2:1 VGS/VDS ratio generates a stronger electric field across the gate oxide compared to other bias conditions.
{"title":"Hot carrier stress in junctionless gate-all-around nMOSFETs under different bias conditions","authors":"Wen-Teng. Chang , Liang-I. Cai , Hung-Hsi Chen , Jen-Chien Li , Yao-Jen Lee","doi":"10.1016/j.sse.2025.109187","DOIUrl":"10.1016/j.sse.2025.109187","url":null,"abstract":"<div><div>In conventional long-channel MOSFETs, the most significant hot carrier degradation at inversion-mode junctions typically occurs when the gate voltage (V<sub>GS</sub>) is approximately half the drain voltage (V<sub>DS</sub>). This work investigates the impact of different V<sub>GS</sub>/V<sub>DS</sub> ratios (1:2, 1:1, and 2:1) on the electrical stress behavior of Junctionless Gate-All-Around (JLGAA) nMOSFETs. Unlike inversion-mode devices, JLGAA transistors exhibit more pronounced threshold voltage (V<sub>t</sub>) shifts under V<sub>GS</sub>/V<sub>DS</sub> ratios of 1:1 and 2:1 compared to 1:2, especially over longer stress durations. Interestingly, the 1:2 stress condition reveals a V<sub>t</sub> turnaround effect during the early stages of stress. TCAD simulations support these observations, showing that a 2:1 V<sub>GS</sub>/V<sub>DS</sub> ratio generates a stronger electric field across the gate oxide compared to other bias conditions.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109187"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144569742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-06-21DOI: 10.1016/j.sse.2025.109183
Qian Bo-Han, Sun Jiu-Xun, Wei Chan, Li Yang, Cui Hai-Juan, Yang Hong-Chun
The fundamental I–V formula of an organic field effect transistor (OFET) is reformulated as double integral of mobility function by using the Poisson’s equation. The reformulated I–V formula overcome the divergence of the integrand in original I–V formula and is convenient not only for further analytic derivations but also for numerical calculations. An analytic binomial expansion for arbitrary power is proposed to analytically derive the OFET model based on Vissenberg-Matters (VM) mobility model being able to consider all terms deduced from the completed VM model. The numerical calculations for six OFET made of four kinds of materials show that the matching degree between theoretical I–V curves and the experimental data is satisfactory for completed model, but evident deviations for ID–VD curves exhibited in usual treatment that only considering first term deduced from the VM model. It is important to consider all terms in modelling OFET to ensure accuracy and reliability for extraction of parameters. These are useful for practical applications and device simulations.
{"title":"Analytic model for organic field-effect transistors based on Vissenberg-Matters mobility model","authors":"Qian Bo-Han, Sun Jiu-Xun, Wei Chan, Li Yang, Cui Hai-Juan, Yang Hong-Chun","doi":"10.1016/j.sse.2025.109183","DOIUrl":"10.1016/j.sse.2025.109183","url":null,"abstract":"<div><div>The fundamental <em>I</em>–<em>V</em> formula of an organic field effect transistor (OFET) is reformulated as double integral of mobility function by using the Poisson’s equation. The reformulated <em>I</em>–<em>V</em> formula overcome the divergence of the integrand in original <em>I</em>–<em>V</em> formula and is convenient not only for further analytic derivations but also for numerical calculations. An analytic binomial expansion for arbitrary power is proposed to analytically derive the OFET model based on Vissenberg-Matters (VM) mobility model being able to consider all terms deduced from the completed VM model. The numerical calculations for six OFET made of four kinds of materials show that the matching degree between theoretical <em>I</em>–<em>V</em> curves and the experimental data is satisfactory for completed model, but evident deviations for <em>I<sub>D</sub></em>–<em>V<sub>D</sub></em> curves exhibited in usual treatment that only considering first term deduced from the VM model. It is important to consider all terms in modelling OFET to ensure accuracy and reliability for extraction of parameters. These are useful for practical applications and device simulations.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109183"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144471777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-07-18DOI: 10.1016/j.sse.2025.109194
Sang-Kon Kim
A small size and tight pitch of contact holes (C/Hs) are crucial for achieving high device density and reducing manufacturing costs. Therefore, the increasing cost and limited resolution of C/Hs in extreme ultraviolet lithography (EUV) make shrinking C/Hs using the resist flow process (RFP) a promising technology. In this study, the Surface Evolver method, finite-element method (FEM), machine learning, and deep learning were applied to RFP to develop a physically accurate RFP model. Deep learning and machine learning proved effective for regression and classification in physical optimization problems. Additionally, self-consistent field theory (SCFT) was used to describe the self-assembly of cylinder-forming block copolymers (BCPs) confined in RFP C/Hs to achieve smaller C/H dimensions. A convolutional neural network (CNN) predicted RFP and BCP outcomes with an error margin of less than 5%, making it suitable for practical applications. This research paves the way for improved RFP shrinkage modeling of random C/Hs and the fabrication of smaller C/Hs.
{"title":"Simulation analysis of resist flow in contact hole shrinkage and its impact on block copolymers","authors":"Sang-Kon Kim","doi":"10.1016/j.sse.2025.109194","DOIUrl":"10.1016/j.sse.2025.109194","url":null,"abstract":"<div><div>A small size and tight pitch of contact holes (C/Hs) are crucial for achieving high device density and reducing manufacturing costs. Therefore, the increasing cost and limited resolution of C/Hs in extreme ultraviolet lithography (EUV) make shrinking C/Hs using the resist flow process (RFP) a promising technology. In this study, the Surface Evolver method, finite-element method (FEM), machine learning, and deep learning were applied to RFP to develop a physically accurate RFP model. Deep learning and machine learning proved effective for regression and classification in physical optimization problems. Additionally, self-consistent field theory (SCFT) was used to describe the self-assembly of cylinder-forming block copolymers (BCPs) confined in RFP C/Hs to achieve smaller C/H dimensions. A convolutional neural network (CNN) predicted RFP and BCP outcomes with an error margin of less than 5%, making it suitable for practical applications. This research paves the way for improved RFP shrinkage modeling of random C/Hs and the fabrication of smaller C/Hs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109194"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144686879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-01Epub Date: 2025-05-28DOI: 10.1016/j.sse.2025.109157
Mohammad Ghanem , Philippe Dollfus , Jerome Saint-Martin
A silicon based nanofilm is examined by using self-consistent electron-phonon transport model. An ensemble Monte Carlo solver for electrons is coupled with a phonon bath that can have a non-uniform temperature. In this simulator, the electron-phonon scattering rates depend on the local temperature and the boundary conditions are also temperature dependent. Using this simulation tool, the thermoelectric properties can be studied, at the microscopic level, in doped semiconductor nanostructures of different sizes and with different types of interfaces. In the present work, the only electronic so-called diffusive Seebeck coefficient of silicon-based nanofilms is investigated as the phonon drag effect is not considered. The influence of the average temperature, temperature gradient, device size, and carrier concentration are investigated.
{"title":"Monte Carlo simulation of thermoelectric properties in silicon nanofilms: diffusive seebeck coefficient analysis","authors":"Mohammad Ghanem , Philippe Dollfus , Jerome Saint-Martin","doi":"10.1016/j.sse.2025.109157","DOIUrl":"10.1016/j.sse.2025.109157","url":null,"abstract":"<div><div>A silicon based nanofilm is examined by using self-consistent electron-phonon transport model. An ensemble Monte Carlo solver for electrons is coupled with a phonon bath that can have a non-uniform temperature. In this simulator, the electron-phonon scattering rates depend on the local temperature and the boundary conditions are also temperature dependent. Using this simulation tool, the thermoelectric properties can be studied, at the microscopic level, in doped semiconductor nanostructures of different sizes and with different types of interfaces. In the present work, the only electronic so-called diffusive Seebeck coefficient of silicon-based nanofilms is investigated as the phonon drag effect is not considered. The influence of the average temperature, temperature gradient, device size, and carrier concentration are investigated.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109157"},"PeriodicalIF":1.4,"publicationDate":"2025-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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