Solid-state Electronics最新文献

This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling.

The fluctuation of the threshold voltage (V_th) presents a challenge while monitoring electrical drift in reliability studies of GaN HEMTs. While technologies, such as ohmic p-GaN, may lessen V_th fluctuations, the issue of recoverable charge trapping still remains. Therefore, it is crucial to adopt novel characterization methods when conducting reliability studies, in order to measure intrinsic changes rather than the charge-trapping effects that exist even in non-degraded transistors. One method expounded in this paper allows for a reliable and replicable measurement of V_th for an ohmic p-GaN gate HEMT GaN. A dedicated gate-bias profile is introduced immediately prior to the threshold-voltage measurement to stabilize it. This preconditioning phase necessitates a negative bias voltage followed by a suitably high voltage to be effective. The novel protocol introduced is also shown to be applicable to other HEMT GaN structures.

The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (L_ov’s) and doping concentrations of the gate-source/drain overlap region (D_ov’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As L_ov and D_ov increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (C_ov,gate-S/D) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs.

The surface electronic states and defects of gallium nitride based high-electron-mobility transistors (HEMTs) play a critical role affecting channel electron density, electron mobility, leakage current, radio frequency (RF) power output and power added efficiency of devices. This article demonstrates the improved surface properties of InAlN/GaN HEMTs through forming gas (FG) annealing, resulting in a significantly improved electrical properties. The X-ray photoelectron spectra reveals a reduction of surface native oxide after FG H₂/N₂ annealing whereby the amount of Ga–O bonds is decreased. Compared with N₂ annealing, an on-resistance of 1.68 Ω·mm, a subthreshold swing of 118 mV/dec, a transconductance peak of 513 mS/mm, a gate diode breakdown voltage of surpassing 42 V, and a high current/power gain cutoff frequency (f_T/f_max) of 165/165 GHz are achieved by the 50-nm InAlN/GaN HEMT on Si substrate.

Quantum bits (qubits) operations in electrically defined Silicon (Si) triple quantum dots (TQDs) are computationally investigated to elevate the potential of TQD structure as a platform for quantum information processing. Employing a realistic Si$/$Si-germanium heterostructure as a target model, device simulations are conducted to secure an initialized qubit state. Basic programmability is verified through implementation of individual qubit operations and 2-qubit entangling operations between neighboring QDs. Constructing a gate sequence composed of 1-qubit and 2-qubit blocks, then, we not only generate three-qubit Greenberger–Horne–Zeilinger state, but also quantify the degradation of state fidelity under the inevitable inaccuracy which are incorporated in the dominant factors of spin-qubit Hamiltonian. Presenting engineering details that are hard to be carried by simulations based on the first principle theory, this work can be served as a practical guideline for designs of scalable quantum processors with electron spin-qubits in Si QD platforms.

The reliability of an Al-doped HfO${}_2$ dielectric used in a high density 2.5D MIMCAP is investigated by constant voltage stress (CVS) and voltage ramp stress (VRS) measurements. The good agreement of the results from the two techniques allows to propose a model for lifetime prediction based on the breakdown characteristics. The extracted activation energy shows a voltage dependence associated with a change in the degradation characteristics of the high-$\kappa$ material at high fields.

Deep learning has shown impressive capabilities in tasks like speech recognition and image classification. However, modern deep neural networks often demand a significant number of weights and extensive computational resources, creating efficiency challenges for applications on edge devices. To address these issues, researchers have introduced deep spiking neural networks (DSNNs) that leverage specialized hardware for synapses and neurons. DSNNs offer a potential solution by improving efficiency in edge-device applications. In this paper, the hardware based DSNN with integrate and fire neuron using steep switching device was investigated. We propose integrate and fire neuron using steep switching device to implement rate coding as input encoding method. Because the steep switching device has double-gate, the threshold voltage of the neuron circuits can be adaptively controlled, which changes the rates of input pulse. Hence, the adjustment of the threshold of neuron can be employed to mitigate the accuracy deterioration resulting from the transformation from deep neural networks (DNNs) to DSNNs. In addition, the off-current of proposed integrate and fire neuron circuit decreases significantly as the steep switching device has steep subthreshold swing. A system simulation of a hardware based DSNN shows that the adjustable threshold of the neuron circuit can achieve a high inference accuracy of 98.36 % which is comparable to that obtained with software based DNN.

Low-dimensional nanomaterials provide promising material platforms for aggressively scaled transistor technologies. We assess the performance potential of transistors based on an array of Tellurium nanowires (TNWs), by parameterizing a machine-learning (ML) tight-binding model with quantum transport device simulations. It has been shown that a transistor based on a parallel array of carbon nanotubes (CNTs) can have excellent on-state performance, but the small bandgap limits the transistor scalability and off-state performance. Our results indicate that compared to the CNT array FETs, the TNW array FETs have significantly suppressed ambipolar transport and improved subthreshold characteristics. The TNW array FET has the potential to achieve a near-ideal subthreshold swing (SS) close to 60 mV/dec, a very large on–off ratio (>10⁹), and low source-drain leakage current at a 10 nm-scale channel length, due to its excellent gate electrostatics with a gate-all-around (GAA) structure, larger band gap and reduced quantum–mechanical tunneling. The TNW array FET also shows excellent scalability with a SS below 100 mV/dec when the channel length is further scaled down to 5 nm. Its larger bandgap and heavier effective mass significantly reduce quantum tunneling. This mechanism contributes to improved subthreshold and lower leakage but also highlights the need to develop low Schottky barrier contacts for TNWs.

Stoichiometric SiN_x layers (x = [N]/[Si] = 1.33) are doped with Si atoms by ultra-low energy ion implantation (ULE-II) and subsequently annealed at different temperatures in inert ambient conditions. Detailed material and memory cells characterization is performed to investigate the effect of Si dopants on the switching properties and performance of the fabricated resistive memory cells. In this context extensive dc current–voltage and impedance spectroscopy measurements are carried out systematically and the role of doping in dielectric properties of the nitride films is enlightened. The dc and ac conduction mechanisms are investigated in a comprehensive way. Room temperature retention characteristics of resistive states are also presented.

Nanostructured Bi₂WO₆ and Bi₂W₂O₉ were synthesized using a hydrothermal method. The crystal structure, morphology, and specific surface area were analyzed via X-ray diffraction, scanning electron microscopy, Brunauer–Emmett–Teller and X-ray photoelectron spectroscopy (XPS) analysis, respectively. The characterization results show that Bi₂WO₆ has a higher specific surface area and a larger pore size than Bi₂W₂O₉, which promote oxygen adsorption and surface reactions. Gas-sensitive tests show that both sensors have a lower detection limit of 2.5 ppm as well as short response and recovery times for detecting triethylamine (TEA). They also have excellent cycling and long-term stability at 180 °C and exhibit excellent gas-sensing performance. The Bi₂WO₆ sensor has a higher response and sensitivity, as well as better selectivity, than the Bi₂W₂O₉ sensor, which is related to the uniformly layered structure of the former material. We have analyzed the mechanism that enables these sensors to detect TEA and have used the Temkin adsorption model to explain the linear relationship. We find that this model provides an excellent theoretical foundation for fitting the working curve of these semiconductor sensors.