Solid-state Electronics最新文献

{"title":"Negative capacitance and negative dielectric behavior of MIS device with Rhenium-Type Schottky contacts","authors":"Mehmet İzzeddin Güler ,&nbsp;Ahmet Kaymaz ,&nbsp;Esra Evcin-Baydilli ,&nbsp;Haziret Durmuş ,&nbsp;Şemsettin Altındal","doi":"10.1016/j.sse.2025.109204","DOIUrl":"10.1016/j.sse.2025.109204","url":null,"abstract":"<div><div>This study offers a thorough examination of the negative capacitance/dielectric behavior of an MIS device with rhenium (Re) type Schottky contact and native oxide interlayer. The pulsed laser deposition method was used to deposit Re as the Schottky contact on the n-type GaAs substrates. Thus, the electrical and dielectric properties were evaluated by <em>I-V, C-V,</em> and <em>G/ω-V</em> tests at<!--> <!-->a high frequency (1 MHz). Experimental results demonstrated that capacitance characteristics showed a marked increase from the inversion region to depletion, with a localized peak observed at 0.26 V. Exceeding 4.16 V, the capacitance values turn negative, signifying a shift to inductive behavior, as shown by a rapid increase in conductance values under the same conditions. In addition, the dynamic resistance profile indicates that the series resistance (<em>R_s</em>) reaches its peak at near-zero bias and stabilizes under significant forward bias, approaching the device’s intrinsic series resistance. Analysis of the <em>C–G/ω–V</em> data also showed two distinct peaks in the corrected conductance (<em>Gc/ω</em>) at –0.55  V and + 0.1  V, due to the response of interface states (<em>N_ss</em>) located at distinct energy levels inside the GaAs bandgap. The transition from capacitive to inductive behavior was recorded with high enough forward bias, at which point the dielectric constant (<em>ε′</em>) turns negative, showing the effects of polarization reversal and reactive energy storage. Additionally, the complex impedance analysis revealed distorted semicircular arcs and loop formations, indicative of interfacial inhomogeneities and multiple charge transport channels. As a result, these findings demonstrate that integrating Re into the MIS structure significantly improves the device’s electrical stability and functional response under varying bias conditions, demonstrating its potential in advanced high-frequency and low-power electronic applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109204"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144831437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Direct extraction of parasitic source and drain resistances in MOSFETs using saturation current ratio","authors":"Ji Won Park ,&nbsp;Seonghyeon Jeong ,&nbsp;Hanbin Lee ,&nbsp;So-Jeong Park ,&nbsp;Jeong Yeon Im ,&nbsp;Dae Hwan Kim ,&nbsp;Yoon Jung Lee ,&nbsp;Dong Myong Kim ,&nbsp;Sung-Jin Choi","doi":"10.1016/j.sse.2025.109209","DOIUrl":"10.1016/j.sse.2025.109209","url":null,"abstract":"<div><div>We propose a saturation current ratio technique (SCRT) for the separate extraction of parasitic source and drain resistances (<em>R_S</em> and <em>R_D</em>) in metal–oxide–semiconductor field-effect transistors (MOSFETs). Unlike conventional methods that require multiple devices or prior knowledge of device parameters, SCRT enables accurate characterization of parasitic resistances using a single device through simple DC measurements. The technique employs a dual configuration by alternating the roles of the source and drain during forward and reverse measurement sweeps. By analyzing the ratio between the drain saturation currents measured in each configuration, SCRT effectively separates <em>R_S</em> and <em>R_D</em> by quantifying their individual contributions to the voltage drop across the source and drain terminals. Experimental validation on both n-channel and p-channel MOSFETs with various channel lengths and widths confirms the robustness, accuracy, and reproducibility of the proposed method. SCRT offers a practical and efficient approach for characterizing asymmetric parasitic resistances in individual devices, making it a reliable alternative to conventional extraction techniques.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109209"},"PeriodicalIF":1.4,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144840762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantitative analysis on z-interference using reprogram scheme in 3D NAND flash memory Vth distribution","authors":"Jooyoung Lee ,&nbsp;Jinil Yoo ,&nbsp;Hyungcheol Shin","doi":"10.1016/j.sse.2025.109198","DOIUrl":"10.1016/j.sse.2025.109198","url":null,"abstract":"<div><div>In this research, we investigated the impact of Reprogram scheme on Z-interference mitigation in the threshold voltage (V_th) distribution of 3D NAND Flash Memory. Statistical Monte-Carlo Simulation was conducted to reproduce the distribution arising from multiple cells, and Incremental Step Pulse Programming (ISPP) was used. During this process, Random Telegraph Noise (RTN) and ISPP noise were applied. The results enabled us to observe the changes in the distribution reflecting reduced z-interference, which were analyzed from various perspectives. It was confirmed that the distribution width, standard deviation of read level intervals, and number of outlier cells are all decreased. Furthermore, we examined the influence of z-interference according to distribution window settings and the application of reprogram scheme.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109198"},"PeriodicalIF":1.4,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144773095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Source/drain metal-dependent oxygen scavenging from the viewpoint of the decoupling between source/drain resistance and threshold voltage in InGaZnO thin-film transistors","authors":"Seungki Kim ,&nbsp;Wonjung Kim ,&nbsp;Seong Hoon Jeon ,&nbsp;Changwook Kim ,&nbsp;Dong Myong Kim ,&nbsp;Sung-Jin Choi ,&nbsp;Yoon Jung Lee ,&nbsp;Dae Hwan Kim","doi":"10.1016/j.sse.2025.109202","DOIUrl":"10.1016/j.sse.2025.109202","url":null,"abstract":"<div><div>Reducing source-drain resistance (R_SD) in oxide semiconductor thin-film transistors (TFTs) mainly impacts the performance and reliability of devices and circuits. Oxygen scavenging (OS) is commonly used during process integration to reduce R_SD, including contact resistance between source-drain (S/D) metal and oxide semiconductors. Meanwhile, the lower R_SD, the better, but the threshold voltage (V_T) should be optimized depending on the application. Therefore, it is essential to decouple R_SD and V_T when applying OS.</div><div>In this study, the OS effect depending on the S/D metal of amorphous InGaZnO (a-IGZO) TFT was investigated from the perspective of decoupling R_SD and V_T. As a result of comparing Cu, Ti, and Al as S/D metals, when Al, which has a high metal–oxygen (M−O) bond strength, was used as the source-drain metal, V_T and R_SD decreased and on-current (I_on) increased compared to when Ti was used. A comprehensive analysis of TFT’s electrical characteristics (V_T, mobility, I_on), X-ray photoelectron spectroscopy (XPS), subgap density of states (DoS), and lateral distribution of thermal equilibrium carrier concentration (n₀(y)) indicates that the occurrence and diffusion of oxygen vacancy (V_O) due to OS in the S/D region cause an increase in subgap DoS and gate-to-S/D overlap length (L_OV) and a decrease in V_T due to an increase in donor concentration in the center of the channel (N_CH) due to a change in n₀(y) profile.</div><div>While R_SD changes before and after post-annealing are ×1.087 (Cu), ×0.606 (Ti), and ×0.283 (Al), N_CH changes are ×0.985 (Cu), ×1.267 (Al), and ×1.183 (Ti). The ΔV_T’s before and after post-annealing are + 0.119 V (Cu), −0.206 V (Al), and − 0.045 V (Ti), while ΔI_on’s are ×0.724 (Cu), ×1.222 (Al), and ×1.193 (Ti). Therefore, it is found that Ti is more advantageous than Al in terms of decoupling R_SD and V_T.</div><div>Our result becomes more critical in employing oxide semiconductor TFTs as the back end of line (BEOL) devices because the phenomenon of V_T being affected in improving R_SD using OS can become more severe in high-temperature processes. Furthermore, our result suggests that when selecting S/D metals and annealing conditions for OS, it is necessary to fully consider not only the R_SD reduction but also the degree to which R_SD and V_T can be decoupled.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109202"},"PeriodicalIF":1.4,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144779380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of operation delay and switching speed limitation due to source/drain resistance and subgap density of states in amorphous InGaZnOx/HfZrOx ferroelectric thin-film transistor","authors":"Sejun Park ,&nbsp;Hyojin Yang ,&nbsp;Haesung Kim ,&nbsp;Hyunwook Jeong ,&nbsp;Sung-Jin Choi ,&nbsp;Dae Hwan Kim ,&nbsp;Dong Myong Kim ,&nbsp;Min-Kyu Park ,&nbsp;Jong-Ho Bae","doi":"10.1016/j.sse.2025.109203","DOIUrl":"10.1016/j.sse.2025.109203","url":null,"abstract":"<div><div>In recent years, ferroelectric memory has garnered significant attention as a next-generation non-volatile memory capable of operating at a low voltage and high speed, making it suitable for embedded memory and in-memory computing applications. Previous research has extensively focused on optimizing the polarization switching speed and operational characteristics of ferroelectric thin films themselves. Recent studies have also demonstrated experimental implementations of memory devices utilizing various semiconductors beyond silicon channels. However, to effectively apply and evaluate ferroelectrics at the transistor level for memory applications, it is crucial to consider not only the intrinsic properties of ferroelectric materials but also to integrate and analyze the performance characteristics of transistors. The size of ferroelectric field effect transistors (FeFET) and the characteristics of semiconductor channel material can significantly influence memory performance and operational speed. Differences in performance may arise depending on the semiconductor channel employed and how defects respond within the materials other than ferroelectric film.</div><div>In this study, ferroelectric thin-film transistors (FeTFTs) and corresponding test element group (TEG) with an amorphous InGaZnO_x (a-IGZO) channel and HfZrO_x (HZO) ferroelectric insulator were fabricated and analyzed to investigate the correlation between operational speed and semiconductor channel properties. Measurements, including DC transfer curves, gate capacitance versus gate voltage (<em>C</em>_GDS–<em>V</em>_G) curves, and the frequency dispersion of <em>C</em>_GDS, were conducted. The results confirmed potential limitations in operational speed due to a-IGZO channel characteristics. TCAD simulations were calibrated considering the extracted subgap density of states (DOS) and contact serial resistance, revealing that the speed of FeTFTs can be constrained by serial resistance and defect responses. These findings underscore the necessity of selecting appropriate device structures and materials for effectively evaluating FeTFTs, and highlight the complexities involved in assessing ferroelectric memory performance, emphasizing the interplay between ferroelectric films and semiconductor channels, interface charges, defect levels influenced by processes, and inherent semiconductor channel performance. This research provides insights into the comprehensive analysis required for evaluating ferroelectric memory devices effectively.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109203"},"PeriodicalIF":1.4,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144809638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Small signal PD SOI MOSFET model: considering impact ionization and self-heating effects","authors":"Narendra Pratap Singh ,&nbsp;Shashank Banchhor ,&nbsp;Ashutosh Yadav ,&nbsp;Ashwaini Goswami ,&nbsp;Avinash Singh ,&nbsp;Rohit Ranjan ,&nbsp;Sudeb Dasgupta ,&nbsp;Anand Bulusu","doi":"10.1016/j.sse.2025.109200","DOIUrl":"10.1016/j.sse.2025.109200","url":null,"abstract":"<div><div>The floating body (FB) effect in Partially Depleted (PD) Silicon-on-Insulator (SOI) devices has the potential to be utilized for enhancing energy efficiency. This is because the floating body potential can be leveraged to modulate the threshold voltage, thereby improving headroom in analog circuit design and thus enabling low-voltage operation. We propose a novel physics-based FB potential model that considers impact ionization (II) and self-heating (SH) effects for low terminal bias (V_DS and V_GS​) operation. Subsequently, the proposed FB potential model is utilized to develop a model for the small-signal parameters (gm and Ro​) of a PD SOI device. This proposed model will be useful for an analog designers to design an energy-efficient analog circuits by considering hitherto unused FB effects in mature PDSOI technology.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109200"},"PeriodicalIF":1.4,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of impact of channel length- and width-directional taper angle in nanosheet and forksheet FETs for 2 nm node and beyond","authors":"Yonghwan Ahn,&nbsp;Junjong Lee,&nbsp;Jinsu Jeong,&nbsp;Seunghwan Lee,&nbsp;Sanguk Lee,&nbsp;Rock-Hyun Baek","doi":"10.1016/j.sse.2025.109199","DOIUrl":"10.1016/j.sse.2025.109199","url":null,"abstract":"<div><div>Herein, an analysis of nanosheet field-effect transistors (NSFETs) and forksheet field-effect transistors (FSFETs) with 3 and 4 channel stacks is performed using fully calibrated technology computer-aided design (TCAD), to study the effect of the taper angle. Variations in the channel length- (A_NS,L) and width-directional (A_NS,W) angles, which inevitably occur during anisotropic etching, significantly affect both DC and AC performance. As A_NS,L decreases, the longer channel decreases subthreshold swing (SS) and increases ballistic mobility, thereby improving the on-state current (I_on). However, at smaller A_NS,L values, the source/drain (S/D) epitaxial volume decreases, reducing the stress on the channel and consequently decreasing I_on. Additionally, the on-state gate capacitance (C_{gg_on}) increases as A_NS,L decreases. In contrast, a smaller A_NS,W increases I_on due to the increased effective channel width (W_eff). Notably, the 4-stack configuration shows a larger I_on than the 3-stack as A_NS,W decreases, attributed to the additional W_eff in the bottom channel of the 4-stack. Similar to A_NS,L, C_{gg_on} increases as A_NS,W decreases. As all-directional taper angle (A_NS,B) decreases, both I_on and C_{gg_on} increase because A_NS,L and A_NS,W simultaneously influence these parameters. Although this effect increases the RC delay in both NSFETs and FSFETs as A_NS,B decreases, FSFETs are more sensitive to RC delay than NSFETs. Furthermore, 4-stack FSFETs exhibit significant degradation in RC delay compared to NSFETs, owing to their high RC delay sensitivity in high-stack configurations. Despite the advantages of FSFETs over NSFETs in terms of RC delay and area reduction, these results indicate that FSFETs are highly sensitive to taper angle variations, particularly in high-stack configurations, potentially negating their RC delay benefits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109199"},"PeriodicalIF":1.4,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144860587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spin-on dopant technology for cost-effective source/drain formation in silicon MOSFETs","authors":"E Kyoung Kim ,&nbsp;Areum Han ,&nbsp;Seok Ki Lee,&nbsp;Byeong Seon Kim,&nbsp;Moon Hee Kang","doi":"10.1016/j.sse.2025.109197","DOIUrl":"10.1016/j.sse.2025.109197","url":null,"abstract":"<div><div>Spin-on dopant (SOD) technology is utilized as a cost-effective approach for forming the source and drain regions of MOSFETs. Desert Silicon P-280, a phosphorus-based dopant with a concentration of 1.9 × 10²² cm⁻³, is used in doping. Following spin-coating at 3000 rpm for 30 s, annealing is performed at temperatures ranging from 800 to 900 °C. As the annealing temperature increases, the sheet resistance significantly decreases from 1260 to 161 Ω/sq. In contrast, the junction depth increases from 0.14 to 0.32  µm on a boron-doped silicon substrate with a resistivity of ∼1 Ω·cm. To assess the electrical performance of the MOSFETs formed using the SOD process, device simulations are performed out using Silvaco technology computer-aided design software and compared with experimental results from MOSFETs fabricated via conventional ion implantation. The results reveal that the SOD-based MOSFET exhibits a threshold voltage (V_th) of ∼−0.30  V, a subthreshold swing (SS) of ∼86 mV/dec, the transconductance (g_m) of ∼0.89 mA/V, along with a comparable on-state currrent. In comparison, conventional ion-implanted MOSFETs show a V_th of −0.25 V, SS of 197.1 mV/dec, and g_m of 0.916 mA/V. These results demonstrate that the SOD technique is a promising alternative for dopant activation and junction formation in MOSFET fabrication, offering process simplicity and cost efficiency, albeit with some trade-offs in subthreshold performance.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109197"},"PeriodicalIF":1.4,"publicationDate":"2025-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144722220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward full relaxation of sSOI substrates for PFET device fabrication","authors":"N-P. Tran,&nbsp;F. Milesi,&nbsp;V-H. Le,&nbsp;L-D. Mohgouk Zouknak,&nbsp;P. Dezest,&nbsp;Ph. Rodriguez,&nbsp;L. Brunet,&nbsp;B. Duriez,&nbsp;M-C. Cyrille,&nbsp;C. Fenouillet-Beranger","doi":"10.1016/j.sse.2025.109196","DOIUrl":"10.1016/j.sse.2025.109196","url":null,"abstract":"<div><div>The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109196"},"PeriodicalIF":1.4,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of channel conduction on capacitance characteristic in the Kelvin AC pseudo-MOS method","authors":"Kyohei Ueda,&nbsp;Shingo Sato","doi":"10.1016/j.sse.2025.109193","DOIUrl":"10.1016/j.sse.2025.109193","url":null,"abstract":"<div><div>In this letter, a newly developed buffer circuit designed for analysis using the Kelvin alternating current (AC) pseudo-metal–oxide–semiconductor (MOS) method is presented. This circuit was used to investigate systematically the influence of channel conduction on capacitance characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109193"},"PeriodicalIF":1.4,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144722221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}