Solid-state Electronics最新文献

A new Double-BOX structure is introduced to explore the electrical properties of the trap-rich layer used to enhance the performance of radio frequency Silicon-on-Insulator substrates. Capacitance-voltage (C-V) measurements reveal anomalous behavior with a “shoulder” emerging in the electron accumulation region and a shift towards negative gate voltage in hysteresis. TCAD simulation shows that these features are related to trap states at the grain boundary in the trap-rich polycrystalline silicon (polysilicon) layer. These traps form a potential barrier and affect the C-V curves. To determine the traps density in polysilicon, a three-element circuit model is used. The effective density of fast traps is evaluated from the corrected C-V curve, while the hysteresis of double-sweep C-V measurement yields the slow traps density at the grain boundary in polysilicon.

This paper discusses the capacitance–voltage (C–V) characteristics of a silicon-on-insulator (SOI) wafer obtained using the alternating current (AC) pseudo-metal–oxide–semiconductor (MOS) method. This study clarified that the C–V characteristics measured using the standard configuration of the AC pseudo-MOS method were strongly ruled by the condition of both the top and back contacts. Using a distinctive setup referred to as the Kelvin AC pseudo-MOS method, coupled with specific treatments applied to the wafer, we acquired C–V and impedance-related characteristics that differed from the standard configuration and aligned with the theoretical expectation for the entire range of measurement frequencies below a few megahertz. In addition, this study demonstrated the qualitative behavior of the frequency-dependent capacitance with the channel conduction of carriers using an analytical model.

Resistive random-access memory (RRAM) is a promising non-volatile memory technology due to its fast operation, low power consumption, and high reliability. However, the negative set phenomenon remains a challenge for RRAM, which can lead to the deterioration of device switching parameters. In this study, we successfully addressed this issue by inserting a NiO blocking layer between the ZrO₂ and Ag top electrodes in ZrO₂-based RRAM. In addition, the resistive switching characteristics of the device are significantly enhanced by the incorporation of a p-type oxide NiO layer. Compared to single-layer ZrO₂ devices, the double-layer Ag/NiO/ZrO₂/ITO RRAM exhibits improved cycling durability (>500 cycles) and good retention time (3 × 10⁴s). Our analysis of the device conduction mechanism and proposed resistive switching model suggest that oxygen vacancies play a connecting role in the reset process, leading to failed reset behavior. Through the incorporation of a p-type semiconductor NiO layer into ZrO₂-based RRAMs, the interference of oxygen vacancies on the reset process can be effectively impeded. This approach not only provides an effective resolution to the unforeseen negative set phenomenon in RRAM devices, but it also holds paramount significance for the advancement of high-performance RRAMs.

A density functional analysis of oxide dipole layers used to set the threshold voltages in high-K/metal CMOS gate stacks is given in terms of the band alignments and chemical trends of these component oxide layers. The oxides SrO, La₂O₃, HfO₂ and Al₂O₃ are found to have similar band gaps and form a ‘staircase’ of band alignments, allowing them to shift the metal electrode Fermi level in both n-type and p-type directions. This analysis supersedes previous largely empirical models based on metal oxide ion densities or electronegativity scales.

The threshold voltage definition and measurement in ultrathin FD-SOI MOS transistors are revisited by comparing theoretical and pragmatic extraction techniques, including novel approaches. The respective merits and limitations of methods based on the monitoring of the potential, mobile charge, gate-to-channel capacitance and drain current are emphasized. Back-gate biasing, thickness-induced quantization, potential fluctuations and surface roughness can enhance the disparity between various extraction methods. The origin of these deviations is clarified.

A new Double-BOX structure is introduced to reveal the electrical properties of undoped polysilicon used to enhance the performance of radio frequency SOI substrates. A plateau is clearly observed in the capacitance–voltage (C-V) characteristics, which is due to the influence of the potential barrier formed at the grain boundary. A tangential approximation method based on a three-element circuit model is proposed for correcting the measured C-V curve. With the corrected C-V curve, the effective trap density distribution in polysilicon is determined for each frequency.

Excessive forward leakage currents in GaN p-i-n diodes were investigated. Traditional diffusion mechanism dominates at V_F > 2 V. The effective band gap is derived to be ∼2.21 eV, which is much lower than 3.4 eV and attributed to a band fluctuation caused by dislocations; At 1.35 V < V_F < 2 V, a trap-assisted tunneling process becomes important, whose ideality factor is still larger than 4.1 at T = 400 K; Two distinct power-law relationships were observed at lower biases, separated at V_F = 0.8 V, whose exponents are extracted to be ∼8 and ∼4, respectively. The behavior is in a good agreement with the space-charge-limited model, featuring an exponentially decaying distribution of trap states below the conduction band.

This work reports the impact of gate oxide thickness on flicker noise (1/f) in 45-nm RFSOI NFET devices. In addition, the effect of finger width scaling on 1/f noise parameters is studied in linear region. The dominant source of 1/f noise is also analyzed. It is observed that thin oxide devices show carrier number fluctuation; however, for thick oxide devices, correlated number-mobility govern the noise. Extracted trap densities using 1/f noise show higher volume trap densities in thin oxide devices. Moreover, trap distribution behavior is analyzed using frequency exponent. Further, GLOBALFOUNDRIES PDK is utilized to model 1/f noise behavior of the devices.

In different environments, high concentration of n-butanol will have certain harm to the human senses and nervous system, meanwhile the electrochemical sensor limits its widespread use due to its high power consumption, so it is very meaningful to develop a semiconductor n-butanol sensor with low energy consumption. In this paper, α-Fe₂O₃ nanorods were prepared by one-step hydrothermal method and then assembled into a n-butanol sensor capable of detecting n-butanol, and the effects of two different calcination temperatures on the performance of the sensor were investigated. Due to its higher Fe³⁺ content, higher oxygen vacancy content and larger specific surface area, S1-250 provided more active sites for gas adsorption, which making the response of S1-250 to 100 ppm n-butanol at 215 °C reached to 88.4. Finally, the effect of the calcination temperature on the sensor and the response mechanism were discussed. This paper offers promising applications for low-energy n-butanol sensors assembled from a single material α −Fe₂O₃.

In this paper, InP Double-Heterojunction Bipolar Transistors (DHBTs) on a 3-inch InP substrate is demonstrated through stepper-based photolithography. The performance of the fabricated InP DHBTs such as DC characteristics, high-frequency characteristics, and uniformity of the 3-inch wafer is investigated to verify the stepper-based fabrication process. To improve the high-frequency characteristics, the self-aligned base-emitter contact is realized by using the high height-to-width ratio and vertical sidewall emitter profile of the Au electroplating process. The fabricated DHBTs with W_E = 0.6 μm and L_E = 15 μm exhibits current gain (β) = 50 at V_CE = 1.0 V and an open-base common-emitter breakdown voltage (BV_CEO) of 5.7 V at J_C = 0.01 mA/µm² and 7.5 V at J_C = 0.1 mA/µm², respectively. Moreover, the fabricated DHBTs with W_E = 0.6 μm and L_E = 15 μm show excellent f_T of 244 GHz and f_max of 221 GHz at J_C = 4.4 mA/μm² and V_CE = 1.6 V. In order to evaluate the uniformity of the fabricated DHBTs, we measure current gain (β) and high-frequency characteristics with W_E = 0.6 μm and L_E = 15 μm and the average values and standard deviation of the β, f_T, and f_max are β = 49.3 ± 1.9, f_T = 241.4 ± 3.8 GHz, and f_max = 221.5 ± 4.0 GHz, respectively. Thanks to the optimized stepper-based fabrication process, the fabricated InP DHBTs exhibit well-balanced high-frequency characteristics and excellent uniformity.