Pub Date : 2025-12-01Epub Date: 2025-08-23DOI: 10.1016/j.sse.2025.109221
Andreas Fuchsberger , Lukas Wind , Aníbal Pacheco-Sanchez , Johannes Aberl , Moritz Brehm , Lilian Vogl , Peter Schweizer , Masiar Sistani , Walter M. Weber
Advancing SOI-based transistors with Ge-rich layers aims to increase device performance in terms of on-state operation and switching speed. Here, we investigate multi-heterojunction SiGe-based Schottky barrier FETs with Ge concentrations up to 75% by means of temperature- dependent electrical characterizations to identify the transport regimes and the effective barrier heights with a thermionic-emission-based model. Importantly, incorporating 33% Ge gives the best compromise for n- and p-type on-state symmetry. As the Ge concentration increases, the p-type on-state current becomes dominant, which is interesting for low-power p-type transistors.
{"title":"A Schottky barrier field-effect transistor platform with variable Ge content on SOI","authors":"Andreas Fuchsberger , Lukas Wind , Aníbal Pacheco-Sanchez , Johannes Aberl , Moritz Brehm , Lilian Vogl , Peter Schweizer , Masiar Sistani , Walter M. Weber","doi":"10.1016/j.sse.2025.109221","DOIUrl":"10.1016/j.sse.2025.109221","url":null,"abstract":"<div><div>Advancing SOI-based transistors with Ge-rich layers aims to increase device performance in terms of on-state operation and switching speed. Here, we investigate multi-heterojunction SiGe-based Schottky barrier FETs with Ge concentrations up to 75% by means of temperature- dependent electrical characterizations to identify the transport regimes and the effective barrier heights with a thermionic-emission-based model. Importantly, incorporating 33% Ge gives the best compromise for n- and p-type on-state symmetry. As the Ge concentration increases, the p-type on-state current becomes dominant, which is interesting for low-power p-type transistors.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109221"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-12DOI: 10.1016/j.sse.2025.109229
Lisa Tondelli , Andries J. Scholten , Thanh Viet Dinh , Luca Selmi
FinFET technology is widely used for advanced digital, RF, and analog applications due to its high performance and scalability. However, the non-planar architecture introduces increased electrical parasitics and self-heating effects (SHEs), which can degrade device reliability and performance.
We analyze, by simulation, the thermal behavior of four FinFET layouts designed with realistic process rules, focusing on transistor channels at the boundary of the large FinFET arrays required by RF applications. The findings highlight key thermal trade-offs of FinFET structures and suggest ways to balance static and dynamic self-heating for optimum performance and limited overtemperature.
{"title":"Layout effects on the thermal metrics of multichannel FinFETs","authors":"Lisa Tondelli , Andries J. Scholten , Thanh Viet Dinh , Luca Selmi","doi":"10.1016/j.sse.2025.109229","DOIUrl":"10.1016/j.sse.2025.109229","url":null,"abstract":"<div><div>FinFET technology is widely used for advanced digital, RF, and analog applications due to its high performance and scalability. However, the non-planar architecture introduces increased electrical parasitics and self-heating effects (SHEs), which can degrade device reliability and performance.</div><div>We analyze, by simulation, the thermal behavior of four FinFET layouts designed with realistic process rules, focusing on transistor channels at the boundary of the large FinFET arrays required by RF applications. The findings highlight key thermal trade-offs of FinFET structures and suggest ways to balance static and dynamic self-heating for optimum performance and limited overtemperature.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109229"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145057261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-30DOI: 10.1016/j.sse.2025.109253
Swapna Sarker, Abhishek Kumar, Avirup Dasgupta
We propose a geometry-dependent compact model for subband energies of stacked Gate-All-Around Field Effect Nanosheet Transistors (GAAFETs). The proposed model captures impact of the corner radius along with the width and thickness of the nanosheet on the subband energies. It is crucial to include corner radius dependence since, for highly scaled GAAFETs, variation in corner radius results in considerable change in the geometrical confinement which affects the terminal characteristics of the device. The proposed compact model has been leveraged to perform detailed variability analysis of the GAAFET. The model has been implemented in the industry standard BSIM-CMG framework and validated with subband energy calculations from TCAD. To the best of our knowledge, this is the first variability-aware compact model for subband energies in GAAFETs that takes into account the effect of corner rounding and its impact on terminal characteristics.
{"title":"Physics-based compact model of subband energy for GAAFETs including corner rounding and geometric variability analysis utilizing Monte Carlo simulation","authors":"Swapna Sarker, Abhishek Kumar, Avirup Dasgupta","doi":"10.1016/j.sse.2025.109253","DOIUrl":"10.1016/j.sse.2025.109253","url":null,"abstract":"<div><div>We propose a geometry-dependent compact model for subband energies of stacked Gate-All-Around Field Effect Nanosheet Transistors (GAAFETs). The proposed model captures impact of the corner radius along with the width and thickness of the nanosheet on the subband energies. It is crucial to include corner radius dependence since, for highly scaled GAAFETs, variation in corner radius results in considerable change in the geometrical confinement which affects the terminal characteristics of the device. The proposed compact model has been leveraged to perform detailed variability analysis of the GAAFET. The model has been implemented in the industry standard BSIM-CMG framework and validated with subband energy calculations from TCAD. To the best of our knowledge, this is the first variability-aware compact model for subband energies in GAAFETs that takes into account the effect of corner rounding and its impact on terminal characteristics.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109253"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145220575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-08-26DOI: 10.1016/j.sse.2025.109210
Josef Gull, Hans Kosina
A novel two-particle Monte Carlo (MC) transport model has been developed and applied to determine the energy distribution function (EDF) in a MOSFET. A dedicated statistical enhancement algorithm enhances the number of samples at higher energies. A comparison with the well-established one-particle MC method and a related enhancement method is presented.
{"title":"Statistical enhancement in two-particle Device Monte Carlo","authors":"Josef Gull, Hans Kosina","doi":"10.1016/j.sse.2025.109210","DOIUrl":"10.1016/j.sse.2025.109210","url":null,"abstract":"<div><div>A novel two-particle Monte Carlo (MC) transport model has been developed and applied to determine the energy distribution function (EDF) in a MOSFET. A dedicated statistical enhancement algorithm enhances the number of samples at higher energies. A comparison with the well-established one-particle MC method and a related enhancement method is presented.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109210"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144902954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-06DOI: 10.1016/j.sse.2025.109230
Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich
In this study, we fabricated high-quality, liquid gate-all-around silicon nanowire (NW) field-effect transistor (FET) biosensors with a gold bowtie antenna using a silicon-on-insulator (SOI) wafer. The electrical and noise properties of these novel NW FETs were investigated under 940 nm light-emitting diode (LED) optical excitation in different solutions. A two-level signal (TLS) that is useful for biosensing was successfully activated at the light excitation only. The detection of repeatable fluctuations in current, manifested as minor peaks in the I–V curves under infrared illumination, confirms the activation of a TLS in the biosensors. The TLS demonstrates a linear dependence of its amplitude in relation to intensity. Moreover, we performed TLS studies in MgCl2 solutions of different concentrations. The results indicate that the FET devices incorporating a gold antenna have considerable potential for the excitation of TLS, thus allowing the sensitivity of the biosensors to be about 300 % enhanced.
{"title":"Silicon nanowire field-effect transistor biosensors with bowtie antenna","authors":"Yongqiang Zhang , Kai Li , Nazarii Boichuk , Denys Pustovyi , Valeriia Chekubasheva , Hanlin Long , Mykhailo Petrychuk , Svetlana Vitusevich","doi":"10.1016/j.sse.2025.109230","DOIUrl":"10.1016/j.sse.2025.109230","url":null,"abstract":"<div><div>In this study, we fabricated high-quality, liquid gate-all-around silicon nanowire (NW) field-effect transistor (FET) biosensors with a gold bowtie antenna using a silicon-on-insulator (SOI) wafer. The electrical and noise properties of these novel NW FETs were investigated under 940 nm light-emitting diode (LED) optical excitation in different solutions. A two-level signal (TLS) that is useful for biosensing was successfully activated at the light excitation only. The detection of repeatable fluctuations in current, manifested as minor peaks in the I–V curves under infrared illumination, confirms the activation of a TLS in the biosensors. The TLS demonstrates a linear dependence of its amplitude in relation to intensity. Moreover, we performed TLS studies in MgCl<sub>2</sub> solutions of different concentrations. The results indicate that the FET devices incorporating a gold antenna have considerable potential for the excitation of TLS, thus allowing the sensitivity of the biosensors to be about 300 % enhanced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109230"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145045991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-16DOI: 10.1016/j.sse.2025.109246
Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee
We investigate the effects of plasma on SiO2 surfaces in various plasma environments, including Ar, O2, and N2, under identical plasma conditions for low-temperature annealing in SiO2/SiO2 wafer bonding. After plasma treatments, no damage is observed on the SiO2 surface, which is comparable to post-CMP SiO2. With the Ar and O2 plasma treatments and XPS analysis, the SiO2 surface shows a Si-OH-rich surface and changes to more hydrophilic properties. Although N2 plasma treatment results in a few isolated voids being observed compared to O2 plasma treatment, N2 plasma treatment will be a suitable choice for Cu/SiO2 hybrid bonding thanks to its highest bonding strength compared to other plasma treatments and the ability to avoid Cu oxidation. On the other hand, O2 plasma treatment on SiO2 surface is the most effective way for SiO2/SiO2 wafer bonding providing excellent hydrophilicity, strong bonding strength, and minimal bonding voids.
{"title":"Comparative effects of plasma treatments on SiO2 surface and bonding performance for wafer and hybrid bonding","authors":"Sung-Min Park , Sang Hyun Jung , Joong-Heon Kim , Seung Heon Shin , Jaejin Lee","doi":"10.1016/j.sse.2025.109246","DOIUrl":"10.1016/j.sse.2025.109246","url":null,"abstract":"<div><div>We investigate the effects of plasma on SiO<sub>2</sub> surfaces in various plasma environments, including Ar, O<sub>2</sub>, and N<sub>2</sub>, under identical plasma conditions for low-temperature annealing in SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding. After plasma treatments, no damage is observed on the SiO<sub>2</sub> surface, which is comparable to post-CMP SiO<sub>2</sub>. With the Ar and O<sub>2</sub> plasma treatments and XPS analysis, the SiO<sub>2</sub> surface shows a Si-OH-rich surface and changes to more hydrophilic properties. Although N<sub>2</sub> plasma treatment results in a few isolated voids being observed compared to O<sub>2</sub> plasma treatment, N<sub>2</sub> plasma treatment will be a suitable choice for Cu/SiO<sub>2</sub> hybrid bonding thanks to its highest bonding strength compared to other plasma treatments and the ability to avoid Cu oxidation. On the other hand, O<sub>2</sub> plasma treatment on SiO<sub>2</sub> surface is the most effective way for SiO<sub>2</sub>/SiO<sub>2</sub> wafer bonding providing excellent hydrophilicity, strong bonding strength, and minimal bonding voids.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109246"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-09-24DOI: 10.1016/j.sse.2025.109254
Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga
The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (Vth), ON current (ION), and OFF current (IOFF) is statistically calculated with varying channel doping, source/drain (S/D) extension region (LEXT), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σVth) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in LEXT, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.
{"title":"Statistical analysis of random dopant fluctuation in Complementary FET","authors":"Sandeep Kumar , Deven H. Patil , Khushi Jain , Ankit Dixit , Naveen Kumar , Vihar Georgiev , S. Dasgupta , Navjeet Bagga","doi":"10.1016/j.sse.2025.109254","DOIUrl":"10.1016/j.sse.2025.109254","url":null,"abstract":"<div><div>The vertical stacking of the confined channels (sheets) in stacked transistors requires a tightly controlled geometrical design, with doping fluctuation as a critical factor that decides the device’s reliability. Therefore, using well-calibrated TCAD models, we thoroughly investigate the impact of random dopant fluctuation (RDF) on Complementary FET (CFET). The standard deviation (σ) of threshold voltage (V<sub>th</sub>), ON current (I<sub>ON</sub>), and OFF current (I<sub>OFF</sub>) is statistically calculated with varying channel doping, source/drain (S/D) extension region (L<sub>EXT</sub>), channel thickness, channel width, and number of sheets. The comprehensive investigation indicates that a threshold fluctuation (σV<sub>th</sub>) of ∼ 2 mV is observed even in an undoped channel, which indicates that RDF is significantly pronounced in L<sub>EXT</sub>, causing reliability concerns. Thus, the proposed analysis is worth exploring for an insight into the scalability of CFET for future sub-2 nm technology nodes.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109254"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-08-23DOI: 10.1016/j.sse.2025.109213
L. Donetti, C. Medina-Bailon, J.L. Padilla, C. Sampedro, F. Gamiz
In this work, we present Mulhacen, a 3D multi-subband simulator developed for the accurate study of nonplanar devices which are at the core of present and future technology nodes. It allows to consider electrons in different conduction band valleys and, among its main features, we can highlight the accurate evaluation of quantum effects in the plane transverse to transport through the solution of the 2D Schrödinger equation in several device cross sections, as well as Monte Carlo description of transport. The simulator is based on a finite elements discretization, which allows an accurate description of realistic device geometries.
{"title":"MULHACEN, enhanced multi-subband Monte Carlo simulator for nonplanar FETs","authors":"L. Donetti, C. Medina-Bailon, J.L. Padilla, C. Sampedro, F. Gamiz","doi":"10.1016/j.sse.2025.109213","DOIUrl":"10.1016/j.sse.2025.109213","url":null,"abstract":"<div><div>In this work, we present <span>Mulhacen</span>, a 3D multi-subband simulator developed for the accurate study of nonplanar devices which are at the core of present and future technology nodes. It allows to consider electrons in different conduction band valleys and, among its main features, we can highlight the accurate evaluation of quantum effects in the plane transverse to transport through the solution of the 2D Schrödinger equation in several device cross sections, as well as Monte Carlo description of transport. The simulator is based on a finite elements discretization, which allows an accurate description of realistic device geometries.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109213"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144895147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01Epub Date: 2025-10-09DOI: 10.1016/j.sse.2025.109258
Geon Kim , Jin So , Eungi Hwang , Jun Lee , Garam Kim
As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.
{"title":"Design and analysis of source-side raised SiGe storage for improved sensing margin in 1T DRAM","authors":"Geon Kim , Jin So , Eungi Hwang , Jun Lee , Garam Kim","doi":"10.1016/j.sse.2025.109258","DOIUrl":"10.1016/j.sse.2025.109258","url":null,"abstract":"<div><div>As semiconductor devices scale aggressively into the nanoscale regime, one-transistor (1T) dynamic random-access memory (DRAM) has gained attention as a highly scalable alternative to conventional capacitor-based DRAM. By storing charge in the transistor’s floating body, 1T DRAM enables a compact cell design without the need for a separate storage capacitor. However, existing silicon-based 1T DRAM structures suffer from limited charge retention and degraded sensing margin, both of which restrict reliable memory operations. This work proposes a novel 1T DRAM structure featuring a SiGe hole storage region strategically raised near the source side. The SiGe region enhances hole confinement in the storage region and reduces diffusion-driven recombination at the source and drain, resulting in improved sensing performance. Technology computer-aided design (TCAD) simulations demonstrate that the proposed structure achieves up to 14 % improvement in sensing margin compared to conventional designs, along with enhanced read current differentiation. These results validate the effectiveness of the proposed approach and its suitability for next-generation, high-density, low-power memory applications.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109258"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145266538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to its excellent electrical performance and compatibility with CMOS processing, polycrystalline silicon TFT has been applied in AMOLED display backplane. As short channel length can potentially benefit current density and cutoff frequency, polycrystalline silicon vertical TFT can be applied in conventional 2-transistor and 1-capcitor (2T1C) pixel unit. The fabrication of polycrystalline silicon vertical TFT was introduced, and the electrical characteristics of the fabricated device was demonstrated. Thereafter, the electrical parameters of the vertical TFT were analyzed and compared under different electrical stress durations, which interprets the inherent mechanism of the stress instability. The total density of states (DOS) and interface DOS of the fabricated devices also indicate that the stress instability is due to charge trapping in gate dielectric layer. The electrical instability is simulated by using high-k gate dielectric layer, and the reduced electrical field in the gate dielectric layer can potentially improve the electrical stability. Finally, 2T1C configuration of AMOLED pixel unit shows the influence of gate dielectric layer on the stress stability, the TFTs with high-k gate dielectric layer shows higher stress stability and lower error rate of OLED current.
{"title":"Interpretation of electrical instability for polycrystalline silicon vertical TFT","authors":"Peng Zhang , Emmanuel Jacques , Régis Rogel , Laurent Pichon , Olivier Bonnaud","doi":"10.1016/j.sse.2025.109263","DOIUrl":"10.1016/j.sse.2025.109263","url":null,"abstract":"<div><div>Due to its excellent electrical performance and compatibility with CMOS processing, polycrystalline silicon TFT has been applied in AMOLED display backplane. As short channel length can potentially benefit current density and cutoff frequency, polycrystalline silicon vertical TFT can be applied in conventional 2-transistor and 1-capcitor (2T1C) pixel unit. The fabrication of polycrystalline silicon vertical TFT was introduced, and the electrical characteristics of the fabricated device was demonstrated. Thereafter, the electrical parameters of the vertical TFT were analyzed and compared under different electrical stress durations, which interprets the inherent mechanism of the stress instability. The total density of states (DOS) and interface DOS of the fabricated devices also indicate that the stress instability is due to charge trapping in gate dielectric layer. The electrical instability is simulated by using high-<em>k</em> gate dielectric layer, and the reduced electrical field in the gate dielectric layer can potentially improve the electrical stability. Finally, 2T1C configuration of AMOLED pixel unit shows the influence of gate dielectric layer on the stress stability, the TFTs with high-<em>k</em> gate dielectric layer shows higher stress stability and lower error rate of OLED current.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"230 ","pages":"Article 109263"},"PeriodicalIF":1.4,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145320062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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