Solid-state Electronics最新文献

In this study, 3D simulations are introduced to analyze electric-dipole spin resonance (EDSR) for a spin qubit defined in a $28\mathrm{nm}$-node Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted Silicon-On-Insulator (FD-SOI) device operated at cryogenic temperatures. The device under consideration is designed to be compatible with STMicroelectronics’ standard fabrication techniques. The simulations predict the experimental and device parameters (e.g. drive amplitude, leakage, and Rabi frequency) required to make EDSR a viable means of qubit control before the device is fabricated. This work highlights how 3D TCAD tools which can simulate quantum-mechanical effects can help steer the design of quantum devices.

A low-resistivity titanium silicide (TiSi₂) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi₂. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi₂ by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi₂. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 10¹⁴ cm⁻². The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs.

The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative average performance of the devices and provided a large effective area for 1/f noise analysis. Results showed an improvement in the saturation drain current when going from room temperature to cryogenic temperatures, with the subthreshold swing saturating around 100 K and the threshold voltage shifting by approximately 150 mV, following similar trends observed in Silicon cryogenic electronics. Additionally, the study confirms that the noise at cryogenic temperatures does not follow the commonly assumed linear scaling with temperature. This deviation from the linear scaling has been associated with the presence of tail states at the interface in bulk and silicon-on-insulator (SOI) devices. These results suggest that the excess 1/f noise in this advanced device architecture is not related to the device architecture but rather to the microscopic material properties of semiconductor/dielectric interfaces.

The reliability of a β-Ga₂O₃ thin-film field-effect transistor is investigated under positive-bias stress (PBS). The transistor has a tri-gate structure with a gate dielectric of Al₂O₃. By characterizing low-frequency noise (LFN), the spatial distribution of trap in the gate dielectric was quantitatively extracted. The measured power spectral density (PSD) followed a 1/f-shape due to trapping and de-trapping of the channel carriers to and from the gate dielectric. Notably, the vertical distribution of the traps perpendicular to the interface of β-Ga₂O₃ and Al₂O₃ was mapped

In this work, models of p-type CuO metal-oxide- semiconductor (MOS) capacitor and thin-film transistors (TFTs) are established using numerical simulation tools and compared with experimental data, to investigate the impact of a passivation layer on the TFT subthreshold behavior. Simulated transfer curves and hole concentrations of back-gated CuO TFT with 10 μm channel length confirm the experimental observation of buried-channel and accumulation-mode conduction mechanisms. The subthreshold behavior is analyzed with HfO2 passivation on the top CuO surface varying the densities of fixed oxide charge and interface states, as well as the thickness of the CuO film. The simulation results demonstrate a significant potential improvement of the subthreshold slope and on/off current ratio, mainly thanks to the optimization of the fixed oxide charge densities.

Time-dependent dielectric breakdown (TDDB) is commonly used to assess dielectric failures. However, TDDB provides limited insights into the physics of dielectric degradation. In this paper, we explore the potential of random telegraph noise (RTN) spectroscopy to study the physics of dielectric breakdown. RTN is a fluctuation in the dielectric leakage current due to capture/emission of injected electrons by dielectric traps. We report an RTN study of large-area alumina (${\text{Al}}_2{\text{O}}_3$) thin films. A stress experiment is performed on a fresh sample, where RTN is measured before, during and after stress. Important degradation signatures are identified in the RTN spectra. The degradation imposed by the applied stress is observed as a consistent transition between two distributions, where the RTN transitions from an initial pre-stress Gaussian, to a final post-stress exponential. A calculation of the noise entropy, which generally increases with growing material disorder, confirms the transition to an exponential distribution. Finally, we relate the RTN distribution parameters to the defectivity of the dielectric.

Chalcogenides Ovonic Threshold Switching (OTS) chalcogenide materials have suitable electronic properties for two-terminal selector application. To reduce the use of toxic elements, there is a need to replace As and Se of the presently-used OTS materials with environmentally friendly OTS materials. In an effort to accelerate the discovery of such materials, we predicted electrical device parameters only from atomistic first-principles simulations and performed a theoretical screening for alternative OTS compositions. With the help of the identified correlations between the theoretical trap/mobility gaps, the local atomic coordination environments and the experimentally-measured threshold, hold voltages or hold, leakage currents and other physics-based material parameter filters like material stability and OTS gauge, we identified more than 35 promising As/Se-free ternary alloy OTS compositions.

The degradation of Ge junctions epitaxially grown within shallow trench isolation (STI) on Si is investigated for geometries with different Area-to-Perimeter (A/P) ratios under constant-voltage stress. We show that the reverse-bias relative current shift ($\Delta I\left(t\right)/I_0$) exhibits a two component behaviour ascribed to the interplay between charge trapping in (pre-existing) traps and generation of new defects mostly along the perimeter of the junctions (Ge/STI interfaces), which affect the trap assisted tunnelling (TAT) leakage current. A semi-empirical model of the degradation kinetics is proposed, allowing to decouple the role of the two individual degradation mechanisms. The insights and the methodology presented are expected to be of relevance for Ge-on-Si active components for Silicon Photonics applications.

We perform trap density (D_t) extraction through admittance measurements on amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin films using multi-finger MOS structures. We investigate the impact of channel length (L_ch) on C-V and G-V characteristics and demonstrate a reliable trap density extraction method in short channel devices. The method is validated for pure and Magnesium-doped a-IGZO (Mg:IGZO). The experimental results are consistent with simulations based on a distributed network model.