Solid-state Electronics最新文献

英文中文

Geometrical variability impact on the gate tunneling leakage mechanisms in FinFETs 几何变异性对栅极隧穿泄漏机制的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-20 DOI: 10.1016/j.sse.2025.109212

C. Medina-Bailon, J.L. Padilla, L. Donetti, C. Navarro, C. Sampedro, F. Gamiz

Given the critical role that quantum tunneling effects play in the behavior of nanoelectronic devices, it is essential to investigate the influence and restraints of these phenomena on the overall transistor performance. In this work, a previously developed gate leakage model, incorporated into an in-house 2D Multi-Subband Ensemble Monte Carlo simulation framework, is employed to analyze the leakage current flowing across the gate insulator. The primary objective is to evaluate how variations in key geometrical parameters (specifically, gate oxide and semiconductor thicknesses dimensions) affect the magnitude and bias dependence of tunneling-induced leakage. Simulations are performed on a representative FinFET structure, and the results reveal that tunneling effects become increasingly pronounced at low gate voltages in devices with thinner oxides and thicker semiconductor thickness. These findings underscore the relevance of incorporating quantum tunneling mechanisms in predictive modeling of advanced transistor architectures.

鉴于量子隧穿效应在纳米电子器件的行为中所起的关键作用，有必要研究这些现象对晶体管整体性能的影响和限制。在这项工作中，将先前开发的栅极泄漏模型整合到内部二维多子带集成蒙特卡罗模拟框架中，用于分析流过栅极绝缘子的泄漏电流。主要目的是评估关键几何参数（特别是栅极氧化物和半导体厚度尺寸）的变化如何影响隧道诱发泄漏的大小和偏置依赖性。在具有代表性的FinFET结构上进行了模拟，结果表明，在低栅极电压下，在更薄的氧化物和更厚的半导体厚度的器件中，隧道效应越来越明显。这些发现强调了在先进晶体管架构的预测建模中结合量子隧道机制的相关性。

引用次数: 0

An All-GaN cascode device with integrated plane-parallel capacitor with high dynamic breakdown voltage and high switching performance 一种具有高动态击穿电压和高开关性能的集成平面并联电容器的全氮化镓级联器件

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-19 DOI: 10.1016/j.sse.2025.109219

Jinyi Wang , Yian Yin , Qiao Sun , Chunxiao Zhao , Qian Zeng , Jiahao Du , Yele Qu , Tiankai Wang , Nan Jiang

All-GaN Cascode devices have been shown to have higher switching speeds than standalone E-mode devices. However, during the switching process of the device, the breakdown voltage drops significantly, this will greatly reduce the reliability of the device, especially in the presence of voltage overshoot. In this paper, an All-GaN Cascode structure with integrated plane-parallel capacitor structure is proposed, and the breakdown voltage in the switching process is referred to as the dynamic breakdown voltage. The test results show that the dynamic breakdown voltage is increased from 497 V to 639 V compared with the conventional structure. In addition, a dual-pulse test circuit is set up to test the switching performance of All-GaN Cascode devices under different conditions, it is proved that the series structure of All-GaN Cascode device can reduce the deterioration of switching performance caused by the increase of capacitance. The above results indicate that All-GaN Cascode devices may have great application potential in high speed and high voltage switching circuits.

全氮化镓Cascode器件已被证明比独立的E-mode器件具有更高的开关速度。但是，在器件的开关过程中，击穿电压显著下降，这将大大降低器件的可靠性，特别是在存在电压超调的情况下。本文提出了一种集成平面并联电容器结构的全氮化镓级联码结构，开关过程中的击穿电压称为动态击穿电压。试验结果表明，与传统结构相比，动态击穿电压由497 V提高到639 V。此外，搭建了双脉冲测试电路，对不同条件下All-GaN Cascode器件的开关性能进行了测试，证明了All-GaN Cascode器件的串联结构可以减少因电容增大而导致的开关性能的恶化。以上结果表明，All-GaN Cascode器件在高速高压开关电路中具有很大的应用潜力。

{"title":"An All-GaN cascode device with integrated plane-parallel capacitor with high dynamic breakdown voltage and high switching performance","authors":"Jinyi Wang , Yian Yin , Qiao Sun , Chunxiao Zhao , Qian Zeng , Jiahao Du , Yele Qu , Tiankai Wang , Nan Jiang","doi":"10.1016/j.sse.2025.109219","DOIUrl":"10.1016/j.sse.2025.109219","url":null,"abstract":"<div><div>All-GaN Cascode devices have been shown to have higher switching speeds than standalone E-mode devices. However, during the switching process of the device, the breakdown voltage drops significantly, this will greatly reduce the reliability of the device, especially in the presence of voltage overshoot. In this paper, an All-GaN Cascode structure with integrated plane-parallel capacitor structure is proposed, and the breakdown voltage in the switching process is referred to as the dynamic breakdown voltage. The test results show that the dynamic breakdown voltage is increased from 497 V to 639 V compared with the conventional structure. In addition, a dual-pulse test circuit is set up to test the switching performance of All-GaN Cascode devices under different conditions, it is proved that the series structure of All-GaN Cascode device can reduce the deterioration of switching performance caused by the increase of capacitance. The above results indicate that All-GaN Cascode devices may have great application potential in high speed and high voltage switching circuits.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"229 ","pages":"Article 109219"},"PeriodicalIF":1.4,"publicationDate":"2025-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144893113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Nanoscale SOI strain engineering: STRASS-enabled local stress optimization 纳米尺度SOI应变工程：strass支持的局部应力优化

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-18 DOI: 10.1016/j.sse.2025.109215

L.D. Mohgouk Zouknak, V-H. Le, N-P. Tran, F. Milesi, J.-M. Hartmann, S. Jarjayes, J. Lespiaux, A. Jannaud, F. Aussenac, N. Bernier, Ph. Rodriguez, L. Brunet, B. Duriez, M.C. Cyrille, C. Fenouillet-Beranger

As device dimensions continue to shrink, improving electrical performance has become a major challenge in realizing the next generation of FDSOI transistors. One of the key strategies to improve electrical performance is to introduce mechanical stress into the transistor channel to increase carrier mobility. We have investigated two strategies for achieving localized strain using the STRASS process. We have also compared the effectiveness of these approaches, focusing on (i) strain relaxation as device dimensions are reduced and (ii) the effect of Si_0.7Ge_0.3 layer thickness on the resulting stress. We have demonstrated uniaxial stresses

σ_{xx}

> 0.8 GPa in active-like structures with W = 130 nm width.

随着器件尺寸的不断缩小，提高电性能已成为实现下一代FDSOI晶体管的主要挑战。提高电性能的关键策略之一是在晶体管通道中引入机械应力以增加载流子迁移率。我们研究了利用STRASS工艺实现局部应变的两种策略。我们还比较了这些方法的有效性，重点关注(i)器件尺寸减小时的应变松弛以及（ii） Si0.7Ge0.3层厚度对产生应力的影响。我们在W = 130 nm宽的类活性结构中发现了单轴应力σxx >； 0.8 GPa。

引用次数: 0

Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement 智能切割™技术中的断裂动力学：晶圆变形测量

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-17 DOI: 10.1016/j.sse.2025.109218

L. Colonel , K. Blanco , S. Tardif , P.E. Acosta Alba , F. Mazen , J. Eymery , D. Landru , F. Rieutord

High-Speed Cameras help in characterizing the splitting step in the Smart Cut™ technology. Full wafer-scale deformation monitoring upon annealing is then possible. This paper describes the setup, equipment and methodology used to estimate the backside wafer deformation and curvature upon fracture propagation in situ during the fracture step. Finally, with such a setup, the fracture process of a SOI-ready structure is studied dynamically over the whole propagation time scale. These results are consistent with literature work performed using punctual measurements methods and will allow in the future to emphasize the effect of process’ and structure’s geometry.

高速摄像机有助于表征Smart Cut™技术的分裂步骤。这样就可以在退火时进行全晶圆尺度的变形监测。本文介绍了在断裂步骤中，用于估算原位裂缝扩展时晶圆背面变形和曲率的设置、设备和方法。最后，在此基础上，在整个扩展时间尺度上动态研究了SOI-ready结构的断裂过程。这些结果与使用准时测量方法进行的文献工作一致，并将允许在未来强调过程和结构几何的影响。

引用次数: 0

Behavioral SPICE model for memristive crosspoint arrays operating in the nonlinear transport regime 非线性输运状态下记忆交点阵列的行为SPICE模型

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-15 DOI: 10.1016/j.sse.2025.109214

X. Pérez , R. Picos , J. Suñé , E. Miranda

In this letter, a fully behavioral SPICE model for M × N memristive crosspoint arrays (CPAs) is presented. The proposed approach incorporates the current–voltage characteristics of the memdiode model for resistive switching devices, which can account for both the linear (low-voltage) and nonlinear (high-voltage) transport regimes of memristors. At low voltages, the model coincides with the conventional linear formulation based on matrix–vector multiplication (MVM) method. At high voltages, however, this algebraic operation is no longer valid. The model supports two operation modes depending on the requirements of the surrounding circuitry: voltage-controlled current source (VCCS) and voltage-controlled voltage source (VCVS). Current-controlled modes are also feasible for specific applications. Basic guidelines for applying these different modes are provided.

本文提出了M × N记忆交点阵列（CPAs）的全行为SPICE模型。该方法结合了电阻开关器件的忆阻二极管模型的电流-电压特性，可以同时考虑忆阻器的线性（低压）和非线性（高压）输运机制。在低电压下，该模型符合基于矩阵向量乘法（MVM）方法的传统线性公式。然而，在高电压下，这种代数运算不再有效。根据周围电路的要求，该型号支持两种工作模式：压控电流源（VCCS）和压控电压源（VCVS）。电流控制模式对于特定应用也是可行的。本文提供了应用这些不同模式的基本准则。

引用次数: 0

Simulation of hole spin qubits in SOI quantum dots: Comparison between different geometries SOI量子点中空穴自旋量子比特的模拟：不同几何形状的比较

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-14 DOI: 10.1016/j.sse.2025.109201

Lorenzo Raschi, Antonio Gnudi

Hole spins in semiconductor quantum dots are a promising path to implement electrically controlled qubits. This work compares different geometries of hole spin qubits implemented in SOI quantum dots with different nanowire orientations. The goal is to optimize geometry and nanowire orientation to maximize the Rabi frequency for a given RF drive amplitude, based on the theory in Venitucci et al. (2018). The hole eigenfunctions are calculated using the

k \cdot p

model within a COMSOL-based framework. The

g

-matrix formalism is exploited to compute Rabi frequency as a function of the magnetic field orientation.

半导体量子点中的空穴自旋是实现电控量子比特的一种很有前途的途径。这项工作比较了不同纳米线方向的SOI量子点中实现的空穴自旋量子比特的不同几何形状。基于Venitucci等人（2018）的理论，目标是优化几何形状和纳米线方向，以在给定RF驱动幅度下最大化Rabi频率。在基于comsol的框架下，利用k⋅p模型计算孔洞特征函数。利用g矩阵的形式来计算拉比频率作为磁场方向的函数。

引用次数: 0

Numerical investigation of effect of Si separator in bottom dielectric isolation forksheet FETs via in-house TCAD process emulator and device simulator 利用TCAD过程仿真器和器件仿真器对底部介质隔离叉片场效应管中硅分离器的影响进行了数值研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-13 DOI: 10.1016/j.sse.2025.109211

In Ki Kim, Sung-Min Hong

In this work, we investigate the effect of a Si separator on the fabrication and performance of a bottom dielectric isolation (BDI) forksheet field-effect transistor (FSFET) using our in-house technology computer-aided design process emulator and device simulator. The process emulator is implemented with a three-dimensional multi-level-set method to emulate the BDI FSFET fabrication under various process conditions. Our results demonstrate that the addition of a Si separator is a plausible option for the BDI FSFET. To verify this conclusion from an electrical performance perspective, we simulate the electrical characteristics of the devices using our in-house device simulator. The device structures generated from the process emulator are directly used for the device simulation. The device simulation results confirm that incorporating a Si separator remains the optimal choice, even when considering the device performance.

在这项工作中，我们研究了硅分离器对底部介电隔离（BDI）叉片场效应晶体管（fset）的制造和性能的影响，使用我们的内部技术计算机辅助设计过程模拟器和器件模拟器。该过程仿真器采用三维多水平集方法实现，模拟了不同工艺条件下BDI fset的制备过程。我们的结果表明，添加硅分离器是BDI fset的合理选择。为了从电气性能的角度验证这一结论，我们使用我们内部的设备模拟器模拟了设备的电气特性。由过程仿真器生成的器件结构直接用于器件仿真。器件仿真结果证实，即使考虑到器件性能，集成硅分离器仍然是最佳选择。

引用次数: 0

Study of RRAM devices with PECVD silicon-oxide resistive switching layer PECVD氧化硅阻性开关层RRAM器件的研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-13 DOI: 10.1016/j.sse.2025.109208

Ivan Lisovyi , Bartłomiej Stonio , Jakub Jasiński , Piotr Wiśniewski

In this work, we study the RRAM devices with PECVD silicon-oxide layer in a Al(Ni)/SiO_x/Cr structure. We perform the electrical characterization, analyze the extracted parameters in HRS and LRS states. Statistical distribution of the extracted parameters were also presented and analyzed. Transport mechanisms for different voltage range and device states were identified. Low-temperature process used to fabricate the presented devices is advantageous due to the possibility of BEOL integration.

本文研究了Al(Ni)/SiOx/Cr结构的PECVD氧化硅层RRAM器件。我们进行了电学表征，分析了在HRS和LRS状态下提取的参数。给出并分析了提取参数的统计分布。确定了不同电压范围和器件状态下的输运机制。由于BEOL集成的可能性，使用低温工艺制造所提出的器件是有利的。

引用次数: 0

Integration of W vias for individual coupling control in 28 nm FD-SOI qubit arrays 集成用于28纳米FD-SOI量子比特阵列单个耦合控制的W通孔

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-12 DOI: 10.1016/j.sse.2025.109205

G.A. Elbaz , J. Pelloux-Prayer , K. Gruel , P. Torresani , R. Lethiecq , P.L. Julliard , C. Suarez-Segovia , F. Arnaud , E. Nowak , T. Meunier , B.C. Paz

Using known industrial fabrication methods, we repurpose W vias and, with a single contact patterning step, integrate both gates to define the electrochemical potential of quantum dots (QDs) and vias to define their coupling barriers in CMOS-based, linear qubit arrays. We show both simulated and experimental results of individual coupling control of QDs in arrays that were fully fabricated in a foundry on the 28 nm FD-SOI platform. We show detailed wafer-level transfer characteristics for each barrier implemented on a 1x3 linear array, at room temperature and at 2 K, which demonstrate that the vias are well-behaved MOSFET gates with electrostatic control over the Si channel.

使用已知的工业制造方法，我们重新利用W过孔，并通过单个接触图图化步骤，集成两个门来定义量子点（QDs）的电化学电位，并在基于cmos的线性量子比特阵列中定义它们的耦合势垒。我们展示了在28纳米FD-SOI平台上在铸造厂完全制造的阵列中量子点的单个耦合控制的模拟和实验结果。我们展示了在室温和2k下，在1x3线性阵列上实现的每个势垒的详细晶圆级转移特性，这表明过孔是性能良好的MOSFET栅极，具有对Si沟道的静电控制。

引用次数: 0

Experimental investigation of 7-level stacked nanosheet nMOSFETs for high-temperature applications 高温应用中7能级堆叠纳米片nmosfet的实验研究

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-08-12 DOI: 10.1016/j.sse.2025.109207

Michelly de Souza , Marcelo A. Pavanello , Mikaël Cassé , Sylvain Barraud

This study experimentally investigates the electrical characteristics of seven-level stacked nanosheet SOI nMOSFETs for high-temperature applications. The experimental findings reveal a significant advantage of this architecture, demonstrating a reduced threshold voltage variation with temperature compared to both two-level stacked nanosheet transistors and state-of-the-art Fully-Depleted SOI MOSFETs. Furthermore, analysis of the normalized transconductance per total width indicates that the enhancement in carrier mobility, typically observed for wider nanosheets relative to narrower ones, tends to saturate for wider devices and to reduce as the operating temperature increases. Also, the normalized transconductance per channel length indicates a reduction of mobility for short-channel devices.

本研究通过实验研究了用于高温应用的七能级堆叠纳米片SOI nmosfet的电学特性。实验结果揭示了该结构的显著优势，与两级堆叠纳米片晶体管和最先进的全耗尽SOI mosfet相比，该结构的阈值电压随温度的变化减小。此外，对每总宽度的归一化跨导的分析表明，载流子迁移率的增强，通常是在较宽的纳米片上观察到的，随着工作温度的升高，载流子迁移率趋于饱和，并且随着工作温度的升高而降低。此外，每个通道长度的标准化跨电导表明了短通道器件的迁移率降低。

引用次数: 0

首页上一页

下一页尾页

类型

全部化学•材料生命科学医学物理工程技术环境•农林材料科学地球科学法学管理学化学环境科学与生态学计算机科学教育学经济学农林科学人文科学生物学数学物理与天体物理心理学综合性期刊其他工业工程理学历史学农学文学信息工程

数据库

全部 ACS Publications Elsevier ieeexplore Springer The Royal Society of Chemistry Wiley

期刊

Solid-state Electronics

全部 Acc. Chem. Res. ACS Applied Bio Materials ACS Appl. Electron. Mater. ACS Appl. Energy Mater. ACS Appl. Mater. Interfaces ACS Appl. Nano Mater. ACS Appl. Polym. Mater. ACS BIOMATER-SCI ENG ACS Catal. ACS Cent. Sci. ACS Chem. Biol. ACS Chemical Health & Safety ACS Chem. Neurosci. ACS Comb. Sci. ACS Earth Space Chem. ACS Energy Lett. ACS Infect. Dis. ACS Macro Lett. ACS Mater. Lett. ACS Med. Chem. Lett. ACS Nano ACS Omega ACS Photonics ACS Sens. ACS Sustainable Chem. Eng. ACS Synth. Biol. Anal. Chem. BIOCHEMISTRY-US Bioconjugate Chem. BIOMACROMOLECULES Chem. Res. Toxicol. Chem. Rev. Chem. Mater. CRYST GROWTH DES ENERG FUEL Environ. Sci. Technol. Environ. Sci. Technol. Lett. Eur. J. Inorg. Chem. IND ENG CHEM RES Inorg. Chem. J. Agric. Food. Chem. J. Chem. Eng. Data J. Chem. Educ. J. Chem. Inf. Model. J. Chem. Theory Comput. J. Med. Chem. J. Nat. Prod. J PROTEOME RES J. Am. Chem. Soc. LANGMUIR MACROMOLECULES Mol. Pharmaceutics Nano Lett. Org. Lett. ORG PROCESS RES DEV ORGANOMETALLICS J. Org. Chem. J. Phys. Chem. J. Phys. Chem. A J. Phys. Chem. B J. Phys. Chem. C J. Phys. Chem. Lett. Analyst Anal. Methods Biomater. Sci. Catal. Sci. Technol. Chem. Commun. Chem. Soc. Rev. CHEM EDUC RES PRACT CRYSTENGCOMM Dalton Trans. Energy Environ. Sci. ENVIRON SCI-NANO ENVIRON SCI-PROC IMP ENVIRON SCI-WAT RES Faraday Discuss. Food Funct. Green Chem. Inorg. Chem. Front. Integr. Biol. J. Anal. At. Spectrom. J. Mater. Chem. A J. Mater. Chem. B J. Mater. Chem. C Lab Chip Mater. Chem. Front. Mater. Horiz. MEDCHEMCOMM Metallomics Mol. Biosyst. Mol. Syst. Des. Eng. Nanoscale Nanoscale Horiz. Nat. Prod. Rep. New J. Chem. Org. Biomol. Chem. Org. Chem. Front. PHOTOCH PHOTOBIO SCI PCCP Polym. Chem.

﹀