Solid-state Electronics最新文献

英文中文

Design and modeling of resonant tunneling transport-controlled voltage-induced double quantum dot channel nanowire field-effect-transistor (DQD-FET) for multi-threshold current levels 多阈值电流水平下共振隧道输运控制电压感应双量子点通道纳米线场效应晶体管（DQD-FET）的设计与建模

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-10-01 DOI: 10.1016/j.sse.2025.109259

N. Paul , S. Chattopadhyay

The article deals with the modeling of gate voltage controlled resonant tunneling transport in a complementary-metal–oxide–semiconductor (CMOS) compatible double quantum dot channel nanowire field-effect-transistor (FET). Appropriate applied voltages at two separate gates, gate-1 and gate-2 of the device form two voltage-tunable quantum dots underneath the gates, within the nanowire channel. The quantum dot eigenstates are tuned by varying the applied gate voltages to enable voltage-modulated resonant tunneling transport. Such transport is modeled by employing a Schrödinger-Poisson self-consistent framework using non-equilibrium Green’s function (NEGF) formalism. Electron–phonon scattering within the nanowire channel is also considered. The transfer characteristics exhibit multiple current thresholds in the range of 10⁻⁴ μA/μm–1 μA/μm due to resonant tunneling. The phonon scattering is observed to significantly depend on nanowire geometry and applied gate voltages, with tunneling dominated quasi-ballistic transport occurring at higher gate voltages. Also, steep sub-threshold slopes of 30 mV/decade–8 mV/decade range and transconductance in the range of 10⁻⁷ μS/μm–1 μS/μm at room temperature are obtained by varying the nanowire diameter in the range of 20 nm–5 nm. Therefore, such device architecture exhibits significant potential for achieving multi-current thresholds in a CMOS compatible architecture at room temperature.

本文研究了互补金属氧化物半导体（CMOS）兼容双量子点通道纳米线场效应晶体管（FET）中栅极电压控制的谐振隧道输运模型。在两个独立的门上施加适当的电压，器件的门1和门2在门的下面形成两个电压可调的量子点，在纳米线通道内。量子点本征态通过改变所施加的栅极电压来调谐，从而实现电压调制的谐振隧道传输。这种传输通过使用非平衡格林函数（NEGF）形式主义的Schrödinger-Poisson自洽框架来建模。同时也考虑了纳米线通道内的电子-声子散射。由于谐振隧道效应的存在，传输特性在10−4 μA/μm - 1 μA/μm范围内表现出多个电流阈值。观察到声子散射显著依赖于纳米线几何形状和施加的栅极电压，在较高的栅极电压下发生隧道主导的准弹道输运。当纳米线直径在20 nm ~ 5 nm范围内变化时，室温下的亚阈值斜率为30 mV/decade ~ 8 mV/decade，跨导范围为10 ~ 7 μS/μm ~ 1 μS/μm。因此，这种器件架构在室温下实现CMOS兼容架构的多电流阈值方面显示出巨大的潜力。

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引用次数: 0

Frequency-driven dielectric analysis of ultrathin HfOx-TiOx composite films 超薄HfOx-TiOx复合薄膜的频率驱动介电分析

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-22 DOI: 10.1016/j.sse.2025.109220

Rezwana Sultana , Karimul Islam , Piotr Jeżak , Robert Mroczyński

This study investigates the frequency-dependent dielectric properties of ultrathin HfO_x-TiO_x composite films (HTO) in a metal–oxide–semiconductor (MOS) configuration over a frequency range of 1 kHz to 3 MHz. The films were deposited using a pulsed-DC magnetron sputtering technique in an atomic layer deposition-like manner, incorporating very thin TiO_x layers within the bulk of HfO_x. Structural analysis revealed that the films are amorphous and exhibit uniform and smooth surfaces. The dielectric constant (ε′) and dielectric loss (ε′′) exhibit a decreasing trend with increasing frequency, demonstrating typical dielectric behavior. Furthermore, the characteristic dielectric relaxation frequency shifts toward lower frequency values with the insertion of TiO_x. The Cole-Cole plot confirms the non-Debye relaxation behavior across all samples. Optical spectroscopy analysis reveals a systematic increase in the optical band gap upon more TiO_x insertion. Analysis of current–voltage (I-V) characteristics demonstrates low leakage currents across the composite films. Understanding the dielectric parameters and the electrical characteristics is crucial for the potential application of these films in advanced electronic applications.

本研究研究了金属氧化物半导体（MOS）结构中超薄HfOx-TiOx复合薄膜（HTO）在1 kHz至3 MHz频率范围内的频率相关介电特性。薄膜是用脉冲直流磁控溅射技术以类似原子层沉积的方式沉积的，在HfOx的主体内结合了非常薄的TiOx层。结构分析表明，薄膜是无定形的，表面均匀光滑。介电常数（ε’）和介电损耗（ε’）随频率的增加呈减小趋势，表现出典型的介电特性。此外，随着TiOx的加入，特征介电弛豫频率向低频值偏移。Cole-Cole图证实了所有样本的非德拜松弛行为。光谱学分析表明，随着TiOx的加入，光学带隙系统地增加。电流-电压（I-V）特性分析表明，复合薄膜的漏电流较低。了解这些薄膜的介电参数和电学特性对于这些薄膜在先进电子应用中的潜在应用至关重要。

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引用次数: 0

Enhancing ultra-thin-barrier AlGaN/GaN HEMTs with LPCVD SiN passivation for high-power applications 利用LPCVD SiN钝化技术增强超薄势垒AlGaN/GaN hemt的高功率应用

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-10-02 DOI: 10.1016/j.sse.2025.109260

Jui-Sheng Wu , Chen-Hsi Tsai , You-Chen Weng , Edward Yi Chang

Ultra-thin-barrier AlGaN/GaN HEMTs offer a gate-recess-free solution but suffer from high on-resistance and current degradation. In this work, ultra-thin-barrier AlGaN/GaN heterostructures with a 1-nm GaN cap and 5-nm Al_0.22Ga_0.78N barrier were fabricated, followed by LPCVD SiN passivation of four different thicknesses (50, 60, 150, and 220 nm) to solve the low carrier density issues associated with thin-barrier structures. The 220 nm LPCVD-SiN passivated device achieves a high I_D,max of 907 mA/mm and the lowest on-resistance of 8.9 Ω·mm. In addition, to evaluate the stability of current output, thinner LPCVD-SiN layers exhibit better current stability under ON-state stress up to 150 °C. These findings highlight the benefits of ultra-thin-barrier AlGaN/GaN HEMTs design for future high-power GaN applications.

超薄势垒AlGaN/GaN hemt提供无栅极凹槽的解决方案，但存在高导通电阻和电流降解的问题。在这项工作中，制备了具有1 nm GaN帽和5 nm Al0.22Ga0.78N势垒的超薄AlGaN/GaN势垒异质结构，然后通过LPCVD SiN钝化四种不同厚度（50,60,150和220 nm）来解决与薄势垒结构相关的低载流子密度问题。220 nm LPCVD-SiN钝化器件具有较高的内径，最大可达907 mA/mm，最低导通电阻为8.9 Ω·mm。此外，为了评估电流输出的稳定性，更薄的LPCVD-SiN层在高达150°C的on状态应力下表现出更好的电流稳定性。这些发现突出了超薄势垒AlGaN/GaN hemt设计对未来高功率GaN应用的好处。

引用次数: 0

Comparison of Self-Heating effect between SOI and SOS MOSFETs SOI和SOS mosfet自热效应比较

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-18 DOI: 10.1016/j.sse.2025.109250

Run-Song Dou , Jia-Min Li , Fan-Yu Liu , Hui-ping Zhu , Bo Li , Jiang-Jiang Li , Bao-Gang Sun , Yang Huang , Jing Wan , Yong Xu , Zheng-sheng Han , Sorin Cristoloveanu

In this research, we perform an in-depth analysis of the self-heating effect (SHE) and heat transfer characteristics of devices fabricated on silicon-on-insulator (SOI) and silicon-on-silicon carbide (SOS) substrates using technology computer-aided design (TCAD) numerical simulations. The results reveal that, under identical operating conditions, the maximum lattice temperature increase in SOI devices is approximately 3.9 times higher than that in SOS devices, highlighting the superior thermal management properties of SOS devices. When SHE is considered at a gate voltage of 1.8 V, the leakage current in SOS devices decreases by about 27 % compared to SOI devices, demonstrating enhanced resistance to SHE in SOS devices. Analysis of the thermal dissipation pathways reveals that for SOI devices, heat primarily dissipates through the source and drain regions within the device layer, while for SOS devices it predominantly dissipates through the silicon carbide substrate due to its high thermal conductivity, thereby significantly improving thermal dissipation efficiency. Additionally, our research uncovers a correlation between increasing device layer thickness and elevated lattice temperature for both SOI and SOS structures. This phenomenon is closely associated with thermal-electric coupling effects and changes in device thermal resistance.

在本研究中，我们使用计算机辅助设计（TCAD）数值模拟技术深入分析了在绝缘体上硅（SOI）和碳化硅上硅（SOS）衬底上制造的器件的自热效应（SHE）和传热特性。结果表明，在相同的操作条件下，SOI器件的最大晶格温度升高约为SOS器件的3.9倍，突出了SOS器件优越的热管理性能。当栅极电压为1.8 V时，与SOI器件相比，SOS器件的泄漏电流减少了约27%，表明SOS器件对SHE的抵抗能力增强。通过对热耗散途径的分析可知，对于SOI器件，热量主要通过器件层内的源极区和漏极区消散，而对于SOS器件，由于其高导热性，热量主要通过碳化硅衬底消散，从而显著提高了散热效率。此外，我们的研究揭示了SOI和SOS结构的器件层厚度增加与晶格温度升高之间的相关性。这一现象与热电耦合效应和器件热阻的变化密切相关。

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引用次数: 0

Boosting the electrical performance of solar cells by using PIN diode structure with different layout styles controlled by MOS capacitor 利用MOS电容控制不同布局风格的PIN二极管结构提高太阳能电池的电性能

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-23 DOI: 10.1016/j.sse.2025.109217

Fernando Pizzo Ribeiro, Egon H.S. Galembeck, Salvador Pinillos Gimenez

In this study, an innovative solar cell (SC) design is proposed and analyzed using the Sentaurus Technology Computer-Aided Design (TCAD) simulator. Departing from conventional rectangular architecture, a half-circular geometry is introduced to improve light absorption and enhance electrical performance. The simulation framework models the solar cell’s behavior under standard test conditions, incorporating realistic material properties and stratified layer structures. Key electrical performance metrics, Fill Factor (FF), and conversion Efficiency are evaluated. The results demonstrate that the half-circular configuration achieves an energy conversion efficiency of 15.33 %, and an FF of 74.2 %. This work lays the groundwork for future experimental validation and encourages the investigation of alternative geometries to improve photovoltaic device performance further.

在本研究中，提出了一种创新的太阳能电池（SC）设计，并使用Sentaurus Technology计算机辅助设计（TCAD）模拟器进行了分析。与传统的矩形建筑不同，引入了半圆几何形状，以改善光吸收并提高电气性能。该仿真框架模拟了太阳能电池在标准测试条件下的行为，结合了真实的材料特性和分层结构。关键电气性能指标，填充系数（FF）和转换效率进行评估。结果表明，半圆结构的能量转换效率为15.33%，FF为74.2%。这项工作为未来的实验验证奠定了基础，并鼓励对替代几何形状的研究，以进一步提高光伏器件的性能。

引用次数: 0

ZnPc-based schottky diodes: Effect of amorphous polymer interlayers on electrical and structural properties zno基肖特基二极管：非晶聚合物中间层对电学和结构性能的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-16 DOI: 10.1016/j.sse.2025.109249

Nargis Khatun , Sumona Sinha , A.K.M. Maidul Islam

This study investigates the influence of Indium Tin Oxide (ITO) electrode surface modification on the electrical properties of zinc phthalocyanine (ZnPc)– based Schottky diodes, using amorphous polymers, specifically polystyrene (Ps) and poly(butyl methacrylate) (PBMA). Devices with configurations of Al (Aluminum)/ZnPc/ITO, Al/ZnPc/Ps/ITO, and Al/ZnPc/PBMA/ITO were fabricated and analysed through current–voltage (I-V) characterisation. Devices modified with polymers showed significantly improved electrical performance, with the rectification ratio rising from 0.81 (pure ZnPc) to 4.24 for ITO modified with PBMA and 6.32 for ITO modified with Ps, along with optimised ideality factors and reduced series resistance. Space-charge-limited conduction (SCLC) became dominant, indicating enhanced charge mobility in the modified devices. UV–Vis analysis further confirmed this improvement, showing that PBMA modification enhances π–π* interactions and molecular aggregation within ZnPc thin films, reducing the optical bandgap from 3.05 eV to 2.75 eV (Ps) and 2.68 eV (PBMA), which indicates modified electronic properties due to polymer incorporation. Structural investigations employing XRR and AFM complement these findings, demonstrating improved crystallite size and a smoother surface, which lead to better charge transport. These results highlight the efficiency of polymer surface modification in enhancing ZnPc-based Schottky diodes, presenting intriguing possibilities for future optoelectronic applications.

本研究研究了铟锡氧化物（ITO）电极表面改性对酞菁锌（ZnPc）基肖特基二极管电性能的影响，采用非晶态聚合物，特别是聚苯乙烯（Ps）和聚甲基丙烯酸丁酯（PBMA）。制备了具有Al (Aluminum)/ZnPc/ITO、Al/ZnPc/Ps/ITO和Al/ZnPc/PBMA/ITO结构的器件，并通过电流-电压（I-V）表征对其进行了分析。用聚合物修饰的器件表现出显著改善的电性能，整流比从0.81（纯ZnPc）上升到PBMA修饰的ITO的4.24和Ps修饰的ITO的6.32，同时优化了理想因子和降低了串联电阻。空间电荷限制传导（SCLC）成为主导，表明改进后的器件中电荷迁移率增强。UV-Vis分析进一步证实了这一改进，表明PBMA修饰增强了ZnPc薄膜内π -π *相互作用和分子聚集，将光学带隙从3.05 eV减小到2.75 eV （Ps）和2.68 eV (PBMA)，这表明聚合物掺入修饰了电子性能。利用XRR和AFM的结构研究补充了这些发现，证明了改进的晶体尺寸和更光滑的表面，导致更好的电荷传输。这些结果突出了聚合物表面改性在增强znpc基肖特基二极管方面的效率，为未来光电应用提供了有趣的可能性。

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引用次数: 0

Trap-rich high-resistivity silicon for improved on-chip monolithic transformers characteristics 用于改善片上单片变压器特性的富阱高电阻硅

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-10-08 DOI: 10.1016/j.sse.2025.109261

Najeh Zeidi , Farès Tounsi , Jean-Pierre Raskin , Denis Flandre

This paper investigates the performance of monolithic on-chip planar transformers implemented on high-resistivity substrates incorporating a trap-rich layer (HR-Si + TR), using both experimental measurements and electromagnetic simulations. Two transformer topologies, i.e., interleaved and concentric, were fabricated, measured, and simulated on both standard silicon (Std-Si) and HR-Si + TR to assess the impact of substrate losses. Key figures of merit, including self-resonant frequency (SRF), mutual inductance, reactive and resistive coupling factors, and maximum power-transfer efficiency, were extracted and compared. Results show that the HR-Si + TR substrate markedly enhances both topologies: for the interleaved transformer, the SRF increases by 3.8 % from 3.66 to 3.80 GHz, while the peak power-transfer efficiency nearly doubles from 0.33 at 1.42 GHz to 0.63 at 2.26 GHz; for the concentric transformer, the SRF rises by over 31 % from 3.12 to 4.10 GHz, and the efficiency increases more than threefold from 0.06 at 1.48 GHz to 0.22 at 2.15 GHz. These improvements arise from the HR-Si + TR substrate’s ability to substantially reduce the resistive mutual coupling factor by minimizing eddy current losses in the substrate and raising the impedance of the RC leakage path to ground, thereby limiting trace crosstalk and power leakage between traces. The benefits are particularly pronounced in the concentric topology, where the larger winding separation amplifies the impact of reduced substrate-induced losses.

本文利用实验测量和电磁模拟，研究了采用富阱层（HR-Si + TR）的高电阻率衬底实现的单片片上平面变压器的性能。在标准硅（Std-Si）和HR-Si + TR上制作、测量和模拟了两种变压器拓扑，即交错和同心拓扑，以评估衬底损耗的影响。提取并比较了自谐振频率（SRF）、互感系数、无功耦合系数和电阻耦合系数以及最大功率传输效率等关键性能指标。结果表明，HR-Si + TR衬底显著增强了这两种拓扑结构：对于交错变压器，SRF从3.66 GHz提高到3.80 GHz提高了3.8%，峰值功率传输效率从1.42 GHz的0.33提高到2.26 GHz的0.63，几乎翻了一番；对于同心变压器，SRF从3.12 GHz提高到4.10 GHz，提高了31%以上，效率从1.48 GHz时的0.06提高到2.15 GHz时的0.22，提高了三倍多。这些改进源于HR-Si + TR衬底能够通过最小化衬底中的涡流损耗和提高RC漏径对地的阻抗，从而大大降低电阻互耦系数，从而限制了走线串扰和走线之间的功率泄漏。这种优势在同心拓扑结构中尤为明显，较大的绕组间距放大了基材损耗降低的影响。

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引用次数: 0

CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit 一晶体管一电容电路中双层铁电隧道结的CMOS后端集成

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-09-23 DOI: 10.1016/j.sse.2025.109255

Keerthana Shajil Nair , Muhammad Hamid Raza , Catherine Dubourdieu , Veeresh Deshpande

Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf_0.5Zr_0.5O₂ (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric-dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm² at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.

基于铁电f0.5 zr0.5 o2 （HZO）的铁电隧道结（FTJ）器件作为用于神经形态计算应用的CMOS后端可积低功耗非易失性存储器，最近引起了人们的极大兴趣。在本文中，我们展示了金属-铁电-介电-金属双层FTJ器件在180nm CMOS技术芯片后端的集成。我们介绍了集成的FTJ器件的电气特性，包括在开/关电流比为~ 18时的极化开关和电阻开关行为，以及在读取电压为1.8 V时的导通电流密度为~ 24.5 μA/cm2。此外，我们还演示了一个1-晶体管-1-电容器（1T1C）电路，通过将后端FTJ器件与前端nMOS晶体管连接，将FTJ器件的ON电流放大2.6倍。因此，我们展示了用于神经形态应用的基于hzo的FTJ器件集成的基本构建块。

引用次数: 0

On the role of power dissipation in the Post-BD behavior of FDSOI NanoWire FETs 功率损耗对FDSOI纳米线场效应管后bd行为的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-29 DOI: 10.1016/j.sse.2025.109228

R. Goyal, A. Crespo-Yepes, M. Porti, R. Rodriguez, M. Nafria

Dielectric Breakdown, which has been associated with the progressive wear-out of the gate dielectric, has been one of the most detrimental failure mechanisms in CMOS devices. With downscaling, new device architectures and/or materials have been introduced, so, it is necessary to evaluate the BD impact at device (and circuit) level in these new structures. In this work, the dielectric BD and the post-BD behavior in largely scaled FDSOI nanowire transistors with high-k gate dielectric have been characterized, using the energy and the power dissipated by the device under test as key parameters. The experimental results evidence the presence of new detrimental effects for the device’s integrity beyond the traditional dielectric BD.

电介质击穿与栅极电介质的逐渐损耗有关，是CMOS器件中最有害的失效机制之一。随着规模的缩小，新的器件架构和/或材料已经被引入，因此，有必要在这些新结构中评估器件（和电路）级别的BD影响。在这项工作中，以被测器件的能量和功耗为关键参数，对具有高k栅极介电介质的FDSOI纳米线晶体管的介电BD和后BD行为进行了表征。实验结果表明，除了传统的介质BD外，还存在新的对器件完整性的不利影响。

引用次数: 0

Impact of back-biasing on the series resistance in ultrathin SOI devices 背偏对超薄SOI器件串联电阻的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics

Pub Date : 2025-12-01 Epub Date: 2025-08-30 DOI: 10.1016/j.sse.2025.109225

Yu Yan , Cunhua Dou , Xuan Zhang , Weijia Song , Zhiyu Tang , Binhong Li , Jing Wan , Huabin Sun , Xing Zhao , Yun Wang , Yong Xu , Sorin Cristoloveanu

The universal burden of series resistance in short-channel MOSFETs is even more critical in ultrathin transistors where the sheet resistance of source and drain terminals is high. However, FD-SOI devices benefit from the back-gate action which can also modulate the series resistance. Several methods for series resistance extraction are examined. Unlike an advanced FD-SOI MOSFET with highly-doped raised terminals, the junctionless transistors (with either conventional or core–shell architecture) exhibit higher series resistance, strongly dependent on back-gate voltage.

短沟道mosfet中串联电阻的普遍负担在超薄晶体管中更为严重，因为超薄晶体管的源极和漏极的片电阻很高。然而，FD-SOI器件受益于后门作用，它也可以调制串联电阻。介绍了几种串联电阻提取方法。与具有高掺杂凸起端子的先进FD-SOI MOSFET不同，无结晶体管（具有传统或核壳结构）具有更高的串联电阻，强烈依赖于反向电压。

引用次数: 0

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