Pub Date : 2024-03-26DOI: 10.1016/j.sse.2024.108907
Kunhui Xu , Xiaoli Tian , Wei Wei , Xinhua Wang , Yun Bai , Chengyue Yang , Yidan Tang , Chengzhan Li , Xinyu Liu , Hong Chen
In this article, the mechanism analysis of the impact of the LJFET on the conduction characteristic of SiC IGBT is verified through simulation results and actual tests. Planar p-channel SiC IGBTs with different LJFET including 3.2 μm, 10 μm, and 12 μm are fabricated and tested for trend verification, and test results are fit with simulation. Under the same conditions, when the LJFET increases from 3 μm to 10 μm, the conduction characteristic is relatively improved. Moreover, the forward voltage drop degenerates when the LJFET increases from 10 μm to 12 μm. When the gate voltage is −20 V, the forward voltage drop of the p-channel SiC IGBT at the current density of 100 A/cm2 is −10.20 V. At the same time, the breakdown voltage reaches 10 kV.
本文通过仿真结果和实际测试验证了 LJFET 对 SiC IGBT 传导特性影响的机理分析。为了验证趋势,我们制作并测试了具有不同 LJFET(包括 3.2 μm、10 μm 和 12 μm)的平面 p 沟道 SiC IGBT,测试结果与仿真结果相吻合。在相同条件下,当 LJFET 从 3 μm 增加到 10 μm 时,传导特性相对得到改善。此外,当 LJFET 从 10 μm 增大到 12 μm 时,正向压降变小。当栅极电压为 -20 V 时,电流密度为 100 A/cm2 的 p 沟道 SiC IGBT 的正向压降为 -10.20 V。
{"title":"Impact of JFET width on conduction characteristic for p-channel SiC IGBT","authors":"Kunhui Xu , Xiaoli Tian , Wei Wei , Xinhua Wang , Yun Bai , Chengyue Yang , Yidan Tang , Chengzhan Li , Xinyu Liu , Hong Chen","doi":"10.1016/j.sse.2024.108907","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108907","url":null,"abstract":"<div><p>In this article, the mechanism analysis of the impact of the <em>L</em><sub>JFET</sub> on the conduction characteristic of SiC IGBT is verified through simulation results and actual tests. Planar p-channel SiC IGBTs with different <em>L</em><sub>JFET</sub> including 3.2 μm, 10 μm, and 12 μm are fabricated and tested for trend verification, and test results are fit with simulation. Under the same conditions, when the <em>L</em><sub>JFET</sub> increases from 3 μm to 10 μm, the conduction characteristic is relatively improved. Moreover, the forward voltage drop degenerates when the <em>L</em><sub>JFET</sub> increases from 10 μm to 12 μm. When the gate voltage is −20 V, the forward voltage drop of the p-channel SiC IGBT at the current density of 100 A/cm<sup>2</sup> is −10.20 V. At the same time, the breakdown voltage reaches 10 kV.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"216 ","pages":"Article 108907"},"PeriodicalIF":1.7,"publicationDate":"2024-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140321465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-26DOI: 10.1016/j.sse.2024.108906
Z. Li, K. Yao, M. Ashtar, Y. Yang, D. Cao
Ferroelectric materials have great promise for use in photodetectors due to their built-in electric field-assisted carrier separation and switchable polarization properties. Carrier separation efficiency is a decisive factor in evaluating photodetector performance. The photodetector optoelectronic performance can be enhanced further by optimizing the thickness of the ferroelectric film to take full advantage of the switchable polarization properties of the ferroelectric material, and by enhancing the built-in electric field to drive carrier separation. In this work, we optimize the performance of PbZr0.52Ti0.48O3 (PZT) photodetectors by modulating the thickness of the film. It is observed that thicker ferroelectric films have lower coercivity fields, which are more favorable for ferroelectric domain switching. On this basis, the ferroelectric properties of ferroelectric PZT films were optimized by thickness tuning, and the photodetection performance of PZT-based self-powered photodetectors was explored. It is found that the polarization enhances the internal electric field, driving photogenerated carrier separation and improving the self-powered current, while also selectively enhancing photodetectivity for devices of different thicknesses. Additionally, both film thickness and ferroelectric polarization significantly impact the response time.
{"title":"Tailoring the optoelectronic properties of PZT through the modulation of the thin film","authors":"Z. Li, K. Yao, M. Ashtar, Y. Yang, D. Cao","doi":"10.1016/j.sse.2024.108906","DOIUrl":"10.1016/j.sse.2024.108906","url":null,"abstract":"<div><p>Ferroelectric materials have great promise for use in photodetectors due to their built-in electric field-assisted carrier separation and switchable polarization properties. Carrier separation efficiency is a decisive factor in evaluating photodetector performance. The photodetector optoelectronic performance can be enhanced further by optimizing the thickness of the ferroelectric film to take full advantage of the switchable polarization properties of the ferroelectric material, and by enhancing the built-in electric field to drive carrier separation. In this work, we optimize the performance of PbZr<sub>0.52</sub>Ti<sub>0.48</sub>O<sub>3</sub> (PZT) photodetectors by modulating the thickness of the film. It is observed that thicker ferroelectric films have lower coercivity fields, which are more favorable for ferroelectric domain switching. On this basis, the ferroelectric properties of ferroelectric PZT films were optimized by thickness tuning, and the photodetection performance of PZT-based self-powered photodetectors was explored. It is found that the polarization enhances the internal electric field, driving photogenerated carrier separation and improving the self-powered current, while also selectively enhancing photodetectivity for devices of different thicknesses. Additionally, both film thickness and ferroelectric polarization significantly impact the response time.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108906"},"PeriodicalIF":1.7,"publicationDate":"2024-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140403008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A global I-V and C-V BSIM-CMG parameter extraction methodology based on deep learning is proposed. 100 k training datasets were generated through Monte Carlo simulation varying 28 IV and CV model parameters in the industry-standard BSIM-CMG FinFET model. For each of the 100 k Monte Carlo-selected BSIM-CMG parameter dataset, the ID-VG and CGG-VG characteristics of seven Monte Carlo-selected gate lengths ranging from 14 nm to 110 nm were generated as the input to train the parameter extraction neural network. The neural network outputs for training are the 28 model parameters’ values. The neural network's capability to extract BSIM-CMG model parameters that accurately fit TCAD-generated ID-VG and CGG-VG data over a range of gate lengths was demonstrated. This marks the first time a deep learning compact model parameter extraction flow, employing a single neural network for both I-V and C-V parameters and for a range of gate length, is presented.
{"title":"A single neural network global I-V and C-V parameter extractor for BSIM-CMG compact model","authors":"Jen-Hao Chen , Fredo Chavez , Chien-Ting Tung , Sourabh Khandelwal , Chenming Hu","doi":"10.1016/j.sse.2024.108898","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108898","url":null,"abstract":"<div><p>A global I-V and C-V BSIM-CMG parameter extraction methodology based on deep learning is proposed. 100 k training datasets were generated through Monte Carlo simulation varying 28 IV and CV model parameters in the industry-standard BSIM-CMG FinFET model. For each of the 100 k Monte Carlo-selected BSIM-CMG parameter dataset, the I<sub>D</sub>-V<sub>G</sub> and C<sub>GG</sub>-V<sub>G</sub> characteristics of seven Monte Carlo-selected gate lengths ranging from 14 nm to 110 nm were generated as the input to train the parameter extraction neural network. The neural network outputs for training are the 28 model parameters’ values. The neural network's capability to extract BSIM-CMG model parameters that accurately fit TCAD-generated I<sub>D</sub>-V<sub>G</sub> and C<sub>GG</sub>-V<sub>G</sub> data over a range of gate lengths was demonstrated. This marks the first time a deep learning compact model parameter extraction flow, employing a single neural network for both I-V and C-V parameters and for a range of gate length, is presented.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"216 ","pages":"Article 108898"},"PeriodicalIF":1.7,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140188281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-11DOI: 10.1016/j.sse.2024.108897
N. Zerhouni Abdou , S. Reboh , L. Brunet , M. Alepidis , P. Acosta Alba , S. Cristoloveanu , I. Ionica
The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes.
无结 EZ-FET 是一种类似 FDSOI 的简单器件,只需要两个光刻层和标准加工步骤。该器件采用简化的结构和制造流程,使用未掺杂的源极和漏极,可对绝缘体上的半导体薄膜(SOI)和栅堆进行快速电气评估。本文介绍了一个能再现无结 EZ-FET 特殊传输特性的电气模型。然后对模型进行了简化,从而开发出一种实用的参数提取方法。该方法经过实验验证,可提供 SOI 薄膜电子和空穴的电特性(迁移率、阈值电压)。
{"title":"Methodology for parameters extraction with undoped junctionless EZ-FETs","authors":"N. Zerhouni Abdou , S. Reboh , L. Brunet , M. Alepidis , P. Acosta Alba , S. Cristoloveanu , I. Ionica","doi":"10.1016/j.sse.2024.108897","DOIUrl":"10.1016/j.sse.2024.108897","url":null,"abstract":"<div><p>The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"217 ","pages":"Article 108897"},"PeriodicalIF":1.7,"publicationDate":"2024-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140282136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The CMOS compatibility of Negative Capacitance (NC) FETs has been enhanced tremendously after introducing a thin film-doped HfO2 as a ferroelectric (FE) layer. For a given FE layer, the NC property is governed by specific HfO2 dopants (e.g., La, Zr, Al, Sr, Gd, Y, and Si). Thus, the TCAD simulation considerably depends on the dopant-specific Landau parameters (), and its solidity needs proper attention. Further, the reliability of the NC devices is severely affected by process variations, i.e., interface trap charges, work function variation, random dopant fluctuation, and ambient temperature (external), which modulates the device threshold voltage (Vth); in turn, the device aging. In this paper, using well-calibrated TCAD models, we investigated reliability for the different dopant-specific NC-FinFET, in terms of Vth, ON current (ION), and OFF current (IOFF) modulation induced by: (i) the interface trap variability (ITV) considering the different trap concentration and energy location; (ii) the work function variability (WFV) considering different metal grain sizes (Gr); (iii) the random dopant fluctuations (RDF); and (iv) the ambient temperature. In this way, the device aging is calculated by inspecting Vth shift by . These investigations pave the path for realizing a reliable NC-FinFET design.
{"title":"Unveiling the reliability of negative capacitance FinFET with confrontation of different HfO2-ferroelectric dopants","authors":"Rajeewa Kumar Jaisawal , Sunil Rathore , P.N. Kondekar , Navjeet Bagga","doi":"10.1016/j.sse.2024.108896","DOIUrl":"10.1016/j.sse.2024.108896","url":null,"abstract":"<div><p>The CMOS compatibility of Negative Capacitance (NC) FETs has been enhanced tremendously after introducing a thin film-doped HfO<sub>2</sub> as a ferroelectric (FE) layer. For a given FE layer, the NC property is governed by specific HfO<sub>2</sub> dopants (e.g., La, Zr, Al, Sr, Gd, Y, and Si). Thus, the TCAD simulation considerably depends on the dopant-specific Landau parameters (<span><math><mrow><msub><mi>α</mi><mi>x</mi></msub><mo>,</mo><msub><mi>β</mi><mi>x</mi></msub><mo>,</mo><msub><mi>γ</mi><mi>x</mi></msub><mo>,</mo><msub><mi>ρ</mi><mi>x</mi></msub><mo>,</mo><msub><mi>g</mi><mi>x</mi></msub></mrow></math></span>), and its solidity needs proper attention. Further, the <em>reliability</em> of the NC devices is severely affected by process variations, i.e., interface trap charges, work function variation, random dopant fluctuation, and ambient temperature (external), which modulates the device threshold voltage (V<sub>th</sub>); in turn, the device aging. In this paper, using well-calibrated TCAD models, we investigated reliability for the different dopant-specific NC-FinFET, in terms of V<sub>th</sub>, ON current (I<sub>ON</sub>), and OFF current (I<sub>OFF</sub>) modulation induced by: (<em>i</em>) the interface trap variability (ITV) considering the different trap concentration and energy location; (<em>ii</em>) the work function variability (WFV) considering different metal grain sizes (G<sub>r</sub>); (<em>iii</em>) the random dopant fluctuations (RDF); and (iv) the ambient temperature. In this way, the device aging is calculated by inspecting V<sub>th</sub> shift by <span><math><mrow><mo>±</mo><mn>50</mn><mi>m</mi><mi>V</mi></mrow></math></span>. These investigations pave the path for realizing a reliable NC-FinFET design.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108896"},"PeriodicalIF":1.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140089329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1016/j.sse.2024.108895
E. Salvador, R. Rodriguez, E. Miranda
In this letter, a method for dealing with the time-dependent dielectric breakdown (TDDB) of oxide layers in MOS and MIM structures in the framework of SPICE simulations is reported. In particular, we focus the attention on the clustering model (Burr’s XII distribution) for dielectric breakdown which can be considered an extension of the well known Weibull model. The oxide time-to-breakdown for both models is calculated using the inversion method for the cumulative distribution function. For the sake of completeness, the proposed approach includes uncorrelated variability both in the initial and final resistance states. For illustrative purposes, it is also shown how voltage acceleration, progressive breakdown or any other correlation factor can be introduced in the simulation parameters. As an application example, the proposed method is used to simulate the simplest case of a gate-to-drain dielectric breakdown of a NMOS-based inverter circuit.
在这封信中,我们报告了一种在 SPICE 仿真框架内处理 MOS 和 MIM 结构中氧化层随时间变化的介质击穿 (TDDB) 的方法。我们特别关注介质击穿的聚类模型(Burr's XII 分布),该模型可视为众所周知的 Weibull 模型的扩展。这两种模型的氧化物击穿时间都是通过累积分布函数的反演方法计算得出的。为完整起见,建议的方法包括初始和最终电阻状态的非相关变异性。为了说明问题,还展示了如何在模拟参数中引入电压加速、逐步击穿或任何其他相关因素。作为一个应用实例,所提出的方法用于模拟基于 NMOS 的逆变器电路的栅极到漏极电介质击穿的最简单情况。
{"title":"SPICE simulation of the time-dependent clustering model for dielectric breakdown","authors":"E. Salvador, R. Rodriguez, E. Miranda","doi":"10.1016/j.sse.2024.108895","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108895","url":null,"abstract":"<div><p>In this letter, a method for dealing with the time-dependent dielectric breakdown (TDDB) of oxide layers in MOS and MIM structures in the framework of SPICE simulations is reported. In particular, we focus the attention on the clustering model (Burr’s XII distribution) for dielectric breakdown which can be considered an extension of the well known Weibull model. The oxide time-to-breakdown for both models is calculated using the inversion method for the cumulative distribution function. For the sake of completeness, the proposed approach includes uncorrelated variability both in the initial and final resistance states. For illustrative purposes, it is also shown how voltage acceleration, progressive breakdown or any other correlation factor can be introduced in the simulation parameters. As an application example, the proposed method is used to simulate the simplest case of a gate-to-drain dielectric breakdown of a NMOS-based inverter circuit.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108895"},"PeriodicalIF":1.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140103315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-28DOI: 10.1016/j.sse.2024.108884
Do-Kywn Kim , Dong-Seok Kim , Tae-Eon Kim , Min-Ju Kim , Seung Heon Shin
This paper investigates the impact of gamma-ray (γ-ray) radiation at doses of 100 krads and 1,000 krads on amorphous indium-zinc-oxide (IZO) thin-film transistors (TFTs). The IZO channel's properties are analyzed using X-ray photoelectron spectroscopy (XPS) before and after radiation. Following 100 krads exposure, the oxygen vacancy (VO) peak in the IZO channel increases from 41.8 % to 59.4 % due to the generation of electron-hole pairs. Additionally, the threshold voltage of the IZO TFT negatively shifts from 10.1 V to 5.5 V due to positive charges in the gate oxide layer. Following exposure to 1,000 krads gamma-ray radiation, the threshold voltage of 8.8 V is similar to that of 9.8 V for the non-irradiated TFT. Remarkably, the subthreshold swing (SS) remains unchanged, while the maximum transconductance (gm,max) is improved by 10.0 % and effective mobility (µFE) by 6.1 %. These enhancements result from the diffusion of indium, zinc, and oxygen into the gate oxide layer thanks to the self-heating effect at a dose of 1,000 krads. Based on the results, our findings indicate the IZO TFT shows a significant potential for a radiation-hardness electronic device in harsh environments.
{"title":"Investigation of low to high-dose gamma-ray (γ-ray) radiation effects on indium-zinc-oxide (IZO) thin film transistor (TFT)","authors":"Do-Kywn Kim , Dong-Seok Kim , Tae-Eon Kim , Min-Ju Kim , Seung Heon Shin","doi":"10.1016/j.sse.2024.108884","DOIUrl":"10.1016/j.sse.2024.108884","url":null,"abstract":"<div><p>This paper investigates the impact of gamma-ray (γ-ray) radiation at doses of 100 krads and 1,000 krads on amorphous indium-zinc-oxide (IZO) thin-film transistors (TFTs). The IZO channel's properties are analyzed using X-ray photoelectron spectroscopy (XPS) before and after radiation. Following 100 krads exposure, the oxygen vacancy (V<sub>O</sub>) peak in the IZO channel increases from 41.8 % to 59.4 % due to the generation of electron-hole pairs. Additionally, the threshold voltage of the IZO TFT negatively shifts from 10.1 V to 5.5 V due to positive charges in the gate oxide layer. Following exposure to 1,000 krads gamma-ray radiation, the threshold voltage of 8.8 V is similar to that of 9.8 V for the non-irradiated TFT. Remarkably, the subthreshold swing (SS) remains unchanged, while the maximum transconductance (g<sub>m,max</sub>) is improved by 10.0 % and effective mobility (µ<sub>FE</sub>) by 6.1 %. These enhancements result from the diffusion of indium, zinc, and oxygen into the gate oxide layer thanks to the self-heating effect at a dose of 1,000 krads. Based on the results, our findings indicate the IZO TFT shows a significant potential for a radiation-hardness electronic device in harsh environments.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108884"},"PeriodicalIF":1.7,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140009120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-28DOI: 10.1016/j.sse.2024.108893
Yuyun Chen , Guodong Xu , Yunpeng Yu , Yi Shen
Bias stress stabilities of the polymethyl methacrylate (PMMA)-passivated IGZO thin-film transistors (TFTs) after being exposed in a normal and harsh (100 °C steam) environment were studied, in order to comprehensively evaluate protection effects of PMMA. In a normal environment, the PMMA-passivated TFTs exhibited normal switching characteristics and electrical stabilities. However, the switching characteristics and bias stress stabilities were changed after being exposed on 100 °C steam. There were negative Vth shifts on the transfer curves of the steam-exposed IGZO TFTs. Our XPS analysis revealed that the negative ΔVth was related to the steam-induced H2O molecules throughout the IGZO films, which acted as electron donors to introduce more electrons in the front channel. Under PBS, the steam-exposed IGZO TFTs showed an abnormal negative Vth shift while the un-exposed IGZO TFTs showed negligible Vth shift. This abnormality was ascribed to the electrons released from steam-induced H2O molecules, which render the conductive path more easily opened. Under NBS, the steam-exposed IGZO TFT presented larger negative Vth shift than the un-exposed TFT. This result was interpreted in terms of the steam-induced donor states (H2O molecules) near or at channel/insulator interface. Under PBTS and NBTS, the changes in Vth for steam-exposed TFTs were similar to those for un-exposed TFTs. Such a similarity indicates that steam exposure had no effects on NBTS and PBTS stabilities. It was understood in terms that the steam-induced H2O+ recombined with the electrons released from the steam-induced H2O molecules under bias stress, forming H2O to compensate the thermally-induced H2O adsorption. Our results suggest that one-micron-thick PMMA passivation layer enabled to protect IGZO TFTs from H2O in a normal environment, but it provided inadequate protection in a harsh environment. Therefore, a thicker PMMA passivation layer should be considered.
为了全面评估聚甲基丙烯酸甲酯(PMMA)的保护作用,研究了暴露在正常和恶劣(100 °C蒸汽)环境中的聚甲基丙烯酸甲酯(PMMA)钝化 IGZO 薄膜晶体管(TFT)的偏压稳定性。在正常环境下,经过 PMMA 钝化处理的 TFT 具有正常的开关特性和电气稳定性。然而,暴露在 100 °C 蒸汽中后,开关特性和偏压应力稳定性发生了变化。暴露在蒸汽中的 IGZO TFT 的转移曲线出现了负 V 移位。我们的 XPS 分析表明,负 ΔV 与整个 IGZO 薄膜中蒸汽诱导的 HO 分子有关,这些分子作为电子供体在前沟道中引入了更多电子。在 PBS 条件下,蒸汽暴露的 IGZO TFT 显示出异常的负 V 偏移,而未暴露的 IGZO TFT 的 V 偏移可以忽略不计。这种异常是由于蒸汽诱导的 HO 分子释放出电子,使导电路径更容易打开。在 NBS 条件下,蒸汽暴露的 IGZO TFT 比未暴露的 TFT 显示出更大的负 V 偏移。这一结果可以从沟道/绝缘体界面附近或界面上的蒸汽诱导供体态(HO 分子)来解释。在 PBTS 和 NBTS 条件下,蒸汽暴露 TFT 的 V 值变化与未暴露 TFT 相似。这种相似性表明,蒸汽暴露对 NBTS 和 PBTS 的稳定性没有影响。据理解,蒸汽诱导的 HO 与蒸汽诱导的 HO 分子在偏压应力下释放的电子重新结合,形成 HO 以补偿热诱导的 HO 吸附。我们的研究结果表明,在正常环境下,一微米厚的 PMMA 钝化层能够保护 IGZO TFT 免受 HO 的影响,但在恶劣环境下,其保护作用就显得不足了。因此,应考虑使用更厚的 PMMA 钝化层。
{"title":"Bias stress stabilities of PMMA-passivated indium-gallium-zinc-oxide thin-film transistors after 100 °C steam exposure","authors":"Yuyun Chen , Guodong Xu , Yunpeng Yu , Yi Shen","doi":"10.1016/j.sse.2024.108893","DOIUrl":"10.1016/j.sse.2024.108893","url":null,"abstract":"<div><p>Bias stress stabilities of the polymethyl methacrylate (PMMA)-passivated IGZO thin-film transistors (TFTs) after being exposed in a normal and harsh (100 °C steam) environment were studied, in order to comprehensively evaluate protection effects of PMMA. In a normal environment, the PMMA-passivated TFTs exhibited normal switching characteristics and electrical stabilities. However, the switching characteristics and bias stress stabilities were changed after being exposed on 100 °C steam. There were negative V<sub>th</sub> shifts on the transfer curves of the steam-exposed IGZO TFTs. Our XPS analysis revealed that the negative ΔV<sub>th</sub> was related to the steam-induced H<sub>2</sub>O molecules throughout the IGZO films, which acted as electron donors to introduce more electrons in the front channel. Under PBS, the steam-exposed IGZO TFTs showed an abnormal negative V<sub>th</sub> shift while the un-exposed IGZO TFTs showed negligible V<sub>th</sub> shift. This abnormality was ascribed to the electrons released from steam-induced H<sub>2</sub>O molecules, which render the conductive path more easily opened. Under NBS, the steam-exposed IGZO TFT presented larger negative V<sub>th</sub> shift than the un-exposed TFT. This result was interpreted in terms of the steam-induced donor states (H<sub>2</sub>O molecules) near or at channel/insulator interface. Under PBTS and NBTS, the changes in V<sub>th</sub> for steam-exposed TFTs were similar to those for un-exposed TFTs. Such a similarity indicates that steam exposure had no effects on NBTS and PBTS stabilities. It was understood in terms that the steam-induced H<sub>2</sub>O<sup>+</sup> recombined with the electrons released from the steam-induced H<sub>2</sub>O molecules under bias stress, forming H<sub>2</sub>O to compensate the thermally-induced H<sub>2</sub>O adsorption. Our results suggest that one-micron-thick PMMA passivation layer enabled to protect IGZO TFTs from H<sub>2</sub>O in a normal environment, but it provided inadequate protection in a harsh environment. Therefore, a thicker PMMA passivation layer should be considered.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108893"},"PeriodicalIF":1.7,"publicationDate":"2024-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140018081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diffusive memristors made with conductive metal bridge random access memories (RAMs) have been studied for low power consumption and linearity of integrate/fire characteristics of artificial neurons by using a defective graphene interlayer. Utilizing this approach, a volatile artificial neuron incorporating Ag demonstrates sustained low-power characteristics inherent to Ag-based devices, accompanied by linearity in spike occurrence through precise control of on/off-current ratio and conductive filament dissolution time. This approach enables the precise tuning of the neuron's behavior and offers potential applications in neuromorphic computing and artificial intelligence.
{"title":"Improvement of power consumption and linearity of integrate/fire characteristics using diffusive memristors with defective graphene for artificial neuron application","authors":"Moonkyu Song, Sangheon Lee, S.S. Teja Nibhanupudi, Siyu Wu, Sanjay K. Banerjee","doi":"10.1016/j.sse.2024.108892","DOIUrl":"https://doi.org/10.1016/j.sse.2024.108892","url":null,"abstract":"<div><p>Diffusive memristors made with conductive metal bridge random access memories (RAMs) have been studied for low power consumption and linearity of integrate/fire characteristics of artificial neurons by using a defective graphene interlayer. Utilizing this approach, a volatile artificial neuron incorporating Ag demonstrates sustained low-power characteristics inherent to Ag-based devices, accompanied by linearity in spike occurrence through precise control of on/off-current ratio and conductive filament dissolution time. This approach enables the precise tuning of the neuron's behavior and offers potential applications in neuromorphic computing and artificial intelligence.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108892"},"PeriodicalIF":1.7,"publicationDate":"2024-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139975866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-24DOI: 10.1016/j.sse.2024.108894
Shu-Yi Tsai , Kuan-Zong Fung
In this study, the deposition of Li7La3Zr2O12 (LLZO) thin films onto MgO substrates was successfully achieved using the radio frequency magnetron sputtering technique. The deposition process was carried out at various substrate temperatures to investigate their influence on the film properties The as-deposited films were initially amorphous; however, they could be crystallized into the cubic phase by increasing the deposition temperature above 100 °C. Upon raising the deposition temperature to 200 °C, the peaks in the X-ray diffraction pattern became sharper and more intense, indicating an increase in the volume fraction and crystallite size of LLZO. At 200 °C, the film consisted predominantly of the conductive crystalline LLZO phase, resulting in a remarkably high ionic conductivity of about 10−4 S cm−1. The film deposited at 300 °C exhibited the second phase, i.e., the La2Zr2O7 phase, which resulted from excessive lithium losses. These findings highlight the importance of controlling the deposition temperature to achieve the desired crystalline phase and optimize the electrical properties of LLZO thin films.
{"title":"Fabrication of garnet solid electrolytes via sputtering for solid-state batteries","authors":"Shu-Yi Tsai , Kuan-Zong Fung","doi":"10.1016/j.sse.2024.108894","DOIUrl":"10.1016/j.sse.2024.108894","url":null,"abstract":"<div><p>In this study, the deposition of Li<sub>7</sub>La<sub>3</sub>Zr<sub>2</sub>O<sub>12</sub> (LLZO) thin films onto MgO substrates was successfully achieved using the radio frequency magnetron sputtering technique. The deposition process was carried out at various substrate temperatures to investigate their influence on the film properties The as-deposited films were initially amorphous; however, they could be crystallized into the cubic phase by increasing the deposition temperature above 100 °C. Upon raising the deposition temperature to 200 °C, the peaks in the X-ray diffraction pattern became sharper and more intense, indicating an increase in the volume fraction and crystallite size of LLZO.<!--> <!-->At 200 °C, the film consisted predominantly of the conductive crystalline LLZO phase, resulting in a remarkably high ionic conductivity of about 10<sup>−4</sup> <!-->S cm<sup>−1</sup>. The film deposited at 300 °C exhibited the second phase, i.e., the La<sub>2</sub>Zr<sub>2</sub>O<sub>7</sub> phase, which resulted from excessive lithium losses. These findings highlight the importance of controlling the deposition temperature to achieve the desired crystalline phase and optimize the electrical properties of LLZO thin films.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"215 ","pages":"Article 108894"},"PeriodicalIF":1.7,"publicationDate":"2024-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140018077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}