Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270894
I. Sylla
In this paper, a new RF/Microwave source is presented. This source is able to generate a Continuous Waveform (CW) signal as well as a modulated signal like GFSK for Bluetooth and GMSK for GSM. The RF source presented here is based on a direct modulation All-Digital Phase-Locked-Loop (ADPLL) architecture that was originally designed for a Bluetooth transmitter in the 2.4GHz in industry, science, and medicine (ISM) band. By doing some mod$cations, we were able to extend the frequency range of the source. The ADPLL requires a controlled signal from a Digital Signal Processor (DSP). The TMS32OC5402 DSP was chosen for this experiment.
{"title":"Building an rf source for low cost testers using an adpll controlled by texas instruments digital signal processor (DSP) TMS32OC5402","authors":"I. Sylla","doi":"10.1109/TEST.2003.1270894","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270894","url":null,"abstract":"In this paper, a new RF/Microwave source is presented. This source is able to generate a Continuous Waveform (CW) signal as well as a modulated signal like GFSK for Bluetooth and GMSK for GSM. The RF source presented here is based on a direct modulation All-Digital Phase-Locked-Loop (ADPLL) architecture that was originally designed for a Bluetooth transmitter in the 2.4GHz in industry, science, and medicine (ISM) band. By doing some mod$cations, we were able to extend the frequency range of the source. The ADPLL requires a controlled signal from a Digital Signal Processor (DSP). The TMS32OC5402 DSP was chosen for this experiment.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125868363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271108
Fei Su, S. Ozev, K. Chakrabarty
Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in safety-critical biomedical applications, dependability emerges as a critical performance parameter. In this paper, we present a costeffective concurrent test methodology for droplet-based microelectrofluidic systems. We present a classification of catastrophic and parametric faults in such systems and show how faults can be detected by electrostatically controlling and tracking droplet motion. We then present tolerance analysis based on Monte-Carlo simulations to characterize the impact of parameter variations on system performance. To the best of our knowledge, this constitutes the first attempt to define a fault model and to develop a test methodology for droplet-based microelectrofluidic systems.
{"title":"Testing of droplet-based microelectrofluidic systems","authors":"Fei Su, S. Ozev, K. Chakrabarty","doi":"10.1109/TEST.2003.1271108","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271108","url":null,"abstract":"Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in safety-critical biomedical applications, dependability emerges as a critical performance parameter. In this paper, we present a costeffective concurrent test methodology for droplet-based microelectrofluidic systems. We present a classification of catastrophic and parametric faults in such systems and show how faults can be detected by electrostatically controlling and tracking droplet motion. We then present tolerance analysis based on Monte-Carlo simulations to characterize the impact of parameter variations on system performance. To the best of our knowledge, this constitutes the first attempt to define a fault model and to develop a test methodology for droplet-based microelectrofluidic systems.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"109 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130239640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270890
S. Vandivier, M. Wahl, J. Rearick
This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST/spl I.bar/PULSE tests were applied to functional channels as well as channels with a set of externally-induced hard defects. All valid signals were correctly received, and all defects were detected, thus validating both 1149.6's anticipated backwards compatibility with 1149.1 and fault coverage. Mission-mode tests showed no performance degradation due to the test circuits. Characterization across PVT of the test receiver suggests 1149.6's robustness with respect to noise.
{"title":"First ic validation of IEEE Std. 1149.6","authors":"S. Vandivier, M. Wahl, J. Rearick","doi":"10.1109/TEST.2003.1270890","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270890","url":null,"abstract":"This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST/spl I.bar/PULSE tests were applied to functional channels as well as channels with a set of externally-induced hard defects. All valid signals were correctly received, and all defects were detected, thus validating both 1149.6's anticipated backwards compatibility with 1149.1 and fault coverage. Mission-mode tests showed no performance degradation due to the test circuits. Characterization across PVT of the test receiver suggests 1149.6's robustness with respect to noise.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271123
P. Ehlig
Peter Ehlig Texas Instruments, Inc. Stafford, Texas (pehlig@ti.com) I am often introduced as an expert in how integrated circuits work. This is not all tha; accurate. My field of expertise is in how integrated circuits fail and more specifically how they fail in end systems. I find this perspective biases my positions in a different direction from many experts in the fields of silicon test or silicon qualification. also cause issues. These noise events may come from localized current starvation or bus switching. The potential for noise events in the final system is nearly impossible to accurately model in a device design or production test environment. These events, coupled with subtle defects that did not fail the device production test, may later cause end system failures.
{"title":"How (In)adequate is one-time testing","authors":"P. Ehlig","doi":"10.1109/TEST.2003.1271123","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271123","url":null,"abstract":"Peter Ehlig Texas Instruments, Inc. Stafford, Texas (pehlig@ti.com) I am often introduced as an expert in how integrated circuits work. This is not all tha; accurate. My field of expertise is in how integrated circuits fail and more specifically how they fail in end systems. I find this perspective biases my positions in a different direction from many experts in the fields of silicon test or silicon qualification. also cause issues. These noise events may come from localized current starvation or bus switching. The potential for noise events in the final system is nearly impossible to accurately model in a device design or production test environment. These events, coupled with subtle defects that did not fail the device production test, may later cause end system failures.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128780787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271112
David M. Wu, Mike Lin, S. Mitra, Kee-sup Kim, A. Sabbavarapu, T. Jaber, Peter A. Johnson, Dale March, Greg Parrish
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to industrial designs demonstrate significant savings in test cost in terms of test data volume and test application time without compromising test quality. Implementation of the HDFT architecture on Intel ASIC and microprocessor designs are described.
{"title":"II-DFT: a hybrid dft architecture for low-cost high quality structural testing","authors":"David M. Wu, Mike Lin, S. Mitra, Kee-sup Kim, A. Sabbavarapu, T. Jaber, Peter A. Johnson, Dale March, Greg Parrish","doi":"10.1109/TEST.2003.1271112","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271112","url":null,"abstract":"This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to industrial designs demonstrate significant savings in test cost in terms of test data volume and test application time without compromising test quality. Implementation of the HDFT architecture on Intel ASIC and microprocessor designs are described.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129142495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270867
Yu-Shen Yang, Jiang Brandon Liu, P. J. Thadikaran, A. Veneris
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires the extraction of a gate-level (logic) model from the transistor level representation of the circuit under test. Logic extraction is an error prone process due to extraction tool limitations and due to the human interference. Errors introduced by extraction require manual debugging, a resource intensive and time consuming task. This paper presents a set of extraction errors typical in an industrial environment. It also proposes an automated solution to extraction error diagnosis und correction. Experiments on circuits with similar architecture to that of high speed custom-made industrial blocks are conducted to confirm the fitness of the approach.
{"title":"Extraction error diagnosis and correction in high-performance designs","authors":"Yu-Shen Yang, Jiang Brandon Liu, P. J. Thadikaran, A. Veneris","doi":"10.1109/TEST.2003.1270867","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270867","url":null,"abstract":"Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires the extraction of a gate-level (logic) model from the transistor level representation of the circuit under test. Logic extraction is an error prone process due to extraction tool limitations and due to the human interference. Errors introduced by extraction require manual debugging, a resource intensive and time consuming task. This paper presents a set of extraction errors typical in an industrial environment. It also proposes an automated solution to extraction error diagnosis und correction. Experiments on circuits with similar architecture to that of high speed custom-made industrial blocks are conducted to confirm the fitness of the approach.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129783307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271155
Cliff Ma
{"title":"Dfm - an industry paradigm shift","authors":"Cliff Ma","doi":"10.1109/TEST.2003.1271155","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271155","url":null,"abstract":"","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124442427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270891
I. Duzevik
This paper describes the implementation of 1149.6 to an existing commercial high-speed interface device. The first section explains the circuit design decisions made during the definition phase. The insertion of the test circuitry was carefully implemented to co-exist with the mission mode circuitry. The second section describes the effect of the test circuit on the high-speed mission performance of the device and the trade-offs that those effects imposed. After the implementation phase, the test circuit was simulated, verified, manufactured in silicon and tested. The third part of the paper report the findings after the verification and simulation of the functional performance of the IEEE 1149.6 device. An important consideration for the verification process is to determine the fault coverage of AC-coupled line tests. The specific behavior of the test circuit during detection of various faults directly governs the design of the IEEE 1149.6 TAP (test access port) controller. The end presents a summary and discussion of the results. In addition to the performance of the 1149.6 implementation, a brief comparison between the features and characteristics of the IEEE 1149.4 (mixed signal test bus) and IEEE 1149.6 standard are presented.
{"title":"Design and implementation of IEEE 1149.6","authors":"I. Duzevik","doi":"10.1109/TEST.2003.1270891","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270891","url":null,"abstract":"This paper describes the implementation of 1149.6 to an existing commercial high-speed interface device. The first section explains the circuit design decisions made during the definition phase. The insertion of the test circuitry was carefully implemented to co-exist with the mission mode circuitry. The second section describes the effect of the test circuit on the high-speed mission performance of the device and the trade-offs that those effects imposed. After the implementation phase, the test circuit was simulated, verified, manufactured in silicon and tested. The third part of the paper report the findings after the verification and simulation of the functional performance of the IEEE 1149.6 device. An important consideration for the verification process is to determine the fault coverage of AC-coupled line tests. The specific behavior of the test circuit during detection of various faults directly governs the design of the IEEE 1149.6 TAP (test access port) controller. The end presents a summary and discussion of the results. In addition to the performance of the 1149.6 implementation, a brief comparison between the features and characteristics of the IEEE 1149.4 (mixed signal test bus) and IEEE 1149.6 standard are presented.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124493518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271191
E. Starkloff, T. Fountain, G. Black
This paper is a technology review of PXI. It describes the basic PXI architecture and looks in more detail at the features of the slot 2 timing and triggering module.
本文是PXI的技术综述。它描述了基本的PXI架构，并更详细地介绍了插槽2定时和触发模块的功能。
{"title":"The PXI modular instrumentation architecture","authors":"E. Starkloff, T. Fountain, G. Black","doi":"10.1109/TEST.2003.1271191","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271191","url":null,"abstract":"This paper is a technology review of PXI. It describes the basic PXI architecture and looks in more detail at the features of the slot 2 timing and triggering module.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121241131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271146
Mike P. Li
As the data rate reaches 1 Gb/s or beyond, most of the communication standards use the serial link architecture due to its capability of delivering data at a rate up to 100 Gb/s and beyond. This serial link is an asynchronized system with a bit clock embedded in the transmitting data bit stream. Transmitting multiple Gb/s data for a single channel over a distance of -10 m $1000/device). Meanwhile, the chip-to-chip (L 1 Gb/s for serial link. The transmitter, receiver, and transceiver ICs for backplane WO links are characterized by copper medium, low cost, high volume, multiple channels, and significant integration. Typical standards for copper based serial communication include: PCI-Express, Infiniband, Serial ATA, Rapid IO. The high volume and low cost can be put in perspective by the - 2 billion PCI Express ports on the chipset in a PC expected to be shipped in the first year of its production, and this number is much larger than the sum of all the Gb/s ports shipped so far for fiber based datacom and telecom applications. Testing those ICs in production is expected to encounter three major difficulties of : a.) the instrument rack-and-stack approach developed for datacom and telecom ICs will no longer be a viable solution due to its high cost and slow test time; b.) traditional ATEs are synchronized system with a distributed globe clock and do not fit into the asynchronized serial link scheme well; c.) new analog/mixed-signal parameters/functions of timing jitter, amplitude noise, eye-diagram, and bit error rate (BER) required for serial link are not offered by most ATEs with necessary accuracy at multiple Gbfs rate. It is believed that no single company along can solve a11 those chanllenges. To discuss the possible solutions in dealing with those challenges identified, a panel consists of leading experts from leading companies and academia across the technical fields of IC design and manufacture, instrumentation, and ATE is formed. Outstanding questions discussed by this panel for the multiple Gb/s serial link will include, but not limited to : a.) what need to be tested in production and why? b.) what will be the viable test method ATE, or open architecture (OA) with module instruments, or DFTBIST, or combination between them? c.) what are the bandwidth, DJ, RJ, and noise requirements for the tester hardware and how to verify them? d.) what constitute a correct jittedsignal integrity testing method? e.) how can we test BER down to within seconds?
{"title":"Production test challenges and possible solutions for multiple GB/s ICs","authors":"Mike P. Li","doi":"10.1109/TEST.2003.1271146","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271146","url":null,"abstract":"As the data rate reaches 1 Gb/s or beyond, most of the communication standards use the serial link architecture due to its capability of delivering data at a rate up to 100 Gb/s and beyond. This serial link is an asynchronized system with a bit clock embedded in the transmitting data bit stream. Transmitting multiple Gb/s data for a single channel over a distance of -10 m $1000/device). Meanwhile, the chip-to-chip (L 1 Gb/s for serial link. The transmitter, receiver, and transceiver ICs for backplane WO links are characterized by copper medium, low cost, high volume, multiple channels, and significant integration. Typical standards for copper based serial communication include: PCI-Express, Infiniband, Serial ATA, Rapid IO. The high volume and low cost can be put in perspective by the - 2 billion PCI Express ports on the chipset in a PC expected to be shipped in the first year of its production, and this number is much larger than the sum of all the Gb/s ports shipped so far for fiber based datacom and telecom applications. Testing those ICs in production is expected to encounter three major difficulties of : a.) the instrument rack-and-stack approach developed for datacom and telecom ICs will no longer be a viable solution due to its high cost and slow test time; b.) traditional ATEs are synchronized system with a distributed globe clock and do not fit into the asynchronized serial link scheme well; c.) new analog/mixed-signal parameters/functions of timing jitter, amplitude noise, eye-diagram, and bit error rate (BER) required for serial link are not offered by most ATEs with necessary accuracy at multiple Gbfs rate. It is believed that no single company along can solve a11 those chanllenges. To discuss the possible solutions in dealing with those challenges identified, a panel consists of leading experts from leading companies and academia across the technical fields of IC design and manufacture, instrumentation, and ATE is formed. Outstanding questions discussed by this panel for the multiple Gb/s serial link will include, but not limited to : a.) what need to be tested in production and why? b.) what will be the viable test method ATE, or open architecture (OA) with module instruments, or DFTBIST, or combination between them? c.) what are the bandwidth, DJ, RJ, and noise requirements for the tester hardware and how to verify them? d.) what constitute a correct jittedsignal integrity testing method? e.) how can we test BER down to within seconds?","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117171945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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