Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271084
H. Hungar, T. Margaria, B. Steffen
We study the extension of applicability of system-level testing techniques to the construction of a consistent model of (legacy) systems under test, which are seen as black boxes. We gather observations via an automated test environment and systematically extend available test suites according to learning procedures. Testing plays two roles here: (i) as an application domain and (ii) as the enabling technology for the adopted learning technique. The benefits include enhanced error detection and diagnosis, both during the testing phase and the online test of deployed systems at customer sites.
{"title":"Test-based model generation for legacy systems","authors":"H. Hungar, T. Margaria, B. Steffen","doi":"10.1109/TEST.2003.1271084","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271084","url":null,"abstract":"We study the extension of applicability of system-level testing techniques to the construction of a consistent model of (legacy) systems under test, which are seen as black boxes. We gather observations via an automated test environment and systematically extend available test suites according to learning procedures. Testing plays two roles here: (i) as an application domain and (ii) as the enabling technology for the adopted learning technique. The benefits include enhanced error detection and diagnosis, both during the testing phase and the online test of deployed systems at customer sites.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126289674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271072
B. Kruseman, Stefan van den Oetelaar
Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-100 mA of a single core. Nevertheless this is not sufficient to handle the next generations of very deep sub-micron technologies. Moreover delay-fault testing and very-low voltage testing are not a real alternative for the detection of resistive shorts. The main limitation of ∆IDDQ testing is the intra-die variation of the threshold voltage which results in variations in the off-state current. Two methods are investigated that improve the detection capabilities of ∆IDDQ testing. The first method reduces the impact of intra-die variation by reducing the amount of logic that switches states. This method can handle very large off-state currents although at the cost of a substantial increase in test time. The second method investigates the correct scaling of the intra-die variations as a function of temperature. We show that both methods improve the detection capabilities of ∆IDDQ testing.
{"title":"Detection of resistive shorts in deep sub-micron technologies","authors":"B. Kruseman, Stefan van den Oetelaar","doi":"10.1109/TEST.2003.1271072","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271072","url":null,"abstract":"Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-100 mA of a single core. Nevertheless this is not sufficient to handle the next generations of very deep sub-micron technologies. Moreover delay-fault testing and very-low voltage testing are not a real alternative for the detection of resistive shorts. The main limitation of ∆IDDQ testing is the intra-die variation of the threshold voltage which results in variations in the off-state current. Two methods are investigated that improve the detection capabilities of ∆IDDQ testing. The first method reduces the impact of intra-die variation by reducing the amount of logic that switches states. This method can handle very large off-state currents although at the cost of a substantial increase in test time. The second method investigates the correct scaling of the intra-die variations as a function of temperature. We show that both methods improve the detection capabilities of ∆IDDQ testing.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125306652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271206
R. Joshi, K. Williams, L. Whetsel
This paper describes an addressable shadow protocol device that is capable of providing connectivity between a backplane resident IEEE 1149.1 test bus master and a plurality of 1149.1 device chains existing on a board or module. The enhanced device provides for improvement in test, emulation, programming, and other applications based on the 1149.1 test bus.
{"title":"Evolution of IEEE 1149.1 addressable shadow protocol devices","authors":"R. Joshi, K. Williams, L. Whetsel","doi":"10.1109/TEST.2003.1271206","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271206","url":null,"abstract":"This paper describes an addressable shadow protocol device that is capable of providing connectivity between a backplane resident IEEE 1149.1 test bus master and a plurality of 1149.1 device chains existing on a board or module. The enhanced device provides for improvement in test, emulation, programming, and other applications based on the 1149.1 test bus.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131725116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270892
L. Whetsel
The use of AC coupled interconnects to provide communication paths between devices are increasing. The existing IEEE 1149.1 boundary scan standard (JTAG) has limitations that hinder it from being able to effectively test all AC coupled interconnects. This paper describes a simple enhancement to the JTAG architecture enabling it to operate in new modes facilitating AC interconnect testing.
{"title":"Adapting jtag for ac interconnect testing","authors":"L. Whetsel","doi":"10.1109/TEST.2003.1270892","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270892","url":null,"abstract":"The use of AC coupled interconnects to provide communication paths between devices are increasing. The existing IEEE 1149.1 boundary scan standard (JTAG) has limitations that hinder it from being able to effectively test all AC coupled interconnects. This paper describes a simple enhancement to the JTAG architecture enabling it to operate in new modes facilitating AC interconnect testing.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128382901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270885
Puneet Gupta, M. Hsiao
The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture small- distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. Clustering of paths has been done in order to improve the test set quality. Implications were used to identify the untestable paths. Finally an incremental propagation based ATPG is used for transition faults. Results for ISCAS'85 and full-scan ISCAS'89 benchmark circuits show that the filtered non- robust path set can be reduced to 40% smaller than the conventional path set without losing delay defect coverage. Clustering reduces vector size in average by about 40%.
{"title":"High quality atpg for delay defects","authors":"Puneet Gupta, M. Hsiao","doi":"10.1109/TEST.2003.1270885","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270885","url":null,"abstract":"The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture small- distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. Clustering of paths has been done in order to improve the test set quality. Implications were used to identify the untestable paths. Finally an incremental propagation based ATPG is used for transition faults. Results for ISCAS'85 and full-scan ISCAS'89 benchmark circuits show that the filtered non- robust path set can be reduced to 40% smaller than the conventional path set without losing delay defect coverage. Clustering reduces vector size in average by about 40%.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132715539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271148
John C. Johnson
The agenda of high volume manufacturing (HVM) test is cost. Equipment costs, throughput, factory overhead, yield, and many other parameters make up overall test costs. But the start of any cost optimization must start with a very clear perspective of what HVM test must achieve, and what it cannot afford to be responsible for. HVM test is mostly a screen to ensure that outgoing products meet established goals for quality defect rate and reliability. It cannot afford to duplicate design validation processes that do not efficiently support this primary screening goal. Multi-GB/s devices drive this distinction to a critical level.
{"title":"Cost containment for high-volume test of multi-gb/s ports","authors":"John C. Johnson","doi":"10.1109/TEST.2003.1271148","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271148","url":null,"abstract":"The agenda of high volume manufacturing (HVM) test is cost. Equipment costs, throughput, factory overhead, yield, and many other parameters make up overall test costs. But the start of any cost optimization must start with a very clear perspective of what HVM test must achieve, and what it cannot afford to be responsible for. HVM test is mostly a screen to ensure that outgoing products meet established goals for quality defect rate and reliability. It cannot afford to duplicate design validation processes that do not efficiently support this primary screening goal. Multi-GB/s devices drive this distinction to a critical level.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130973340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270861
D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Reorda, V. Tancorre, M. Violante
This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE.
{"title":"Exploiting programmable bist for the diagnosis of embedded memory cores","authors":"D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Reorda, V. Tancorre, M. Violante","doi":"10.1109/TEST.2003.1270861","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270861","url":null,"abstract":"This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271096
Huaxing Tang, S. Reddy, I. Pomeranz
We propose a new method for reducing test data volume and test application time in scan designs with multiple scan chains. The method uses a reconfigurable switch to apply tests from a limited number of external inputs to a large number of internal scan chains. The reconfigurable switch allows different subsets of scan chains to be connected to the same external input at different times, thus allowing varied tests to be applied to the circuit.
{"title":"On reducing test data volume and test application time for multiple scan chain designs","authors":"Huaxing Tang, S. Reddy, I. Pomeranz","doi":"10.1109/TEST.2003.1271096","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271096","url":null,"abstract":"We propose a new method for reducing test data volume and test application time in scan designs with multiple scan chains. The method uses a reconfigurable switch to apply tests from a limited number of external inputs to a large number of internal scan chains. The reconfigurable switch allows different subsets of scan chains to be connected to the same external input at different times, thus allowing varied tests to be applied to the circuit.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133769653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271079
H. Hashempour, F. Meyer, F. Lombardi, F. Karimi
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (OUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.
{"title":"Hybrid multisite testing at manufacturing","authors":"H. Hashempour, F. Meyer, F. Lombardi, F. Karimi","doi":"10.1109/TEST.2003.1271079","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271079","url":null,"abstract":"This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (OUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116758408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270909
J. Nejedlo
This paper summarizes the test challenges associated with next -generation platform buses and introduces an Intel-developed technology called IBISTTM (Interconnect Built-In Self-Test) created to meet those challenges. The IBISTTM testing methodology and associated on-die architecture customized for PCI Express (PCIe) interface is described.
{"title":"IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO","authors":"J. Nejedlo","doi":"10.1109/TEST.2003.1270909","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270909","url":null,"abstract":"This paper summarizes the test challenges associated with next -generation platform buses and introduces an Intel-developed technology called IBISTTM (Interconnect Built-In Self-Test) created to meet those challenges. The IBISTTM testing methodology and associated on-die architecture customized for PCI Express (PCIe) interface is described.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121906898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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