Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045006
P. Lu, P. Andreani, A. Liscidini
Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.
{"title":"A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs","authors":"P. Lu, P. Andreani, A. Liscidini","doi":"10.1109/ESSCIRC.2011.6045006","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045006","url":null,"abstract":"Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125655812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044909
J. Rabaey
The exact functioning and operation of the brain has been and still is to a major degree a great mystery. The recent introduction of advanced imaging tools such as fMRI, EEG and eCoG and, most recently, direct neural sensing are throwing the doors of neuroscience wide open, and enable direct in-vivo observations of the brain at work in dynamic conditions. This may help to address a broad range of neural impairments and diseases, such as stroke, paralysis, epilepsy, depression, etc. However, for all of these to happen it is essential that neural interface circuitry is developed that surpasses the state of the art in ultra-low power miniaturized design by at least an order of magnitude. Furthermore, the resulting sensory/stimulation nodes have to be energy-self contained and support wireless links > 1 Mbps. This paper explores the opportunities of accomplishing just that, and demonstrates the feasibility with a number of examples. The potential outcomes of these developments are just "mind-blowing", and can dramatically impact the evolution of human-cyber interfaces in the decades to come.
{"title":"Brain-machine interfaces as the new frontier in extreme miniaturization","authors":"J. Rabaey","doi":"10.1109/ESSCIRC.2011.6044909","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044909","url":null,"abstract":"The exact functioning and operation of the brain has been and still is to a major degree a great mystery. The recent introduction of advanced imaging tools such as fMRI, EEG and eCoG and, most recently, direct neural sensing are throwing the doors of neuroscience wide open, and enable direct in-vivo observations of the brain at work in dynamic conditions. This may help to address a broad range of neural impairments and diseases, such as stroke, paralysis, epilepsy, depression, etc. However, for all of these to happen it is essential that neural interface circuitry is developed that surpasses the state of the art in ultra-low power miniaturized design by at least an order of magnitude. Furthermore, the resulting sensory/stimulation nodes have to be energy-self contained and support wireless links > 1 Mbps. This paper explores the opportunities of accomplishing just that, and demonstrates the feasibility with a number of examples. The potential outcomes of these developments are just \"mind-blowing\", and can dramatically impact the evolution of human-cyber interfaces in the decades to come.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126148106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044941
M. Kaltiokallio, V. Saari, J. Ryynänen, Sami Kallioinen, A. Pärssinen
This paper presents a wideband blocker filtering technique for a RF front-end. The wideband LNA and the transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The front-end achieves a gain of 43 and 41 dB, noise figure of 3.2 and 5.7 dB with IIP3 of −13 and −5 dBm with the transferred-impedance filter turned off and on, respectively. Added selectivity of 6 dB is achieved by using the structure described in this paper.
{"title":"Wideband 2 to 6GHz RF front-end with blocker filtering","authors":"M. Kaltiokallio, V. Saari, J. Ryynänen, Sami Kallioinen, A. Pärssinen","doi":"10.1109/ESSCIRC.2011.6044941","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044941","url":null,"abstract":"This paper presents a wideband blocker filtering technique for a RF front-end. The wideband LNA and the transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The front-end achieves a gain of 43 and 41 dB, noise figure of 3.2 and 5.7 dB with IIP3 of −13 and −5 dBm with the transferred-impedance filter turned off and on, respectively. Added selectivity of 6 dB is achieved by using the structure described in this paper.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130334110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044966
J. Lindstrand, C. Bryant, Markus Törmänen, H. Sjöland
This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52×0.48mm2 including pads.
{"title":"A 1.6–2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOS","authors":"J. Lindstrand, C. Bryant, Markus Törmänen, H. Sjöland","doi":"10.1109/ESSCIRC.2011.6044966","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044966","url":null,"abstract":"This paper presents a wideband CMOS power amplifier intended for cellular handset applications. The circuit exploits injection locking to achieve a power gain of 20.5dB from a single stage amplifier. The maximum output power of 29dBm, with a peak drain- and power-added-efficiency (PAE) of 66% and 64%, respectively, occurs at a center frequency of 2GHz with a 3V supply. A cross-coupled cascode topology enables a wideband PAE exceeding 50% from 1.6 to 2.6GHz. For output power levels below 4dBm the circuit operates as a linear class AB amplifier with a power consumption of 17mW from a 0.48V supply. The power gain of 20.5dB is kept constant for all output powers; with an AM-AM- and AM-PM-conversion of 0.2dB and 17deg, respectively, over the entire WCDMA dynamic range of 80dB. The circuit is implemented in a standard 65nm CMOS process with a total chip area of 0.52×0.48mm2 including pads.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127973084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044969
Hoai-Nam Nguyen, S. Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Y. Eo, Hyun-Kyu Yu
This paper presents a low power discrete-time receiver supporting three broadcast services FM, T-DMB and DAB. To meet the requirement of sensitivity, three LNAs are implemented to cover each band. The proposed mixer core is terminated by a common-gate current buffer to improve linearity and merged with a switched-capacitor sampled filter in current mode for low power and low complexity. The filter performs the second-order low-pass filtering with anti-aliasing ratio up to 70 dB at 1.6 MHz bandwidth. The chip is fabricated in a 90 nm CMOS technology and dissipates 11 mA current from 1.2 V supply. The receiver shows 48 dB maximum gain, 60 dB gain control range, 2.7 dB noise figure, and −22/0 dBm IIP3 in LNA high/low gain mode.
{"title":"A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip","authors":"Hoai-Nam Nguyen, S. Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Y. Eo, Hyun-Kyu Yu","doi":"10.1109/ESSCIRC.2011.6044969","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044969","url":null,"abstract":"This paper presents a low power discrete-time receiver supporting three broadcast services FM, T-DMB and DAB. To meet the requirement of sensitivity, three LNAs are implemented to cover each band. The proposed mixer core is terminated by a common-gate current buffer to improve linearity and merged with a switched-capacitor sampled filter in current mode for low power and low complexity. The filter performs the second-order low-pass filtering with anti-aliasing ratio up to 70 dB at 1.6 MHz bandwidth. The chip is fabricated in a 90 nm CMOS technology and dissipates 11 mA current from 1.2 V supply. The receiver shows 48 dB maximum gain, 60 dB gain control range, 2.7 dB noise figure, and −22/0 dBm IIP3 in LNA high/low gain mode.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130131303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044959
Blazej Nowacki, N. Paulino, J. Goes
This paper presents a Δ∑ modulator (Δ∑M) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a Δ∑M using mostly dynamic elements thus reducing the power dissipation. A prototyped 2nd-order Δ∑M circuit, using this technique, was designed in a 130 nm CMOS technology; the measured results prove the validity of the concept. Measured results show that the Δ∑M achieves a peak SNDR of 72.8 dB, a peak SNR of 73.9 dB and a DR of 78.2 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating less than 300 μW from a 1.2V power supply voltage, resulting in a FOM of 139.3 fJ/conv.-step. As far as the authors have knowledge, this circuit represents the first prototyped switched-capacitor (SC) circuit based on UIS.
{"title":"A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS","authors":"Blazej Nowacki, N. Paulino, J. Goes","doi":"10.1109/ESSCIRC.2011.6044959","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044959","url":null,"abstract":"This paper presents a Δ∑ modulator (Δ∑M) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a Δ∑M using mostly dynamic elements thus reducing the power dissipation. A prototyped 2nd-order Δ∑M circuit, using this technique, was designed in a 130 nm CMOS technology; the measured results prove the validity of the concept. Measured results show that the Δ∑M achieves a peak SNDR of 72.8 dB, a peak SNR of 73.9 dB and a DR of 78.2 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating less than 300 μW from a 1.2V power supply voltage, resulting in a FOM of 139.3 fJ/conv.-step. As far as the authors have knowledge, this circuit represents the first prototyped switched-capacitor (SC) circuit based on UIS.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129575293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044896
Sushrant Monga, Vinod Kumar
Architecture for I/O driver is proposed for high voltage (up to 3.6V) application by using low voltage devices. The proposed I/O is configurable to support multi supply range (1.8V-2.7V-3.6V). The buffer is designed in 40nm CMOS process by using standard 32Å oxide devices. This technique generates a set of dynamic bias signals as a function of input data sequence and the present value of the output which are fed to the cascoded stages to derive the next state of the output PAD. The experimental results confirmed successful operation up to 200 MHz with 10pF load on IO pad, with multiple supply rails.
{"title":"A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS","authors":"Sushrant Monga, Vinod Kumar","doi":"10.1109/ESSCIRC.2011.6044896","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044896","url":null,"abstract":"Architecture for I/O driver is proposed for high voltage (up to 3.6V) application by using low voltage devices. The proposed I/O is configurable to support multi supply range (1.8V-2.7V-3.6V). The buffer is designed in 40nm CMOS process by using standard 32Å oxide devices. This technique generates a set of dynamic bias signals as a function of input data sequence and the present value of the output which are fed to the cascoded stages to derive the next state of the output PAD. The experimental results confirmed successful operation up to 200 MHz with 10pF load on IO pad, with multiple supply rails.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117192553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044946
W. Liew, X. Zou, Y. Lian
This paper presents a power-efficient system architecture for the design of multiple-channel neural recording interface. A new multiple-channel SAR ADC is proposed to facilitate multiplexing among channels, thus eliminates the need for analog multiplexer and associated buffers. The proposed ADC is verified through a 16-channel recording chip fabricated in a standard 0.13-μm CMOS technology with an active area of 1.17 mm2. The chip consumes 18 μW from a 0.5-V supply and attains a noise efficiency factor of 3.09. The average per channel power and area are 1.13 μW and 0.073 mm2, respectively, which are the lowest among existing multiple-channel designs.
{"title":"A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing scheme","authors":"W. Liew, X. Zou, Y. Lian","doi":"10.1109/ESSCIRC.2011.6044946","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044946","url":null,"abstract":"This paper presents a power-efficient system architecture for the design of multiple-channel neural recording interface. A new multiple-channel SAR ADC is proposed to facilitate multiplexing among channels, thus eliminates the need for analog multiplexer and associated buffers. The proposed ADC is verified through a 16-channel recording chip fabricated in a standard 0.13-μm CMOS technology with an active area of 1.17 mm2. The chip consumes 18 μW from a 0.5-V supply and attains a noise efficiency factor of 3.09. The average per channel power and area are 1.13 μW and 0.073 mm2, respectively, which are the lowest among existing multiple-channel designs.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131051482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044957
A. Ashry, H. Aboushady
A 4th order subsampled RF LC ∑Δ ADC suitable for Software Defined Radio applications is presented. The ADC is clocked at 3.2GHz and centered at 2.4GHz. The simplicity of the ADC architecture combined with the subsampling technique result in a significant performance enhancement and power consumption reduction. A sine-shaped feedback DAC is used, not only for its reduced sensitivity to clock jitter but also for its more convenient frequency response to subsampled ∑Δ ADCs. An efficient algorithm for the tuning and calibration of the LC-based loop filter is presented. The ADC is implemented in a standard 130nm CMOS technology. It achieves a 51dB SFDR and a 40dB SNDR in a 25MHz BW and consumes only 19mW from a 1.2V supply.
{"title":"A 4th order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DAC","authors":"A. Ashry, H. Aboushady","doi":"10.1109/ESSCIRC.2011.6044957","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044957","url":null,"abstract":"A 4th order subsampled RF LC ∑Δ ADC suitable for Software Defined Radio applications is presented. The ADC is clocked at 3.2GHz and centered at 2.4GHz. The simplicity of the ADC architecture combined with the subsampling technique result in a significant performance enhancement and power consumption reduction. A sine-shaped feedback DAC is used, not only for its reduced sensitivity to clock jitter but also for its more convenient frequency response to subsampled ∑Δ ADCs. An efficient algorithm for the tuning and calibration of the LC-based loop filter is presented. The ADC is implemented in a standard 130nm CMOS technology. It achieves a 51dB SFDR and a 40dB SNDR in a 25MHz BW and consumes only 19mW from a 1.2V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131124440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044989
M. Sosio, A. Liscidini, R. Castello, F. Bernardinis
A filtering ADC used to implement the complete base-band in a receiver chain is presented. Passive filtering and in-band noise shaping lead to a frequency dependent dynamic range that better fits with the system requirements of a wireless receiver. The 90nm CMOS prototype is embedded in a fully integrated tuner compliant with DVB-T and ATSC standards. For a 6MHz channel bandwidth, the filtering ADC exhibits a frequency dependent dynamic range varying from 75.6dB to 90dB while drawing 30mA from a 1.8V supply.
{"title":"A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC","authors":"M. Sosio, A. Liscidini, R. Castello, F. Bernardinis","doi":"10.1109/ESSCIRC.2011.6044989","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044989","url":null,"abstract":"A filtering ADC used to implement the complete base-band in a receiver chain is presented. Passive filtering and in-band noise shaping lead to a frequency dependent dynamic range that better fits with the system requirements of a wireless receiver. The 90nm CMOS prototype is embedded in a fully integrated tuner compliant with DVB-T and ATSC standards. For a 6MHz channel bandwidth, the filtering ADC exhibits a frequency dependent dynamic range varying from 75.6dB to 90dB while drawing 30mA from a 1.8V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130667384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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