Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326855
M. Sivaraman, A. Strojwas
Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations/spl minus/caused by the imperfect fabrication process/spl minus/which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance.<>
{"title":"Towards incorporating device parameter variations in timing analysis","authors":"M. Sivaraman, A. Strojwas","doi":"10.1109/EDTC.1994.326855","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326855","url":null,"abstract":"Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations/spl minus/caused by the imperfect fabrication process/spl minus/which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326868
D. Jacquet, G. Saucier
Presents the design of a dedicated chip achieving the recognition phase of layered neural networks. General back-propagation (GBP) and learning vector quantization (LVQ) neurons can be emulated on this chip (called the OCR-chip). It consists of five processors: four neuron processors interconnected in a ring, each are computing several states of different GBP neurons, and a LVQ processor used to compute the states of the LVQ neurons. Connections between GBP neurons folded on the same processor are implemented in each processor by using an address generator based on modulus m counters. An optical character recognition (OCR) neural network (840 neurons in 4 layers and 800 LVQ neurons) is used as demonstrator.<>
{"title":"Design of a digital neural chip: application to optical character recognition by neural network","authors":"D. Jacquet, G. Saucier","doi":"10.1109/EDTC.1994.326868","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326868","url":null,"abstract":"Presents the design of a dedicated chip achieving the recognition phase of layered neural networks. General back-propagation (GBP) and learning vector quantization (LVQ) neurons can be emulated on this chip (called the OCR-chip). It consists of five processors: four neuron processors interconnected in a ring, each are computing several states of different GBP neurons, and a LVQ processor used to compute the states of the LVQ neurons. Connections between GBP neurons folded on the same processor are implemented in each processor by using an address generator based on modulus m counters. An optical character recognition (OCR) neural network (840 neurons in 4 layers and 800 LVQ neurons) is used as demonstrator.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128795939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326810
Peter T. Breuer, Luis Sánchez-Fernández, C. D. Kloos
A simple formal semantics for the standard hardware description language VHDL is set out in functional style. The presentation comprises an executable specification for a synchronously clocked VHDL simulator.<>
{"title":"Clean formal semantics for VHDL","authors":"Peter T. Breuer, Luis Sánchez-Fernández, C. D. Kloos","doi":"10.1109/EDTC.1994.326810","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326810","url":null,"abstract":"A simple formal semantics for the standard hardware description language VHDL is set out in functional style. The presentation comprises an executable specification for a synchronously clocked VHDL simulator.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128574382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326897
F. Calvo, P. Plaza, P. Mateos
The ICM2 circuit is part of a new ATM (Asynchronous Transfer Mode) switch core of a new Broad Band ISDN exchange system that can switch at least 2.488 Gb/s. It is being developed by TELEFONICA I+D for the Spanish PTT, TELEFONICA. The circuit was processed with a 0.7 micron CMOS technology, and a first silicon success has been obtained. Its die size is 12.8/spl times/12.1 sqmm and its working frequency is 70 MHz.<>
{"title":"ICM2 IC: A new ATM switching element for 2.48 Gb/s communications","authors":"F. Calvo, P. Plaza, P. Mateos","doi":"10.1109/EDTC.1994.326897","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326897","url":null,"abstract":"The ICM2 circuit is part of a new ATM (Asynchronous Transfer Mode) switch core of a new Broad Band ISDN exchange system that can switch at least 2.488 Gb/s. It is being developed by TELEFONICA I+D for the Spanish PTT, TELEFONICA. The circuit was processed with a 0.7 micron CMOS technology, and a first silicon success has been obtained. Its die size is 12.8/spl times/12.1 sqmm and its working frequency is 70 MHz.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128748921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326898
H. Nguyen, J. Tual, L. Ducousso, M. Thill, P. Vallet
This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits.<>
{"title":"Logic synthesis and verification of the CPU and caches of a mainframe system","authors":"H. Nguyen, J. Tual, L. Ducousso, M. Thill, P. Vallet","doi":"10.1109/EDTC.1994.326898","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326898","url":null,"abstract":"This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116737749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326866
M. Srivastava, M. Potkonjak
We present algorithm transformations to simultaneously optimize for throughput and latency for the important case of linear time-invariant DSP systems. Although throughput alone can be arbitrarily improved using previously published techniques, none of them is effective when latency constraints are considered. We have used a state-space based approach which treats various algorithm transformations in an integrated fashion, and answers analytically whether it is possible to simultaneously meet any given combination of constraints on latency and throughput. The analytic approach is optimum and constructive in nature, and produces a complete implementation when feasibility conditions are fulfilled. We also present a sub-optimal but hardware efficient heuristic approach. On all benchmarks the new approaches show much superior results than published ones.<>
{"title":"Transforming linear systems for joint latency and throughput optimization","authors":"M. Srivastava, M. Potkonjak","doi":"10.1109/EDTC.1994.326866","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326866","url":null,"abstract":"We present algorithm transformations to simultaneously optimize for throughput and latency for the important case of linear time-invariant DSP systems. Although throughput alone can be arbitrarily improved using previously published techniques, none of them is effective when latency constraints are considered. We have used a state-space based approach which treats various algorithm transformations in an integrated fashion, and answers analytically whether it is possible to simultaneously meet any given combination of constraints on latency and throughput. The analytic approach is optimum and constructive in nature, and produces a complete implementation when feasibility conditions are fulfilled. We also present a sub-optimal but hardware efficient heuristic approach. On all benchmarks the new approaches show much superior results than published ones.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132855627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326877
M. Damiani
Nondeterministic finite-state machines are being considered for extracting and representing sequential don't care conditions arising in high-level descriptions. This paper shows that they can also be used for capturing in full the sequential don't cares arising from embedding of a machine in a larger synchronous network in a uniform way. A novel algorithm for synthesizing a minimum-state deterministic finite-state machine from a nondeterministic one is developed here. The techniques developed in this paper are useful when incorporated in a synthesis system extracting sequential don't care information from high-level descriptions.<>
{"title":"Nondeterministic finite-state machines and sequential don't cares","authors":"M. Damiani","doi":"10.1109/EDTC.1994.326877","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326877","url":null,"abstract":"Nondeterministic finite-state machines are being considered for extracting and representing sequential don't care conditions arising in high-level descriptions. This paper shows that they can also be used for capturing in full the sequential don't cares arising from embedding of a machine in a larger synchronous network in a uniform way. A novel algorithm for synthesizing a minimum-state deterministic finite-state machine from a nondeterministic one is developed here. The techniques developed in this paper are useful when incorporated in a synthesis system extracting sequential don't care information from high-level descriptions.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326867
L. Ramachandran, D. Gajski, Viraphol Chaiyakul
During synthesis of behavioral descriptions array variables are implemented with memory modules. In this paper we show that simple one-to-one mapping between the array variables and the memory modules lead to inefficient designs. We propose a new algorithm, MeSA, which computes for a given set of array variables, (a) the number of memory modules, (b) the size of each module (c) the number of ports on each module and (d) and the grouping of array variables assigned to each memory module. The effects of address translations are incorporated into the algorithm. While most previous research efforts have concentrated on scalar variables, the primary focus in this paper is deriving efficient storage assignment for array variables.<>
{"title":"An algorithm for array variable clustering","authors":"L. Ramachandran, D. Gajski, Viraphol Chaiyakul","doi":"10.1109/EDTC.1994.326867","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326867","url":null,"abstract":"During synthesis of behavioral descriptions array variables are implemented with memory modules. In this paper we show that simple one-to-one mapping between the array variables and the memory modules lead to inefficient designs. We propose a new algorithm, MeSA, which computes for a given set of array variables, (a) the number of memory modules, (b) the size of each module (c) the number of ports on each module and (d) and the grouping of array variables assigned to each memory module. The effects of address translations are incorporated into the algorithm. While most previous research efforts have concentrated on scalar variables, the primary focus in this paper is deriving efficient storage assignment for array variables.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114329795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326803
H. Ahmad, R. Mack
A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution.<>
{"title":"AREAL: automated reasoning expert for analogue layout","authors":"H. Ahmad, R. Mack","doi":"10.1109/EDTC.1994.326803","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326803","url":null,"abstract":"A system for analogue circuit layout generation is presented which utilises knowledge and geometric reasoning to prune the design space. Topological and geometric constraints, deduced from analogue and connectivity information, are expressed in the form of Boolean relations, and are imposed and preserved throughout the solution by means of a Boolean-constraint-solver. The reduced design space is then explored by a controlled branch-and-bound process to find an optimal solution.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134029620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326809
K. Schneider, T. Kropf, Ramayya Kumar
Usually, digital circuits are split up into control and data path as there are specific synthesis methods for controllers and operation units. However, all known approaches to hardware verification which make use of this fact, model the operation unit also as a finite-state machine. This leads to enormous space requirements which limit the applicability of these approaches. In order to avoid this, abstraction mechanisms can be used to map Boolean tuples onto more complex data types. However, approaches to the verification of generic n-bit circuits have considered so far only circuits with simple controllers, such that the verification of only combinational circuits or special cases of sequential circuits is possible. In this paper, we present a new approach to hardware verification which allows the verification of generic circuits with non-trivial controllers.<>
{"title":"Control path oriented verification of sequential generic circuits with control and data path","authors":"K. Schneider, T. Kropf, Ramayya Kumar","doi":"10.1109/EDTC.1994.326809","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326809","url":null,"abstract":"Usually, digital circuits are split up into control and data path as there are specific synthesis methods for controllers and operation units. However, all known approaches to hardware verification which make use of this fact, model the operation unit also as a finite-state machine. This leads to enormous space requirements which limit the applicability of these approaches. In order to avoid this, abstraction mechanisms can be used to map Boolean tuples onto more complex data types. However, approaches to the verification of generic n-bit circuits have considered so far only circuits with simple controllers, such that the verification of only combinational circuits or special cases of sequential circuits is possible. In this paper, we present a new approach to hardware verification which allows the verification of generic circuits with non-trivial controllers.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：