Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326858
M. E. Dalkiliç, Vijay Pitchumani
Presents an accurate resource lower bound estimation technique which leads to an efficient, and optimal solution of time-constrained as well as hardware resource-constrained scheduling problems in high-level synthesis. A given time or hardware constrained scheduling problem is transformed into a cost ordered sequence of feasible scheduling problems where a solution to this new problem is guaranteed to be an optimal solution to the original problem. Efficiency of the approach is demonstrated on large high-level synthesis benchmarks like the elliptical wave filter and the discrete cosine transform.<>
{"title":"Optimal operation scheduling using resource lower bound estimations","authors":"M. E. Dalkiliç, Vijay Pitchumani","doi":"10.1109/EDTC.1994.326858","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326858","url":null,"abstract":"Presents an accurate resource lower bound estimation technique which leads to an efficient, and optimal solution of time-constrained as well as hardware resource-constrained scheduling problems in high-level synthesis. A given time or hardware constrained scheduling problem is transformed into a cost ordered sequence of feasible scheduling problems where a solution to this new problem is guaranteed to be an optimal solution to the original problem. Efficiency of the approach is demonstrated on large high-level synthesis benchmarks like the elliptical wave filter and the discrete cosine transform.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326900
S. Gai, P. Montessoro, M. Reorda
The paper describes a new approach to the fault simulation of synchronous sequential circuits. Its novelty comes from combining the event-driven compiled-code simulation technique proposed by H. K. Lee and D. S. Ha (1992) with the single fault propagation fault-parallel fault simulation algorithm used by F. Maamari and J. Rajski (1988). Our approach is particularly suited for those applications requiring the fault simulation of very high numbers of input patterns, like signature computation or fault dictionary construction. A fault simulator named TORSIM has been written to verify the effectiveness of the approach. The results we present show an average speed-up in terms of CPU time of more than one order of magnitude with respect to the ones reported by Maamari and Rajski.<>
提出了一种同步时序电路故障仿真的新方法。它的新颖之处是将H. K. Lee和D. S. Ha(1992)提出的事件驱动的编译代码模拟技术与F. Maamari和J. Rajski(1988)使用的单故障传播故障-并行故障模拟算法相结合。我们的方法特别适合那些需要大量输入模式的故障模拟的应用程序，如签名计算或故障字典构造。为验证该方法的有效性，编写了故障模拟器TORSIM。我们给出的结果显示，与Maamari和Rajski报告的结果相比，CPU时间的平均加速幅度超过了一个数量级。
{"title":"TORSIM: An efficient fault simulator for synchronous sequential circuits","authors":"S. Gai, P. Montessoro, M. Reorda","doi":"10.1109/EDTC.1994.326900","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326900","url":null,"abstract":"The paper describes a new approach to the fault simulation of synchronous sequential circuits. Its novelty comes from combining the event-driven compiled-code simulation technique proposed by H. K. Lee and D. S. Ha (1992) with the single fault propagation fault-parallel fault simulation algorithm used by F. Maamari and J. Rajski (1988). Our approach is particularly suited for those applications requiring the fault simulation of very high numbers of input patterns, like signature computation or fault dictionary construction. A fault simulator named TORSIM has been written to verify the effectiveness of the approach. The results we present show an average speed-up in terms of CPU time of more than one order of magnitude with respect to the ones reported by Maamari and Rajski.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326807
T. Johansson, L. R. Virtanen, J. Gobbi
In a modern IC-process, small-value high-quality capacitors can be designed for placement under metal lines using only existing layout layers and no additional processing. These capacitors may be added to each noise generating block to improve decoupling without using additional silicon area or additional processing. We call this trick "Underground capacitors" but it works under any wide metal line. Two types of circuits were fabricated using a 0.8 /spl mu/m BiCMOS process with three levels of metallization, characterized and compared in the study: a 32/33 prescaler with internal decoupling capacitors and a 64/65 prescaler with no internal decoupling. The bipolar part of the BiCMOS process was used for the circuit design. The dual-modulus prescaler was chosen as a test vehicle because of its importance for frequency synthesis systems.<>
在现代集成电路工艺中，可以设计小值高质量电容器，仅使用现有的布局层，无需额外处理，即可放置在金属线下。这些电容器可以添加到每个噪声产生块以改善去耦，而无需使用额外的硅面积或额外的处理。我们称这种方法为“地下电容器”，但它可以在任何宽的金属线路下工作。采用0.8 /spl μ l /m的BiCMOS工艺和三层金属化工艺制备了两种类型的电路，并对其进行了表征和比较:具有内部去耦电容的32/33预分频器和没有内部去耦的64/65预分频器。利用BiCMOS工艺的双极部分进行电路设计。考虑到双模预分频器在频率合成系统中的重要性，选择双模预分频器作为测试载体。
{"title":"\"Underground capacitors\"/spl minus/Very efficient decoupling for high performance UHF signal processing ICs","authors":"T. Johansson, L. R. Virtanen, J. Gobbi","doi":"10.1109/EDTC.1994.326807","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326807","url":null,"abstract":"In a modern IC-process, small-value high-quality capacitors can be designed for placement under metal lines using only existing layout layers and no additional processing. These capacitors may be added to each noise generating block to improve decoupling without using additional silicon area or additional processing. We call this trick \"Underground capacitors\" but it works under any wide metal line. Two types of circuits were fabricated using a 0.8 /spl mu/m BiCMOS process with three levels of metallization, characterized and compared in the study: a 32/33 prescaler with internal decoupling capacitors and a 64/65 prescaler with no internal decoupling. The bipolar part of the BiCMOS process was used for the circuit design. The dual-modulus prescaler was chosen as a test vehicle because of its importance for frequency synthesis systems.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326856
Ronn B. Brashear, N. Menezes, C. Oh, L. Pileggi, M. R. Mercer
Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a methodology for statistical timing analysis. The authors present a triple-node delay model which inherently captures the effect of input transition time on the gate delays. Response surface methods are used so that the statistical gate delays are generated efficiently. A new path sensitization criterion based on the minimum propagatable pulse width (MPPW) of the gates along a path is used to check for false paths. The overlap of a path with longer paths determines its "statistical significance" to the overall circuit delay. Finally, the circuit delay probability density function is computed by performing a Monte Carlo simulation on the statistically significant path set.<>
{"title":"Predicting circuit performance using circuit-level statistical timing analysis","authors":"Ronn B. Brashear, N. Menezes, C. Oh, L. Pileggi, M. R. Mercer","doi":"10.1109/EDTC.1994.326856","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326856","url":null,"abstract":"Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a methodology for statistical timing analysis. The authors present a triple-node delay model which inherently captures the effect of input transition time on the gate delays. Response surface methods are used so that the statistical gate delays are generated efficiently. A new path sensitization criterion based on the minimum propagatable pulse width (MPPW) of the gates along a path is used to check for false paths. The overlap of a path with longer paths determines its \"statistical significance\" to the overall circuit delay. Finally, the circuit delay probability density function is computed by performing a Monte Carlo simulation on the statistically significant path set.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131310979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326833
J. Naganuma, T. Ogura, T. Hoshino
This paper proposes a new environment for high-level LSI design validation using "Algorithmic Debugging" and evaluates its benefits on three significant examples. A design is specified at a high-level using the structured analysis (SA) method and some errors included in SA specifications are efficiently located by answering just a few queries from the debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. This environment promises to be an important step towards efficient high-level LSI design validation.<>
{"title":"High-level design validation using algorithmic debugging","authors":"J. Naganuma, T. Ogura, T. Hoshino","doi":"10.1109/EDTC.1994.326833","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326833","url":null,"abstract":"This paper proposes a new environment for high-level LSI design validation using \"Algorithmic Debugging\" and evaluates its benefits on three significant examples. A design is specified at a high-level using the structured analysis (SA) method and some errors included in SA specifications are efficiently located by answering just a few queries from the debugger. The number of interactions between the designer and the debugger is reduced by a factor of ten to a hundred compared to conventional simulation based validation methodologies. This environment promises to be an important step towards efficient high-level LSI design validation.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2676 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123263850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326904
F. Franssen, L. Nachtergaele, H. Samsom, F. Catthoor, H. Man
This paper addresses the important problem of efficient system-level evaluation for real-time multi-dimensional signal processing systems, as occurring in image, speech and video processing. We solve both the difficult task of finding a correct procedural ordering for the evaluation (without expanding the code to scalars) and the optimisation of the loop organisation, leading to an acceptable amount of memory within the system-level evaluation and/or software/hardware synthesis environment. The effectiveness of our solution is substantiated with several realistic test cases.<>
{"title":"Control flow optimization for fast system simulation and storage minimization /spl lsqb/real-time multidimensional signal processing/spl rsqb/","authors":"F. Franssen, L. Nachtergaele, H. Samsom, F. Catthoor, H. Man","doi":"10.1109/EDTC.1994.326904","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326904","url":null,"abstract":"This paper addresses the important problem of efficient system-level evaluation for real-time multi-dimensional signal processing systems, as occurring in image, speech and video processing. We solve both the difficult task of finding a correct procedural ordering for the evaluation (without expanding the code to scalars) and the optimisation of the loop organisation, leading to an acceptable amount of memory within the system-level evaluation and/or software/hardware synthesis environment. The effectiveness of our solution is substantiated with several realistic test cases.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124322983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326878
Yosinori Watanabe, R. Brayton
This paper is concerned with the problem of optimizing a system of interacting finite state machines (FSMs). It has been shown previously by the authors that the complete set of sequential behaviors that can be implemented at a particular component of the system can be computed and represented by a single non-deterministic FSM, called the E-machine. In this paper, we consider the problem of finding an optimum behavior for the component, which is given by minimizing the E-machine, where the cost function is the number of states required for representing a behavior. We first present a theoretical analysis, in which we show the E-machine has a special property called pseudo nondeterminism, and this property can be effectively used for solving the problem. We then propose a heuristic method. The algorithm has been implemented, and initial experiments are given.<>
{"title":"State minimization of pseudo non-deterministic FSMs","authors":"Yosinori Watanabe, R. Brayton","doi":"10.1109/EDTC.1994.326878","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326878","url":null,"abstract":"This paper is concerned with the problem of optimizing a system of interacting finite state machines (FSMs). It has been shown previously by the authors that the complete set of sequential behaviors that can be implemented at a particular component of the system can be computed and represented by a single non-deterministic FSM, called the E-machine. In this paper, we consider the problem of finding an optimum behavior for the component, which is given by minimizing the E-machine, where the cost function is the number of states required for representing a behavior. We first present a theoretical analysis, in which we show the E-machine has a special property called pseudo nondeterminism, and this property can be effectively used for solving the problem. We then propose a heuristic method. The algorithm has been implemented, and initial experiments are given.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116889459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326882
M. Favalli, M. Dalpasso, P. Olivo, B. Riccò
This work presents a fault model to effectively account for broken connections inside CMOS circuits. The proposed model is very general, since it allows one to detect broken connections that cannot be individualized by means of test sequences for stuck-open faults; in addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node. Conditions for the detection of broken connections are derived from electrical considerations and the minimum number of input vectors to be applied to test for a broken connection in a node is determined by graph theory. The model can be used to derive tests and to perform fault simulations independently of the actual layout of the circuit.<>
{"title":"Modeling of broken connections faults in CMOS ICs","authors":"M. Favalli, M. Dalpasso, P. Olivo, B. Riccò","doi":"10.1109/EDTC.1994.326882","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326882","url":null,"abstract":"This work presents a fault model to effectively account for broken connections inside CMOS circuits. The proposed model is very general, since it allows one to detect broken connections that cannot be individualized by means of test sequences for stuck-open faults; in addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node. Conditions for the detection of broken connections are derived from electrical considerations and the minimum number of input vectors to be applied to test for a broken connection in a node is determined by graph theory. The model can be used to derive tests and to perform fault simulations independently of the actual layout of the circuit.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115195039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326852
R. Rodríguez-Montañés, J. Figueras
Differences between controllability conditions for I/sub DDQ/ detectability iy in CMOS combinational and sequential circuits with bridging defects are presented. The usual detectability condition for current testability of bridges in combinational circuits is shown to fail for defective sequential circuits. A special class of bridges involving memory elements may change the state memorized in the element becoming current undetectable. Conditions for their occurrence have been investigated and their dependence on transistor size ratio and bridge resistance analyzed. A typical scan cell has been studied and its realistic bridges modifying the memorized state, identified.<>
{"title":"Analysis of bridging defects in sequential CMOS circuits and their current testability","authors":"R. Rodríguez-Montañés, J. Figueras","doi":"10.1109/EDTC.1994.326852","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326852","url":null,"abstract":"Differences between controllability conditions for I/sub DDQ/ detectability iy in CMOS combinational and sequential circuits with bridging defects are presented. The usual detectability condition for current testability of bridges in combinational circuits is shown to fail for defective sequential circuits. A special class of bridges involving memory elements may change the state memorized in the element becoming current undetectable. Conditions for their occurrence have been investigated and their dependence on transistor size ratio and bridge resistance analyzed. A typical scan cell has been studied and its realistic bridges modifying the memorized state, identified.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326857
D. M. Grant, J. V. Meerbergen, P. Lippens
This paper describes an optimization process specific to address generation hardware. By examining a set of pre-defined address sequences at both the word- and bit-levels, a pool of possible hardware solutions may be created from which a global, optimal, bit-level implementation must be found which covers all address sequences. Optimization is completed following a generally iterative method and the resulting architecture may be further improved using generic logic synthesis. The whole process has been implemented in the tool ZIPPO and results for industrially relevant examples are presented.<>
{"title":"Optimization of address generator hardware","authors":"D. M. Grant, J. V. Meerbergen, P. Lippens","doi":"10.1109/EDTC.1994.326857","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326857","url":null,"abstract":"This paper describes an optimization process specific to address generation hardware. By examining a set of pre-defined address sequences at both the word- and bit-levels, a pool of possible hardware solutions may be created from which a global, optimal, bit-level implementation must be found which covers all address sequences. Optimization is completed following a generally iterative method and the resulting architecture may be further improved using generic logic synthesis. The whole process has been implemented in the tool ZIPPO and results for industrially relevant examples are presented.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128306447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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