Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326855
M. Sivaraman, A. Strojwas
Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations/spl minus/caused by the imperfect fabrication process/spl minus/which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance.<>
{"title":"Towards incorporating device parameter variations in timing analysis","authors":"M. Sivaraman, A. Strojwas","doi":"10.1109/EDTC.1994.326855","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326855","url":null,"abstract":"Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations/spl minus/caused by the imperfect fabrication process/spl minus/which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326874
O. Haberl, T. Kropf
In this paper we present the PMSC (Programmable Module Selftest Controller) chip, which realizes an intelligent module test and maintenance (MTM) bus interface for boards as specified in the IEEE 1149.5 standard. Using the standardized "Reset Module with SBIT" command the PMSC chip performs a complete self test of the whole board, which includes the test of all interconnects and all chips. We support chips with a self test capability as well as chips without self test since the PMSC chip allows on-line test pattern generation and test response evaluation.<>
本文提出了PMSC(可编程模块自测控制器)芯片，该芯片实现了IEEE 1149.5标准中主板的智能模块测试与维护(MTM)总线接口。使用标准化的“Reset Module with SBIT”命令，PMSC芯片对整个板进行完整的自检，包括所有互连和所有芯片的测试。我们支持具有自检能力的芯片以及没有自检的芯片，因为PMSC芯片允许在线测试模式生成和测试响应评估。
{"title":"Self testable boards with standard IEEE 1149.5 module test and maintenance (MTM) bus interface","authors":"O. Haberl, T. Kropf","doi":"10.1109/EDTC.1994.326874","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326874","url":null,"abstract":"In this paper we present the PMSC (Programmable Module Selftest Controller) chip, which realizes an intelligent module test and maintenance (MTM) bus interface for boards as specified in the IEEE 1149.5 standard. Using the standardized \"Reset Module with SBIT\" command the PMSC chip performs a complete self test of the whole board, which includes the test of all interconnects and all chips. We support chips with a self test capability as well as chips without self test since the PMSC chip allows on-line test pattern generation and test response evaluation.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326836
D. Gajski, F. Vahid, Sanjiv Narayan
As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. We present a methodology and tool for system-level specification, design and refinement that result in an executable specification for each system component. The specification for each component can then be synthesized into hardware or compiled to software. We highlight advantages of the proposed methodology compared to current practice.<>
{"title":"A system-design methodology: executable-specification refinement","authors":"D. Gajski, F. Vahid, Sanjiv Narayan","doi":"10.1109/EDTC.1994.326836","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326836","url":null,"abstract":"As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. We present a methodology and tool for system-level specification, design and refinement that result in an executable specification for each system component. The specification for each component can then be synthesized into hardware or compiled to software. We highlight advantages of the proposed methodology compared to current practice.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116091546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326863
A. Vuksic, K. Fuchs
A new built-in self testing (BIST) method for the detection of delay faults is proposed. It is shown that all possible pattern pairs can be generated with a MISR using all input combinations. In order to reduce the test pattern set, deterministic delay test generation is used and a minimal set of input vectors is derived via clique covering. Experimental results show that by just using the all-0 and all-1 input vectors, the non-robust path delay fault coverage ranges from 85% to 100%.<>
{"title":"A new BIST approach for delay fault testing","authors":"A. Vuksic, K. Fuchs","doi":"10.1109/EDTC.1994.326863","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326863","url":null,"abstract":"A new built-in self testing (BIST) method for the detection of delay faults is proposed. It is shown that all possible pattern pairs can be generated with a MISR using all input combinations. In order to reduce the test pattern set, deterministic delay test generation is used and a minimal set of input vectors is derived via clique covering. Experimental results show that by just using the all-0 and all-1 input vectors, the non-robust path delay fault coverage ranges from 85% to 100%.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121311292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326795
L. Burgun, N. Dictus, A. Greiner, E. Pradho, C. Sarwary
This paper presents an approach based on ROBDD representation for multilevel logic synthesis. This approach makes it possible to handle very high complexity circuits that cannot be synthesized by the classical factorization algorithms. Two important algorithms are used. The former generates a multilevel expression from an ROBDD. The latter builds a minimal ROBDD from the two ROBDDs representing an incompletely specified Boolean function. This approach is implemented in the logic synthesis software LOGIC developed as part of the ALLIANCE CAD package.<>
{"title":"Multilevel logic synthesis of very high complexity circuits","authors":"L. Burgun, N. Dictus, A. Greiner, E. Pradho, C. Sarwary","doi":"10.1109/EDTC.1994.326795","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326795","url":null,"abstract":"This paper presents an approach based on ROBDD representation for multilevel logic synthesis. This approach makes it possible to handle very high complexity circuits that cannot be synthesized by the classical factorization algorithms. Two important algorithms are used. The former generates a multilevel expression from an ROBDD. The latter builds a minimal ROBDD from the two ROBDDs representing an incompletely specified Boolean function. This approach is implemented in the logic synthesis software LOGIC developed as part of the ALLIANCE CAD package.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123784635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326819
K. Michaels, A. Strojwas
This paper presents a complete variable accuracy device modeling methodology which varies the error tolerances and device model accuracy during the simulation based upon the dynamic state of operation of the circuit and the circuit topology. The number of device model evaluations required and the average device model evaluation time are minimized.<>
{"title":"Variable accuracy device modeling for event-driven circuit simulation","authors":"K. Michaels, A. Strojwas","doi":"10.1109/EDTC.1994.326819","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326819","url":null,"abstract":"This paper presents a complete variable accuracy device modeling methodology which varies the error tolerances and device model accuracy during the simulation based upon the dynamic state of operation of the circuit and the circuit topology. The number of device model evaluations required and the average device model evaluation time are minimized.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124800404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326841
How-Rern Lin, Ching-Lung Chou, Y. Hsu, TingTing Hwang
We consider the transistor sizing problem in a module layout which consists of several rows of automatically generated leaf cells based on a new layout style proposed by Hwang et al. (1991). The sizing is performed in two levels. At the module level, a leaf cell is chosen based on a height slack (usable area) and timing slack. At the cell level, the cell is sized based on a width constraint imposed from the module level. The problem of sizing a cell is formulated as a nonlinear program. The objective is to minimize the difference of actual arrival time and the required time of all output nodes simultaneously. A benchmarking process has been conducted at both cell level and module level. Experiments on a set of cells show that on the average over 25% performance improvement is obtained by using 0.06% more area. Moreover, for a leaf cell with multiple outputs, the sizer can indeed simultaneously make the arrival time of all output nodes close to the required time. Results of a module level experiment show that using height slack the maximum delay of the circuit can be reduced up to 17.7% without area penalty for the example shown.<>
{"title":"Cell height driven transistor sizing in a cell based module design","authors":"How-Rern Lin, Ching-Lung Chou, Y. Hsu, TingTing Hwang","doi":"10.1109/EDTC.1994.326841","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326841","url":null,"abstract":"We consider the transistor sizing problem in a module layout which consists of several rows of automatically generated leaf cells based on a new layout style proposed by Hwang et al. (1991). The sizing is performed in two levels. At the module level, a leaf cell is chosen based on a height slack (usable area) and timing slack. At the cell level, the cell is sized based on a width constraint imposed from the module level. The problem of sizing a cell is formulated as a nonlinear program. The objective is to minimize the difference of actual arrival time and the required time of all output nodes simultaneously. A benchmarking process has been conducted at both cell level and module level. Experiments on a set of cells show that on the average over 25% performance improvement is obtained by using 0.06% more area. Moreover, for a leaf cell with multiple outputs, the sizer can indeed simultaneously make the arrival time of all output nodes close to the required time. Results of a module level experiment show that using height slack the maximum delay of the circuit can be reduced up to 17.7% without area penalty for the example shown.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122375466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326919
Gunnar Bartels, P. M. Kist, Kees Schot, M. Sim
A test harness is a system for testing the reliability of electronic CAD systems (ECADS). Modern ECADS's utilize a framework component for basic services. Since frameworks were originally applied to ECADS's, little is known about the framework requirements for supporting a test harness. Previous work shows that the framework's design data manager can be used. We conclude here that a design flow manager, with slight adaptations, can be used as well. We provide a motivated list of flow requirements, give insight into good and bad features and discuss implementation aspects.<>
{"title":"Flow management requirements of a test harness for testing the reliability of an electronic CAD system","authors":"Gunnar Bartels, P. M. Kist, Kees Schot, M. Sim","doi":"10.1109/EDTC.1994.326919","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326919","url":null,"abstract":"A test harness is a system for testing the reliability of electronic CAD systems (ECADS). Modern ECADS's utilize a framework component for basic services. Since frameworks were originally applied to ECADS's, little is known about the framework requirements for supporting a test harness. Previous work shows that the framework's design data manager can be used. We conclude here that a design flow manager, with slight adaptations, can be used as well. We provide a motivated list of flow requirements, give insight into good and bad features and discuss implementation aspects.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326915
J. Bern, Jordan Gergov, C. Meinel, A. Slobodová
It is shown that Free Binary Decision Diagrams (FBDD's), with respect to a predefined type, provide a canonical representation and allow efficient solutions of the basic tasks in Boolean manipulation in a similar manner to the well-known OBDD's. However, in contrast to OBDD's, the FBDD's allow more succinct representations of Boolean functions. For experimentation we have used an FBDD-package and the types worked with are tree-based. Using different type-creating heuristics, we compare the size of FBDD-representations of some ISCAS benchmarks with the size of their OBDD-representations.<>
{"title":"Boolean manipulation with free BDD's. First experimental results","authors":"J. Bern, Jordan Gergov, C. Meinel, A. Slobodová","doi":"10.1109/EDTC.1994.326915","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326915","url":null,"abstract":"It is shown that Free Binary Decision Diagrams (FBDD's), with respect to a predefined type, provide a canonical representation and allow efficient solutions of the basic tasks in Boolean manipulation in a similar manner to the well-known OBDD's. However, in contrast to OBDD's, the FBDD's allow more succinct representations of Boolean functions. For experimentation we have used an FBDD-package and the types worked with are tree-based. Using different type-creating heuristics, we compare the size of FBDD-representations of some ISCAS benchmarks with the size of their OBDD-representations.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127932768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326880
R. Hahn, Rolf Krieger, B. Becker
One central point of testing is the choice of the fault model and the faults which have to be considered to ensure the correct behaviour of a circuit. The number of faults has a strong influence on the costs which must be paid for in the generation of a test set. For logical fault models this number can be reduced using equivalence relations between faults. Since the complexity of digital circuits is increasing, hierarchical design is becoming more and more important. In this paper, we show that in the case of a hierarchical circuit description often more equivalence relations between faults can be recognized efficiently than in the case of a nonhierarchical description. With respect to the stuck-at fault model, our experiments show that the computation of these equivalence relations can be performed in negligible time and that the number of faults can be reduced considerably.<>
{"title":"A hierarchical approach to fault collapsing","authors":"R. Hahn, Rolf Krieger, B. Becker","doi":"10.1109/EDTC.1994.326880","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326880","url":null,"abstract":"One central point of testing is the choice of the fault model and the faults which have to be considered to ensure the correct behaviour of a circuit. The number of faults has a strong influence on the costs which must be paid for in the generation of a test set. For logical fault models this number can be reduced using equivalence relations between faults. Since the complexity of digital circuits is increasing, hierarchical design is becoming more and more important. In this paper, we show that in the case of a hierarchical circuit description often more equivalence relations between faults can be recognized efficiently than in the case of a nonhierarchical description. With respect to the stuck-at fault model, our experiments show that the computation of these equivalence relations can be performed in negligible time and that the number of faults can be reduced considerably.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126466130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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