Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326890
Sen-Pin Lin, S. Gupta, M. Breuer
The area overhead and performance degradation associated with the hardware used to make a circuit testable using the conventional BILBO methodology can often be excessive. This paper presents a new BILBO-oriented methodology, called Built-In test for Balanced Structure (BIBS), that significantly reduces the number of BILBO registers used in creating a testable circuit, and thus decreases the area overhead and performance degradation. The concept of k-step functionally testable circuits is introduced. When the BIBS methodology is employed, circuits under test are guaranteed to be 1-step functionally testable and thus a high fault coverage can be achieved. A novel test pattern generator design to achieve 1-step functional testability for the BIBS TDM is presented.<>
{"title":"A low cost BIST methodology and associated novel test pattern generator","authors":"Sen-Pin Lin, S. Gupta, M. Breuer","doi":"10.1109/EDTC.1994.326890","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326890","url":null,"abstract":"The area overhead and performance degradation associated with the hardware used to make a circuit testable using the conventional BILBO methodology can often be excessive. This paper presents a new BILBO-oriented methodology, called Built-In test for Balanced Structure (BIBS), that significantly reduces the number of BILBO registers used in creating a testable circuit, and thus decreases the area overhead and performance degradation. The concept of k-step functionally testable circuits is introduced. When the BIBS methodology is employed, circuits under test are guaranteed to be 1-step functionally testable and thus a high fault coverage can be achieved. A novel test pattern generator design to achieve 1-step functional testability for the BIBS TDM is presented.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116557318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326850
E. Isern, J. Figueras
An I/sub DDQ/ testing strategy combined with logical scan-out observation for bridging faults in scan-based sequential circuits is presented. Internal and external zero resistance bridging faults in both the combinational part and the scan path are considered. The testing strategy targets the faults beginning with those harder to detect. Thus, combinational internal shorts and combinational external shorts are targeted first. Remaining external shorts in the scan path are considered later. A standard ATPG for stuck-at faults, adapted to short fault detection, is used. In order to reduce the test application time, the time to apply I/sub DDQ/ test vectors and the time to produce a shift in the scan chain is taken into account. Results of the experimentation on ISCAS'89 circuits show that the strategy provides high quality test sets of reduced size with the highest obtainable coverages for both internal and external shorts.<>
{"title":"Test of bridging faults in scan-based sequential circuits","authors":"E. Isern, J. Figueras","doi":"10.1109/EDTC.1994.326850","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326850","url":null,"abstract":"An I/sub DDQ/ testing strategy combined with logical scan-out observation for bridging faults in scan-based sequential circuits is presented. Internal and external zero resistance bridging faults in both the combinational part and the scan path are considered. The testing strategy targets the faults beginning with those harder to detect. Thus, combinational internal shorts and combinational external shorts are targeted first. Remaining external shorts in the scan path are considered later. A standard ATPG for stuck-at faults, adapted to short fault detection, is used. In order to reduce the test application time, the time to apply I/sub DDQ/ test vectors and the time to produce a shift in the scan chain is taken into account. Results of the experimentation on ISCAS'89 circuits show that the strategy provides high quality test sets of reduced size with the highest obtainable coverages for both internal and external shorts.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132357998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326862
Chih-Ang Chen, S. Gupta
Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs.<>
{"title":"BIST test pattern generators for stuck-open and delay testing","authors":"Chih-Ang Chen, S. Gupta","doi":"10.1109/EDTC.1994.326862","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326862","url":null,"abstract":"Testing for delay and CMOS stuck-open faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) schemes are attractive for such comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs which maximize pattern-pair coverage under any given TPG size constraints. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two-pattern testing. Results derived in this paper provide practical algorithms for the design of optimal TPGs for two-pattern testing. Experiments on some benchmark circuits indicate the TPGs designed using the procedures outlined in this paper provide much higher delay fault coverage than other TPGs.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133252791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326804
A. Abderrahman, B. Kaminska, Y. Savaria
Digital and mixed circuits performance are affected and limited by the simultaneous switching power and ground noise. For accurately selecting the number of power/ground pins to overcome switching noise, it is very important to accurately estimate the worst case simultaneous switching power and ground noise. In this paper we propose a heuristic that helps to estimate this worst case.<>
{"title":"Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits","authors":"A. Abderrahman, B. Kaminska, Y. Savaria","doi":"10.1109/EDTC.1994.326804","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326804","url":null,"abstract":"Digital and mixed circuits performance are affected and limited by the simultaneous switching power and ground noise. For accurately selecting the number of power/ground pins to overcome switching noise, it is very important to accurately estimate the worst case simultaneous switching power and ground noise. In this paper we propose a heuristic that helps to estimate this worst case.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133720054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326861
W. Ke, P. R. Menon
We introduce a new type of delay test set, called a delay-verification test set, which detects the presence of any path delay fault(s) that can affect the timing of the circuit. Such test sets exist even for some circuits that are not completely delay testable. We provide necessary and sufficient conditions for delay-verifiable two-level circuits, which are less stringent than those for complete delay testability. We introduce a new type of test which is not a path delay fault test in the usual sense, but is necessary for verifying the temporal correctness of the circuit under test. A synthesis procedure for delay-verifiable two-level circuits is provided. Experimental data show that delay-verifiable implementations are generally more area-efficient than completely delay testable implementations.<>
{"title":"Synthesis of delay-verifiable two-level circuits","authors":"W. Ke, P. R. Menon","doi":"10.1109/EDTC.1994.326861","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326861","url":null,"abstract":"We introduce a new type of delay test set, called a delay-verification test set, which detects the presence of any path delay fault(s) that can affect the timing of the circuit. Such test sets exist even for some circuits that are not completely delay testable. We provide necessary and sufficient conditions for delay-verifiable two-level circuits, which are less stringent than those for complete delay testability. We introduce a new type of test which is not a path delay fault test in the usual sense, but is necessary for verifying the temporal correctness of the circuit under test. A synthesis procedure for delay-verifiable two-level circuits is provided. Experimental data show that delay-verifiable implementations are generally more area-efficient than completely delay testable implementations.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115719859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326834
M. Edwards, J. Forrest
This paper presents a novel development environment for the design, cosynthesis and performance evaluation of embedded software/hardware systems. System behaviour is defined by a C program, and an interactive profiling tool identifies performance critical regions. The original program is subsequently partitioned into software and hardware modules where a critical region is implemented in custom hardware. The significance of our approach is demonstrated by example systems.<>
{"title":"A development environment for the cosynthesis of embedded software/hardware systems","authors":"M. Edwards, J. Forrest","doi":"10.1109/EDTC.1994.326834","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326834","url":null,"abstract":"This paper presents a novel development environment for the design, cosynthesis and performance evaluation of embedded software/hardware systems. System behaviour is defined by a C program, and an interactive profiling tool identifies performance critical regions. The original program is subsequently partitioned into software and hardware modules where a critical region is implemented in custom hardware. The significance of our approach is demonstrated by example systems.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122124335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326923
Peter Zepter, Thorsten Grötker
The system and architecture design of digital receivers for high to medium throughput communication links and similar signal processing hardware has special characteristics. The algorithm development on the system level is performed using a data flow driven simulation tool. To shorten the turn-around time in the joint optimization of algorithm and architecture we developed the concept of a tool and library support for a smooth direct transition from the untimed system level dynamic data flow specification and simulation to a synchronous timed ASIC implementation using a hardware description language. Multiple and dynamic data rates can be converted. To reuse design knowledge a library of several generic implementations is provided, which should allow to cover various trade-offs for the particular functions. The timing interface of the library allows for introduction of timing and implementation-dependent information in terms of data rates, iteration intervals (i.e. the number of clock cycles between two data items), port related latencies and control conditions (for models with dynamic rates). The system incorporates algorithms for checking whether the system is consistent and deadlock-free as well as the computation of the arrival times for the data items on the edges. The main task in the implementation of the dynamic data flow is the automatic creation of the gated clock or control signal system to enable the correct setting of algorithmic states in the system. Furthermore algorithms for detecting the registers representing the algorithmic states (which are different from pipeline registers when dealing with dynamic subgraphs) and deciding on the feasibility of the implementation have been developed.<>
{"title":"Generating synchronous timed descriptions of digital receivers from dynamic data flow system level configuration","authors":"Peter Zepter, Thorsten Grötker","doi":"10.1109/EDTC.1994.326923","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326923","url":null,"abstract":"The system and architecture design of digital receivers for high to medium throughput communication links and similar signal processing hardware has special characteristics. The algorithm development on the system level is performed using a data flow driven simulation tool. To shorten the turn-around time in the joint optimization of algorithm and architecture we developed the concept of a tool and library support for a smooth direct transition from the untimed system level dynamic data flow specification and simulation to a synchronous timed ASIC implementation using a hardware description language. Multiple and dynamic data rates can be converted. To reuse design knowledge a library of several generic implementations is provided, which should allow to cover various trade-offs for the particular functions. The timing interface of the library allows for introduction of timing and implementation-dependent information in terms of data rates, iteration intervals (i.e. the number of clock cycles between two data items), port related latencies and control conditions (for models with dynamic rates). The system incorporates algorithms for checking whether the system is consistent and deadlock-free as well as the computation of the arrival times for the data items on the edges. The main task in the implementation of the dynamic data flow is the automatic creation of the gated clock or control signal system to enable the correct setting of algorithmic states in the system. Furthermore algorithms for detecting the registers representing the algorithmic states (which are different from pipeline registers when dealing with dynamic subgraphs) and deciding on the feasibility of the implementation have been developed.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124737496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326825
A. Kunzmann, Frank Böhland
In this paper a new algorithm for automatic test pattern generation for finding gate-delay faults will be presented. In contrast to the state-of-the-art approaches the necessary test pattern sequences are generated using the logic function of the circuit to be tested. This enables the usage of both conventional scan flipflops and boundary scan cells, instead of enlarged area-consuming scannable flipflops. Additionally, the test application time can be distinctly reduced since only one test pattern of each test pair has to be loaded into the scan register. Experimental results of the ISCAS-89 benchmark circuits illustrate the efficiency of this new approach.<>
{"title":"Gate-delay fault test with conventional scan-design","authors":"A. Kunzmann, Frank Böhland","doi":"10.1109/EDTC.1994.326825","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326825","url":null,"abstract":"In this paper a new algorithm for automatic test pattern generation for finding gate-delay faults will be presented. In contrast to the state-of-the-art approaches the necessary test pattern sequences are generated using the logic function of the circuit to be tested. This enables the usage of both conventional scan flipflops and boundary scan cells, instead of enlarged area-consuming scannable flipflops. Additionally, the test application time can be distinctly reduced since only one test pattern of each test pair has to be loaded into the scan register. Experimental results of the ISCAS-89 benchmark circuits illustrate the efficiency of this new approach.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326845
H. Esbensen, P. Mazumder
A genetic algorithm (GA) for the Steiner Problem in a graph (SPG) is presented, and its application to global routing of VLSI layouts discussed. In this context the GA's capability to provide several distinct high-quality solutions to a given problem is very advantageous. The performance of the algorithm is compared to that of two heuristics from the literature. The GA is clearly superior in terms of result quality while also being competitive with respect to runtime.<>
{"title":"A genetic algorithm for the Steiner Problem in a graph","authors":"H. Esbensen, P. Mazumder","doi":"10.1109/EDTC.1994.326845","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326845","url":null,"abstract":"A genetic algorithm (GA) for the Steiner Problem in a graph (SPG) is presented, and its application to global routing of VLSI layouts discussed. In this context the GA's capability to provide several distinct high-quality solutions to a given problem is very advantageous. The performance of the algorithm is compared to that of two heuristics from the literature. The GA is clearly superior in terms of result quality while also being competitive with respect to runtime.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133337609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326903
Shan-Hsi Huang, J. Rabaey
Meeting the stringent throughput requirements of high performance DSP applications is a challenging task. Extensive optimization of the computational structure is essential to satisfy these constraints. This paper proposes a new transformational approach for performance optimization. This approach consists of an ordered set of transformations, including algebraic transformations, loop unrolling, and retiming/pipelining, aimed at speeding up both recursive and non-recursive, us well as linear and non-linear applications. Impressive and close to optimal speed-up's have been obtained for a large range of benchmark examples.<>
{"title":"Maximizing the throughput of high performance DSP applications using behavioral transformations","authors":"Shan-Hsi Huang, J. Rabaey","doi":"10.1109/EDTC.1994.326903","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326903","url":null,"abstract":"Meeting the stringent throughput requirements of high performance DSP applications is a challenging task. Extensive optimization of the computational structure is essential to satisfy these constraints. This paper proposes a new transformational approach for performance optimization. This approach consists of an ordered set of transformations, including algebraic transformations, loop unrolling, and retiming/pipelining, aimed at speeding up both recursive and non-recursive, us well as linear and non-linear applications. Impressive and close to optimal speed-up's have been obtained for a large range of benchmark examples.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133795304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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