Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326837
M. Jamoussi, B. Kaminska
In this paper, a new M-testability approach is introduced. M-testability is based on a new Variable Testability Measure (VTM) appropriate in high-level synthesis. It is shown that VTM is a generalization of the C-testability concept which is extended to M-testability to deal with more general arrays such as those of non identical cells or functional primitives in data paths. The elaboration of this concept led to the development of a classified-level approach applied to the data path primitives. Some examples are given to show the practical applicability of the proposed technique in high-level synthesis.<>
{"title":"M-testability: an approach for data-path testability evaluation","authors":"M. Jamoussi, B. Kaminska","doi":"10.1109/EDTC.1994.326837","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326837","url":null,"abstract":"In this paper, a new M-testability approach is introduced. M-testability is based on a new Variable Testability Measure (VTM) appropriate in high-level synthesis. It is shown that VTM is a generalization of the C-testability concept which is extended to M-testability to deal with more general arrays such as those of non identical cells or functional primitives in data paths. The elaboration of this concept led to the development of a classified-level approach applied to the data path primitives. Some examples are given to show the practical applicability of the proposed technique in high-level synthesis.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124118320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326917
M. Flottes, D. Hammad, B. Rouzeyre
The incorporation of an on-line concurrent test method into high level synthesis of data-paths is addressed. Test vectors are propagated through all data-path resources during their idle times from built-in test patterns generators to response collectors. Testing is considered on the behavioral description. From the knowledge of resource idle times, a test flow graph is built up. Synthesis is then performed merging this graph and the normal control/data flow graph.<>
{"title":"Automatic synthesis of BISTed data paths from high level specification","authors":"M. Flottes, D. Hammad, B. Rouzeyre","doi":"10.1109/EDTC.1994.326917","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326917","url":null,"abstract":"The incorporation of an on-line concurrent test method into high level synthesis of data-paths is addressed. Test vectors are propagated through all data-path resources during their idle times from built-in test patterns generators to response collectors. Testing is considered on the behavioral description. From the knowledge of resource idle times, a test flow graph is built up. Synthesis is then performed merging this graph and the normal control/data flow graph.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129102135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326905
T. Michel, R. Leveugle, G. Saucier, R. Doucet, P. Chapier
On-line test mechanisms have been designed for the CPU of a programmable logic controller. Specific devices integrated in an ASIC processor perform control flow checking during both application and system program executions. A prototype has been implemented, demonstrating the very low overhead of the approach. Results of fault injections have then proved the dependability increase at system level.<>
{"title":"Taking advantage of ASICs to improve dependability with very low overheads /spl lsqb/PLC/spl rsqb/","authors":"T. Michel, R. Leveugle, G. Saucier, R. Doucet, P. Chapier","doi":"10.1109/EDTC.1994.326905","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326905","url":null,"abstract":"On-line test mechanisms have been designed for the CPU of a programmable logic controller. Specific devices integrated in an ASIC processor perform control flow checking during both application and system program executions. A prototype has been implemented, demonstrating the very low overhead of the approach. Results of fault injections have then proved the dependability increase at system level.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326853
C. Safinia, R. Leveugle, G. Saucier
High level functional information, available in a circuit specification, can be used to refine timing analysis or modeling. The notion of functional false path is first introduced. Then, the principles of an accurate timing analysis are presented for circuits made up of a controller and a datapath. The approach takes advantage of the circuit hierarchy to reduce the computation complexity and avoids reporting functional false paths.<>
{"title":"Taking advantage of high level functional information to refine timing analysis and timing information","authors":"C. Safinia, R. Leveugle, G. Saucier","doi":"10.1109/EDTC.1994.326853","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326853","url":null,"abstract":"High level functional information, available in a circuit specification, can be used to refine timing analysis or modeling. The notion of functional false path is first introduced. Then, the principles of an accurate timing analysis are presented for circuits made up of a controller and a datapath. The approach takes advantage of the circuit hierarchy to reduce the computation complexity and avoids reporting functional false paths.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127910098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326869
A. Vacher, M. Benkhebbab, A. Guyot, T. Rousseau, A. Skaf
This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.<>
{"title":"A VLSI implementation of parallel fast Fourier transform","authors":"A. Vacher, M. Benkhebbab, A. Guyot, T. Rousseau, A. Skaf","doi":"10.1109/EDTC.1994.326869","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326869","url":null,"abstract":"This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124010691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326838
Hua Xue, C. Di, J. Jess
The electrical behavior of a floating gate MOS transistor is mask-topology-dependent, i.e. floating on different sites of interconnection may result in different fault behavior. In this paper, we present a net-oriented deterministic approach to compute the probability of different open faults on each net, by taking into account the process defect statistics and mask layout data. The open faults causing floating gates are classified into three types, i.e. (1) open causes floating gates of p-channel transistors, (2) open causes floating gates of n-channel transistors, and (3) open causes floating gates of both p-channel transistors and n-channel transistors. For each net the probabilities of floating gate faults (1), (2) and (3) are obtained. The results of the analysis can be used as guidelines for designing more reliable and testable circuits, adopting more accurate fault models, introducing effective testing strategies.<>
{"title":"Probability analysis for CMOS floating gate faults","authors":"Hua Xue, C. Di, J. Jess","doi":"10.1109/EDTC.1994.326838","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326838","url":null,"abstract":"The electrical behavior of a floating gate MOS transistor is mask-topology-dependent, i.e. floating on different sites of interconnection may result in different fault behavior. In this paper, we present a net-oriented deterministic approach to compute the probability of different open faults on each net, by taking into account the process defect statistics and mask layout data. The open faults causing floating gates are classified into three types, i.e. (1) open causes floating gates of p-channel transistors, (2) open causes floating gates of n-channel transistors, and (3) open causes floating gates of both p-channel transistors and n-channel transistors. For each net the probabilities of floating gate faults (1), (2) and (3) are obtained. The results of the analysis can be used as guidelines for designing more reliable and testable circuits, adopting more accurate fault models, introducing effective testing strategies.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131111662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326817
Zhihua Wang, S. W. Director
A novel method for the estimation of yield of integrated circuits based on a two step linear approximation of circuit performance is proposed. By using this method, only one complete circuit simulation is needed for the estimation of yield. A new algorithm for yield optimization is also presented. It is based on the random direction stochastic approximation and does not require the evaluation of yield gradients. Examples are given to demonstrate the efficiency of the algorithm.<>
{"title":"An efficient yield optimization method using a two step linear approximation of circuit performance","authors":"Zhihua Wang, S. W. Director","doi":"10.1109/EDTC.1994.326817","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326817","url":null,"abstract":"A novel method for the estimation of yield of integrated circuits based on a two step linear approximation of circuit performance is proposed. By using this method, only one complete circuit simulation is needed for the estimation of yield. A new algorithm for yield optimization is also presented. It is based on the random direction stochastic approximation and does not require the evaluation of yield gradients. Examples are given to demonstrate the efficiency of the algorithm.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128170398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326891
D. Brasen, G. Saucier
FPGA packages have maximum size constraints much larger than the number of IO pins. The resulting IO bottleneck during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. This cuts more critical timing paths between packages and drastically decreases the circuit operational frequency. In this paper, a bottom-up circuit partitioning method with cone structures is presented. The solution can minimize the delay of critical paths that slow down the circuit without changing the number of partitioned packages.<>
{"title":"FPGA partitioning for critical paths","authors":"D. Brasen, G. Saucier","doi":"10.1109/EDTC.1994.326891","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326891","url":null,"abstract":"FPGA packages have maximum size constraints much larger than the number of IO pins. The resulting IO bottleneck during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. This cuts more critical timing paths between packages and drastically decreases the circuit operational frequency. In this paper, a bottom-up circuit partitioning method with cone structures is presented. The solution can minimize the delay of critical paths that slow down the circuit without changing the number of partitioned packages.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114288456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326813
R. I. Bahar, Hyunwoo Cho, G. Hachtel, E. Macii, F. Somenzi
This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADDs). The procedure we propose, implemented as on extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gate-level representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worst-case primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for low-power consumption.<>
{"title":"Timing analysis of combinational circuits using ADDs","authors":"R. I. Bahar, Hyunwoo Cho, G. Hachtel, E. Macii, F. Somenzi","doi":"10.1109/EDTC.1994.326813","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326813","url":null,"abstract":"This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADDs). The procedure we propose, implemented as on extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gate-level representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worst-case primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for low-power consumption.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326851
M. Sachdev
To ensure the functionality, quality and reliability of digital CMOS ICs, the conventional logic testing and I/sub DDQ/ testing are recognized as absolute test requirements. However, some of the bridging defects in sequential circuits are not detected by I/sub DDQ/. Furthermore, for complex devices, even scan based logic testing can be expensive. In this paper, a new concept of transforming sequential logic into purely combinational logic is described. With the help of the proposed method complete sequential logic is voltage and I/sub DDQ/ tested in four test vectors.<>
{"title":"Transforming sequential logic in digital CMOS ICs for voltage and I/sub DDQ/ testing","authors":"M. Sachdev","doi":"10.1109/EDTC.1994.326851","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326851","url":null,"abstract":"To ensure the functionality, quality and reliability of digital CMOS ICs, the conventional logic testing and I/sub DDQ/ testing are recognized as absolute test requirements. However, some of the bridging defects in sequential circuits are not detected by I/sub DDQ/. Furthermore, for complex devices, even scan based logic testing can be expensive. In this paper, a new concept of transforming sequential logic into purely combinational logic is described. With the help of the proposed method complete sequential logic is voltage and I/sub DDQ/ tested in four test vectors.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128805217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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