Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326848
P. Vanbekbergen, C. Ykman-Couvreur, Bill Lin, H. Man
This paper introduces a new Generalized Signal Transition Graph model for specifying complex mixed asynchronous/synchronous circuits, as found in system-level interfaces. The goal has been to develop extensions that make it possible to model mixed asynchronous/synchronous and arbitration behavior. A number of key extensions have been developed that makes the model much more widely applicable to industrial designs. The extensions include Boolean guards, the introduction of level semantics that make it possible to describe "events" in terms of both signal transitions as well as "signal levels", and the semantic extensions for describing don't care and undefined behavior. The latter extensions make it possible to model synchronous finite state machines using an asynchronous model, hence permitting the specification of mixed asynchronous/synchronous behavior. The proposed Generalized Signal Transition Graph Model is free from the restrictions of the previous models such as liveness, safeness, and free-choice requirements, and permits general Petri-net structures that may include multiple tokens in a place as long as the resulting state graph is bounded and has a consistent state assignment. A key aspect of the generalizations is that all the extensions are defined at the state graph level.<>
{"title":"A generalized signal transition graph model for specification of complex interfaces","authors":"P. Vanbekbergen, C. Ykman-Couvreur, Bill Lin, H. Man","doi":"10.1109/EDTC.1994.326848","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326848","url":null,"abstract":"This paper introduces a new Generalized Signal Transition Graph model for specifying complex mixed asynchronous/synchronous circuits, as found in system-level interfaces. The goal has been to develop extensions that make it possible to model mixed asynchronous/synchronous and arbitration behavior. A number of key extensions have been developed that makes the model much more widely applicable to industrial designs. The extensions include Boolean guards, the introduction of level semantics that make it possible to describe \"events\" in terms of both signal transitions as well as \"signal levels\", and the semantic extensions for describing don't care and undefined behavior. The latter extensions make it possible to model synchronous finite state machines using an asynchronous model, hence permitting the specification of mixed asynchronous/synchronous behavior. The proposed Generalized Signal Transition Graph Model is free from the restrictions of the previous models such as liveness, safeness, and free-choice requirements, and permits general Petri-net structures that may include multiple tokens in a place as long as the resulting state graph is bounded and has a consistent state assignment. A key aspect of the generalizations is that all the extensions are defined at the state graph level.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131712099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326832
B. Rouzeyre, D. Dupont, G. Sagnes
This paper emphasizes on the performance optimization problem of automatically synthesized circuits while respecting area constraints. This optimization is performed at the earliest step of synthesis, i.e. during the scheduling of the behavioral specification of the circuit. It is mainly based on an adequate determination of the type of component which implements each operation in the specification. An algorithm performing concurrently component selection and scheduling is presented. It gives the designer facilities for design-space exploration, i.e. time versus area, since components are taken from a user specified library. The special features of this algorithm are: several component types can implement an operation and one component type can implement several operations; the delays are associated to pairs (component type, operation type); both the usual synchronous control scheme and a control scheme allowing to tune independently the delay of every control step (referred as adjusted control) are discussed.<>
{"title":"Component selection, scheduling and control schemes for high level synthesis","authors":"B. Rouzeyre, D. Dupont, G. Sagnes","doi":"10.1109/EDTC.1994.326832","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326832","url":null,"abstract":"This paper emphasizes on the performance optimization problem of automatically synthesized circuits while respecting area constraints. This optimization is performed at the earliest step of synthesis, i.e. during the scheduling of the behavioral specification of the circuit. It is mainly based on an adequate determination of the type of component which implements each operation in the specification. An algorithm performing concurrently component selection and scheduling is presented. It gives the designer facilities for design-space exploration, i.e. time versus area, since components are taken from a user specified library. The special features of this algorithm are: several component types can implement an operation and one component type can implement several operations; the delays are associated to pairs (component type, operation type); both the usual synchronous control scheme and a control scheme allowing to tune independently the delay of every control step (referred as adjusted control) are discussed.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127582224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326886
Ben Chen, M. Yamazaki, M. Fujita
We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips.<>
{"title":"Bug identification of a real chip design by symbolic model checking","authors":"Ben Chen, M. Yamazaki, M. Fujita","doi":"10.1109/EDTC.1994.326886","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326886","url":null,"abstract":"We show how we have successfully identified the bug of a real chip by using formal verification techniques. Since excessive number of simulation cycles are necessary to debug the chip design, formal verification techniques, specifically CTL symbolic model checking, were adopted to identify the bug. We demonstrate several approaches including abstraction, which make it possible to apply symbolic model checking methods. The methods and ideas reported here are general enough for diagnosing other real chips.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115632976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326800
K.C. Kouakou
Lifetime optimization of some industrial or biological items which can fail under internal or external pertubations are of great interest for researchers in many fields as electronic and computer engineering, medicine, mechanical engineering, railways and many others. Some useful goals of a software called EstiSurv which can be useful in the above fields, are described.<>
{"title":"Software implementation and statistical optimization of some electronic component's lifetime","authors":"K.C. Kouakou","doi":"10.1109/EDTC.1994.326800","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326800","url":null,"abstract":"Lifetime optimization of some industrial or biological items which can fail under internal or external pertubations are of great interest for researchers in many fields as electronic and computer engineering, medicine, mechanical engineering, railways and many others. Some useful goals of a software called EstiSurv which can be useful in the above fields, are described.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114502881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326854
Jürgen Frößl, T. Kropf
In this paper a new formal model is presented which allows the uniform representation of the discrete functional and timing behavior of arbitrary MOS transistor circuits. Algorithms are presented to automatically extract the model from transistor netlists and to transform it into VHDL simulation descriptions. The accuracy of the VHDL simulation is sufficient for a detailed functional and timing analysis of digital circuits, although the runtime is considerably reduced. The model is well suited for formal verification approaches since it is based on formalized timed transition systems.<>
{"title":"A new model to uniformly represent the function and timing of MOS circuits and its application to VHDL simulation","authors":"Jürgen Frößl, T. Kropf","doi":"10.1109/EDTC.1994.326854","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326854","url":null,"abstract":"In this paper a new formal model is presented which allows the uniform representation of the discrete functional and timing behavior of arbitrary MOS transistor circuits. Algorithms are presented to automatically extract the model from transistor netlists and to transform it into VHDL simulation descriptions. The accuracy of the VHDL simulation is sufficient for a detailed functional and timing analysis of digital circuits, although the runtime is considerably reduced. The model is well suited for formal verification approaches since it is based on formalized timed transition systems.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114557833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326839
J. Sousa, F. Gonçalves, João Paulo Teixeira, T. Williams
This paper presents a new model for evaluating the defect level, DL, in VLSI circuits as a function of the yield, Y, and the stuck-at fault coverage, T. It is shown that the observed DL(T) curve can be accurately modeled using non equally probable, realistic faults predicted from defect statistics data and IC layout. The deviation of DL(T) from the one estimated by the Williams-Brown equation is shown, to be caused by two effects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 100% defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-level fault simulation, and the results obtained agree with previously published DL(T) experimental results on actual ICs.<>
{"title":"Fault modeling and defect level projections in digital ICs","authors":"J. Sousa, F. Gonçalves, João Paulo Teixeira, T. Williams","doi":"10.1109/EDTC.1994.326839","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326839","url":null,"abstract":"This paper presents a new model for evaluating the defect level, DL, in VLSI circuits as a function of the yield, Y, and the stuck-at fault coverage, T. It is shown that the observed DL(T) curve can be accurately modeled using non equally probable, realistic faults predicted from defect statistics data and IC layout. The deviation of DL(T) from the one estimated by the Williams-Brown equation is shown, to be caused by two effects. First, the topology of the most likely realistic faults determine their susceptibility, which is typically lower than the stuck-at fault susceptibility. Second, the incompleteness of a given test set and the detection technique (such as static voltage testing) determine a non 100% defect coverage. The suitability of the model was assessed by means of layout fault extraction and switch-level fault simulation, and the results obtained agree with previously published DL(T) experimental results on actual ICs.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124593520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326884
J. Helbig, Peter Kelb
We present an effective method to translate a statechart into an ordered binary decision diagram (OBDD) representation of its transition system. By that it becomes possible to verify a system specified by a statechart by symbolic model checking, one of the most advanced automatic verification techniques. The method exploits the hierarchy in the relevance of information as is implied by the state structure and admits some redundancy to keep the "decoding effort" of each OBDD small. The method is implemented in the ESPRIT project FORMAT, where OBDD based transition systems serve as a common ground to verify specifications in VHDL or (a variant of) statecharts against temporal logic, symbolic timing diagrams, and each other.<>
{"title":"An OBDD-representation of statecharts","authors":"J. Helbig, Peter Kelb","doi":"10.1109/EDTC.1994.326884","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326884","url":null,"abstract":"We present an effective method to translate a statechart into an ordered binary decision diagram (OBDD) representation of its transition system. By that it becomes possible to verify a system specified by a statechart by symbolic model checking, one of the most advanced automatic verification techniques. The method exploits the hierarchy in the relevance of information as is implied by the state structure and admits some redundancy to keep the \"decoding effort\" of each OBDD small. The method is implemented in the ESPRIT project FORMAT, where OBDD based transition systems serve as a common ground to verify specifications in VHDL or (a variant of) statecharts against temporal logic, symbolic timing diagrams, and each other.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125687797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326815
S. Hellebrand, H. Wunderlich
The paper presents a synthesis approach for pipeline-like controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach.<>
{"title":"Synthesis of self-testable controllers","authors":"S. Hellebrand, H. Wunderlich","doi":"10.1109/EDTC.1994.326815","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326815","url":null,"abstract":"The paper presents a synthesis approach for pipeline-like controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal, too. The self-testable structure for a given finite state machine specification is derived from an appropriate realization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine optimal realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132496036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326822
Eamonn Byrne, O. McCarthy, David Lucas, B. Donnellan
A system for optimising analogue circuits is presented. The system "AD-OPT" (Analog Devices OPTimiser) uses numerical simulation and interpolation methods to determine an optimal set of circuit element values and device geometries to meet specific analogue performance requirements. This paper presents an overview of AD-OPT and of its three central modules: the datasheet generator, the database creation module and the optimiser. The paper demonstrates that the increasing speed of work stations and the judicious use of numerical methods, is altering the balance between theoretical and numerical approaches to problem solving.<>
{"title":"An overview of analogue optimisation using \"AD-OPT\"","authors":"Eamonn Byrne, O. McCarthy, David Lucas, B. Donnellan","doi":"10.1109/EDTC.1994.326822","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326822","url":null,"abstract":"A system for optimising analogue circuits is presented. The system \"AD-OPT\" (Analog Devices OPTimiser) uses numerical simulation and interpolation methods to determine an optimal set of circuit element values and device geometries to meet specific analogue performance requirements. This paper presents an overview of AD-OPT and of its three central modules: the datasheet generator, the database creation module and the optimiser. The paper demonstrates that the increasing speed of work stations and the judicious use of numerical methods, is altering the balance between theoretical and numerical approaches to problem solving.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132020433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326894
Hitesh Ajuha, P. R. Menon
This paper presents a new algorithm for reducing the delay of combinational circuits by structural modifications. Delay reduction is obtained by substituting delay-inefficient segments of the longest path in the circuit, by faster segments which perform the same function. Experimental results with the ISCAS85 benchmark circuits showed good delay reduction with only moderate area increase. Extension of this method for delay reduction of technology-mapped circuits appears to be feasible.<>
{"title":"Delay reduction by segment substitution","authors":"Hitesh Ajuha, P. R. Menon","doi":"10.1109/EDTC.1994.326894","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326894","url":null,"abstract":"This paper presents a new algorithm for reducing the delay of combinational circuits by structural modifications. Delay reduction is obtained by substituting delay-inefficient segments of the longest path in the circuit, by faster segments which perform the same function. Experimental results with the ISCAS85 benchmark circuits showed good delay reduction with only moderate area increase. Extension of this method for delay reduction of technology-mapped circuits appears to be feasible.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125401116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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