Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326899
F. Fummi, D. Sciuto, M. Serra
In this paper we present an analysis of the coverage of delay faults in sequential circuits by a functional test pattern generator. Relationships are investigated between a functional fault model and delay faults, with correlations to the stuck-at fault coverage. Undetected faults are identified and an algorithm to improve the delay fault coverage is proposed. The final approach generates a functional test for sequential circuits with optimization and reaches complete coverage of detectable delay faults with short tests.<>
{"title":"A functional approach to delay faults test generation for sequential circuits","authors":"F. Fummi, D. Sciuto, M. Serra","doi":"10.1109/EDTC.1994.326899","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326899","url":null,"abstract":"In this paper we present an analysis of the coverage of delay faults in sequential circuits by a functional test pattern generator. Relationships are investigated between a functional fault model and delay faults, with correlations to the stuck-at fault coverage. Undetected faults are identified and an algorithm to improve the delay fault coverage is proposed. The final approach generates a functional test for sequential circuits with optimization and reaches complete coverage of detectable delay faults with short tests.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326812
B. Wurth, N. Wehn
A new exact technique is presented to calculate the maximal Boolean relation for an arbitrary subcircuit in a multi-level logic circuit. The new technique significantly reduces the memory required for BDD-based Boolean relation calculation. It therefore permits the calculation of Boolean relations for much more complex circuits than was previously possible. The efficiency of the technique is demonstrated on various benchmark circuits. An application to multi-level logic optimization is shown.<>
{"title":"Efficient calculation of Boolean relations for multi-level logic optimization","authors":"B. Wurth, N. Wehn","doi":"10.1109/EDTC.1994.326812","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326812","url":null,"abstract":"A new exact technique is presented to calculate the maximal Boolean relation for an arbitrary subcircuit in a multi-level logic circuit. The new technique significantly reduces the memory required for BDD-based Boolean relation calculation. It therefore permits the calculation of Boolean relations for much more complex circuits than was previously possible. The efficiency of the technique is demonstrated on various benchmark circuits. An application to multi-level logic optimization is shown.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121299187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326823
Vincent Moser, P. Nussbaum, H. Amann, L. Astier, F. Pellandini
In order to master the growing complexity of analogue electronic systems, modelling and simulation of analogue hardware at various levels is absolutely necessary. This paper presents an original modelling method based on the graphical description of analogue electronic functional blocks. This method is intended to be automated and integrated into a design framework: specialists create behavioural models of existing functional blocks, that can then be used through high-level selection and specification. Applications of behavioural modelling are discussed.<>
{"title":"A graphical approach to analogue behavioural modelling","authors":"Vincent Moser, P. Nussbaum, H. Amann, L. Astier, F. Pellandini","doi":"10.1109/EDTC.1994.326823","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326823","url":null,"abstract":"In order to master the growing complexity of analogue electronic systems, modelling and simulation of analogue hardware at various levels is absolutely necessary. This paper presents an original modelling method based on the graphical description of analogue electronic functional blocks. This method is intended to be automated and integrated into a design framework: specialists create behavioural models of existing functional blocks, that can then be used through high-level selection and specification. Applications of behavioural modelling are discussed.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122594146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326864
Tsung-Yi Wu, Tzu-Chieh Tien, A. Wu, Y. Lin
We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms/spl minus/edge-triggered and level-sensitive/spl minus/for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.<>
{"title":"A synthesis method for mixed synchronous/asynchronous behavior","authors":"Tsung-Yi Wu, Tzu-Chieh Tien, A. Wu, Y. Lin","doi":"10.1109/EDTC.1994.326864","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326864","url":null,"abstract":"We propose a method for synthesizing from a behavioral description in a hardware description language. The description provides two mechanisms/spl minus/edge-triggered and level-sensitive/spl minus/for process synchronization and interface designs, which characterize most control-dominated circuits. They are usually asynchronous with the system clock. Conventional control-step-based, scheduling-and-allocation approaches for high-level synthesis are implicitly synchronous and, therefore, cannot correctly produce a structure that exhibits the exact (timing) behavior in the presence of such asynchrony. We construct first a mixed synchronous/asynchronous state graph to capture the described behavior. Then, according to a set of rules, our algorithm transforms the graph into a completely synchronous one, from which synthesis to structure has been proven easy. Simulation of a number of circuits has confirmed that the synthesized structures exhibit identical behavior (in terms of both functionality and timing) as the original description.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123774486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326814
Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu
This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.<>
{"title":"A stepwise refinement data path synthesis procedure for easy testability","authors":"Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu","doi":"10.1109/EDTC.1994.326814","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326814","url":null,"abstract":"This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126768502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326895
D. Gevaert, J. Vanneuville, J. Nedved, J. Sevenhans
This paper describes the design and testing of a 1-bit A/D converter based on the sigma-delta modulation principle. Unlike the conventional realisations using the switched capacitor approach, the current switching technique uses the current level as a variable. In order to check the feasibility and advantages of this technique, a first order 1-bit A/D converter and a second order 1-bit A/D converter were designed. In the first order 1-bit A/D converter a time-continuous current-integrator is used as filter. The circuit has been designed realised and tested. In the second order 1-bit A/D converter the filter is based on the analog sampling and processing of a current signal. The second order filter is implemented with class AB switched current memory cells. The design has been simulated and processed in ES2 1.5 /spl mu/m CMOS technology.<>
{"title":"Switched current sigma-delta A/D converter for a CMOS subscriber line analog front end","authors":"D. Gevaert, J. Vanneuville, J. Nedved, J. Sevenhans","doi":"10.1109/EDTC.1994.326895","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326895","url":null,"abstract":"This paper describes the design and testing of a 1-bit A/D converter based on the sigma-delta modulation principle. Unlike the conventional realisations using the switched capacitor approach, the current switching technique uses the current level as a variable. In order to check the feasibility and advantages of this technique, a first order 1-bit A/D converter and a second order 1-bit A/D converter were designed. In the first order 1-bit A/D converter a time-continuous current-integrator is used as filter. The circuit has been designed realised and tested. In the second order 1-bit A/D converter the filter is based on the analog sampling and processing of a current signal. The second order filter is implemented with class AB switched current memory cells. The design has been simulated and processed in ES2 1.5 /spl mu/m CMOS technology.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125255586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326893
B. Rohfleisch, F. Brglez
This paper introduces the concept of a permissible bridge and a permissible bridge pair. A bridge is a logic node with two inputs and one output. A bridge or a bridge pair are called permissible if they can be inserted into a Boolean network without changing its behavior at primary outputs. There are a total of 255 types of bridges that can be considered between any pair of wires in the network. We discuss a subset of such bridges and present three theorems related to permissible bridges for pairwise detectability, distinguishability and conditional equivalence. Experimental results show that relatively many bridges are permissible in each circuit. In this paper, we exploit the conditional equivalence of wire pairs and show that even after technology mapping, we can significantly reduce the active area as well as the wiring of many designs.<>
{"title":"Introduction of permissible bridges with application to logic optimization after technology mapping","authors":"B. Rohfleisch, F. Brglez","doi":"10.1109/EDTC.1994.326893","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326893","url":null,"abstract":"This paper introduces the concept of a permissible bridge and a permissible bridge pair. A bridge is a logic node with two inputs and one output. A bridge or a bridge pair are called permissible if they can be inserted into a Boolean network without changing its behavior at primary outputs. There are a total of 255 types of bridges that can be considered between any pair of wires in the network. We discuss a subset of such bridges and present three theorems related to permissible bridges for pairwise detectability, distinguishability and conditional equivalence. Experimental results show that relatively many bridges are permissible in each circuit. In this paper, we exploit the conditional equivalence of wire pairs and show that even after technology mapping, we can significantly reduce the active area as well as the wiring of many designs.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127321881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326797
A. V. Goor, Y. Zorian, I. Schanstra
First-In-First-Out (FTFO) memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One way to implement a FIFO is to use a dual-port SRAM memory with a ring-address mechanism consisting of an n-bit shift register (n is the number of words in the FIFO). This saves the address decoder circuitry and allows for higher speed operation, which makes this type of FIFO very popular, especially for embedded applications. The well-known functional tests for SRAMs cannot be applied to FIFOs, because of their built-in access restrictions. Functional fault models and functional tests for ring-address SRAM-type FIFOs have not been documented before; this paper aims at filling in this gap. It introduces functional fault models and presents a set of tests for ring-address SRAM-type FIFOs.<>
{"title":"Functional tests for ring-address SRAM-type FIFOs","authors":"A. V. Goor, Y. Zorian, I. Schanstra","doi":"10.1109/EDTC.1994.326797","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326797","url":null,"abstract":"First-In-First-Out (FTFO) memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One way to implement a FIFO is to use a dual-port SRAM memory with a ring-address mechanism consisting of an n-bit shift register (n is the number of words in the FIFO). This saves the address decoder circuitry and allows for higher speed operation, which makes this type of FIFO very popular, especially for embedded applications. The well-known functional tests for SRAMs cannot be applied to FIFOs, because of their built-in access restrictions. Functional fault models and functional tests for ring-address SRAM-type FIFOs have not been documented before; this paper aims at filling in this gap. It introduces functional fault models and presents a set of tests for ring-address SRAM-type FIFOs.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133025623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326816
M. Nicolaidis, H. Bederr
In this paper we present efficient self checking implementations for multiply and divide arrays. These implementations are strongly fault secure or totally self-checking for a comprehensive fault model which includes stuck-at, stuck-on and stuck-open faults. They are compatible with data paths checked by the parity code (i.e. no code translators are needed), so that the self checking implementation of the whole data path is simplified.<>
{"title":"Efficient implementations of self-checking multiply and divide arrays","authors":"M. Nicolaidis, H. Bederr","doi":"10.1109/EDTC.1994.326816","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326816","url":null,"abstract":"In this paper we present efficient self checking implementations for multiply and divide arrays. These implementations are strongly fault secure or totally self-checking for a comprehensive fault model which includes stuck-at, stuck-on and stuck-open faults. They are compatible with data paths checked by the parity code (i.e. no code translators are needed), so that the self checking implementation of the whole data path is simplified.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114081169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326847
Franz Korf, R. Schlör
Presents a novel method for controller synthesis out of high-level interface specifications. Since the approach uses a novel partitioning technique and exploits structural properties of the synthesis input, the authors reduce the complexity of the synthesis process and the size of the synthesis output drastically in comparison with synthesis tools, which do not exploit structural properties of the synthesis input. The approach is demonstrated on typical examples.<>
{"title":"Interface controller synthesis from requirement specifications","authors":"Franz Korf, R. Schlör","doi":"10.1109/EDTC.1994.326847","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326847","url":null,"abstract":"Presents a novel method for controller synthesis out of high-level interface specifications. Since the approach uses a novel partitioning technique and exploits structural properties of the synthesis input, the authors reduce the complexity of the synthesis process and the size of the synthesis output drastically in comparison with synthesis tools, which do not exploit structural properties of the synthesis input. The approach is demonstrated on typical examples.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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