Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326883
A. Zemva, F. Brglez, K. Kozminski, B. Zajc
This paper introduces a functionality fault model and demonstrates its feasibility and advantages. In current designs, the fanin of logic modules implemented in CMOS standard cell, mask-programmable, or field-programmable gate array technology, rarely exceeds 4 on the average. A functionality fault model, based on complete enumeration of the truth table of each logic module, is thus entirely feasible and enhances the quality of the test significantly. Tests based on this model provide complete coverage of module's behavior, interior faults as well as input stuck-at and bridging faults of any multiplicity/spl minus/reducing the need for technology and implementation-specific fault models, The paper also introducer, techniques that lead to efficient implementation of a prototype test generation system and demonstrates its application not only to generate high quality test patterns but also to generate functionality don't cares that can optimize logic and wiring even after mapping a design into a given technology.<>
{"title":"A functionality fault model: feasibility and applications","authors":"A. Zemva, F. Brglez, K. Kozminski, B. Zajc","doi":"10.1109/EDTC.1994.326883","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326883","url":null,"abstract":"This paper introduces a functionality fault model and demonstrates its feasibility and advantages. In current designs, the fanin of logic modules implemented in CMOS standard cell, mask-programmable, or field-programmable gate array technology, rarely exceeds 4 on the average. A functionality fault model, based on complete enumeration of the truth table of each logic module, is thus entirely feasible and enhances the quality of the test significantly. Tests based on this model provide complete coverage of module's behavior, interior faults as well as input stuck-at and bridging faults of any multiplicity/spl minus/reducing the need for technology and implementation-specific fault models, The paper also introducer, techniques that lead to efficient implementation of a prototype test generation system and demonstrates its application not only to generate high quality test patterns but also to generate functionality don't cares that can optimize logic and wiring even after mapping a design into a given technology.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116662797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326902
C. Liem, T. C. May, P. Paulin
The increasing use of digital signal processors (DSPs) and application specific instruction-set processors (ASIPs) has put a strain on the perceived mature state of compiler technology. The presence of custom hardware for application-specific needs has introduced instruction types which are unfamiliar to the capabilities of traditional compilers. Thus, these traditional techniques can lead to inefficient and sparsely compacted machine microcode. In this paper, we introduce a novel instruction-set matching and selection methodology, based upon a rich representation useful for DSP and mixed control-oriented applications. This representation shows explicit behaviour that references architecture resource classes. This allows a wide range of instructions types to be captured in a pattern set. The pattern set has been organized in a manner such that matching is extremely efficient and retargeting to architectures with new instruction sets is well defined. The matching and selection algorithms have been implemented in a retargetable code generation system called CodeSyn.<>
{"title":"Instruction-set matching and selection for DSP and ASIP code generation","authors":"C. Liem, T. C. May, P. Paulin","doi":"10.1109/EDTC.1994.326902","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326902","url":null,"abstract":"The increasing use of digital signal processors (DSPs) and application specific instruction-set processors (ASIPs) has put a strain on the perceived mature state of compiler technology. The presence of custom hardware for application-specific needs has introduced instruction types which are unfamiliar to the capabilities of traditional compilers. Thus, these traditional techniques can lead to inefficient and sparsely compacted machine microcode. In this paper, we introduce a novel instruction-set matching and selection methodology, based upon a rich representation useful for DSP and mixed control-oriented applications. This representation shows explicit behaviour that references architecture resource classes. This allows a wide range of instructions types to be captured in a pattern set. The pattern set has been organized in a manner such that matching is extremely efficient and retargeting to architectures with new instruction sets is well defined. The matching and selection algorithms have been implemented in a retargetable code generation system called CodeSyn.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130038779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326840
B. A. McCoy, G. Robins
An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e. it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e. where cycles are admissible). We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon. Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters. Finally, we observe that non-tree routing also significantly reduces signal skew.<>
{"title":"Non-tree routing","authors":"B. A. McCoy, G. Robins","doi":"10.1109/EDTC.1994.326840","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326840","url":null,"abstract":"An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e. it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e. where cycles are admissible). We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon. Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters. Finally, we observe that non-tree routing also significantly reduces signal skew.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125379956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326918
M. Straube, W. Wilkes, G. Schlageter
CAD frameworks allow to integrate various CAD tools into an integrated design environment. Such a design environment will give the designer more freedom in organizing his design process and he may follow more than only one predefined design path. This paper introduces a design consulting system which supports the designer in performing this additional task of organizing his design process. The system follows a distributed approach: several expert systems evaluate a given design situation on the basis of their local knowledge, and their results are combined into a common proposal as to how to perform the next design steps. The paper describes the underlying concepts and the implementation design of the design consultant prototype HANDICAP.<>
{"title":"HANDICAP/spl minus/a system for design consulting","authors":"M. Straube, W. Wilkes, G. Schlageter","doi":"10.1109/EDTC.1994.326918","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326918","url":null,"abstract":"CAD frameworks allow to integrate various CAD tools into an integrated design environment. Such a design environment will give the designer more freedom in organizing his design process and he may follow more than only one predefined design path. This paper introduces a design consulting system which supports the designer in performing this additional task of organizing his design process. The system follows a distributed approach: several expert systems evaluate a given design situation on the basis of their local knowledge, and their results are combined into a common proposal as to how to perform the next design steps. The paper describes the underlying concepts and the implementation design of the design consultant prototype HANDICAP.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326860
Sying-Jyan Wang
We present a synthesis procedure for easily testable sequential machines. Testing cost of circuits synthesized from this procedure is reduced, while the added hardware overhead is negligible. The procedure begins with a modification of a state transition graph of a finite state machine (FSM); eventually an easily testable circuit that behaves like the original FSM is synthesized. This result can be combined with previous researches on fully testable sequential circuits to synthesize fully and easily testable sequential machines.<>
{"title":"Synthesis of sequential machines with reduced testing cost","authors":"Sying-Jyan Wang","doi":"10.1109/EDTC.1994.326860","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326860","url":null,"abstract":"We present a synthesis procedure for easily testable sequential machines. Testing cost of circuits synthesized from this procedure is reduced, while the added hardware overhead is negligible. The procedure begins with a modification of a state transition graph of a finite state machine (FSM); eventually an easily testable circuit that behaves like the original FSM is synthesized. This result can be combined with previous researches on fully testable sequential circuits to synthesize fully and easily testable sequential machines.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122528359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326826
D. Dumas, P. Girard, C. Landrault, S. Pravossoudovitch
Delay fault testing has been an active research topic in the last ten years. Recently proposed methods try to move the sampling time of the circuit outputs during testing to produce better fault coverages than that obtained by using a fixed observation time method. In the same way, the authors propose to use such a testing scheme to improve delay fault diagnosis when compared to methods based on fixed output sampling times. The timing analysis which gives the output observation times applied during the test is first described in this paper. Next, the authors present the diagnosis method they implemented with the new testing scheme. Finally, results showing the effectiveness of a variable sampling time strategy for delay fault diagnosis are given.<>
{"title":"Effectiveness of a variable sampling time strategy for delay fault diagnosis","authors":"D. Dumas, P. Girard, C. Landrault, S. Pravossoudovitch","doi":"10.1109/EDTC.1994.326826","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326826","url":null,"abstract":"Delay fault testing has been an active research topic in the last ten years. Recently proposed methods try to move the sampling time of the circuit outputs during testing to produce better fault coverages than that obtained by using a fixed observation time method. In the same way, the authors propose to use such a testing scheme to improve delay fault diagnosis when compared to methods based on fixed output sampling times. The timing analysis which gives the output observation times applied during the test is first described in this paper. Next, the authors present the diagnosis method they implemented with the new testing scheme. Finally, results showing the effectiveness of a variable sampling time strategy for delay fault diagnosis are given.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122712426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326872
M. Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt
The monitoring of power supply current is presented for detecting manufacturing defects in printed circuit boards. Simple and inexpensive test equipment consisting of PC and interface card has been developed to support current monitoring by utilizing IEEE 1149.1 standard test architecture.<>
{"title":"Boundary scan testing combined with power supply current monitoring","authors":"M. Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt","doi":"10.1109/EDTC.1994.326872","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326872","url":null,"abstract":"The monitoring of power supply current is presented for detecting manufacturing defects in printed circuit boards. Simple and inexpensive test equipment consisting of PC and interface card has been developed to support current monitoring by utilizing IEEE 1149.1 standard test architecture.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124983699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326828
Meng Lin, Jwu-E Chen, Chung-Len Lee
For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<>
{"title":"TRANS: a fast and memory-efficient path delay fault simulator","authors":"Meng Lin, Jwu-E Chen, Chung-Len Lee","doi":"10.1109/EDTC.1994.326828","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326828","url":null,"abstract":"For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"82 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326843
Yu-Liang Wu, M. Marek-Sadowska
In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<>
{"title":"An efficient router for 2-D field programmable gate array","authors":"Yu-Liang Wu, M. Marek-Sadowska","doi":"10.1109/EDTC.1994.326843","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326843","url":null,"abstract":"In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115113697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326859
N. D. Holmes, D. Gajski
In this paper, we present a new algorithm for analyzing performance/cost tradeoffs in interactive synthesis of DSP algorithms. Our algorithm handles both memories with different access times and pipelined units with different numbers of stages. The output is a shape function illustrating the performance vs. cost tradeoff. We have tested this algorithm on several benchmarks including an FIR filter and a robot kinematics example. Results show that the average difference in cost, as compared to manual designs, is 0.41%, while the average performance difference is 4.90% without memory access times and 0.77% with memory access times.<>
{"title":"An algorithm for generation of behavioral shape functions","authors":"N. D. Holmes, D. Gajski","doi":"10.1109/EDTC.1994.326859","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326859","url":null,"abstract":"In this paper, we present a new algorithm for analyzing performance/cost tradeoffs in interactive synthesis of DSP algorithms. Our algorithm handles both memories with different access times and pipelined units with different numbers of stages. The output is a shape function illustrating the performance vs. cost tradeoff. We have tested this algorithm on several benchmarks including an FIR filter and a robot kinematics example. Results show that the average difference in cost, as compared to manual designs, is 0.41%, while the average performance difference is 4.90% without memory access times and 0.77% with memory access times.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126347574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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