Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326900
S. Gai, P. Montessoro, M. Reorda
The paper describes a new approach to the fault simulation of synchronous sequential circuits. Its novelty comes from combining the event-driven compiled-code simulation technique proposed by H. K. Lee and D. S. Ha (1992) with the single fault propagation fault-parallel fault simulation algorithm used by F. Maamari and J. Rajski (1988). Our approach is particularly suited for those applications requiring the fault simulation of very high numbers of input patterns, like signature computation or fault dictionary construction. A fault simulator named TORSIM has been written to verify the effectiveness of the approach. The results we present show an average speed-up in terms of CPU time of more than one order of magnitude with respect to the ones reported by Maamari and Rajski.<>
提出了一种同步时序电路故障仿真的新方法。它的新颖之处是将H. K. Lee和D. S. Ha(1992)提出的事件驱动的编译代码模拟技术与F. Maamari和J. Rajski(1988)使用的单故障传播故障-并行故障模拟算法相结合。我们的方法特别适合那些需要大量输入模式的故障模拟的应用程序，如签名计算或故障字典构造。为验证该方法的有效性，编写了故障模拟器TORSIM。我们给出的结果显示，与Maamari和Rajski报告的结果相比，CPU时间的平均加速幅度超过了一个数量级。
{"title":"TORSIM: An efficient fault simulator for synchronous sequential circuits","authors":"S. Gai, P. Montessoro, M. Reorda","doi":"10.1109/EDTC.1994.326900","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326900","url":null,"abstract":"The paper describes a new approach to the fault simulation of synchronous sequential circuits. Its novelty comes from combining the event-driven compiled-code simulation technique proposed by H. K. Lee and D. S. Ha (1992) with the single fault propagation fault-parallel fault simulation algorithm used by F. Maamari and J. Rajski (1988). Our approach is particularly suited for those applications requiring the fault simulation of very high numbers of input patterns, like signature computation or fault dictionary construction. A fault simulator named TORSIM has been written to verify the effectiveness of the approach. The results we present show an average speed-up in terms of CPU time of more than one order of magnitude with respect to the ones reported by Maamari and Rajski.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326840
B. A. McCoy, G. Robins
An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e. it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e. where cycles are admissible). We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon. Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters. Finally, we observe that non-tree routing also significantly reduces signal skew.<>
{"title":"Non-tree routing","authors":"B. A. McCoy, G. Robins","doi":"10.1109/EDTC.1994.326840","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326840","url":null,"abstract":"An implicit premise of existing routing methods is that the routing topology must correspond to a tree (i.e. it does not contain cycles). In this paper we investigate the consequences of abandoning this basic axiom, and instead allow routing topologies that correspond to arbitrary graphs (i.e. where cycles are admissible). We show that adding extra wires to an existing routing tree can often significantly improve signal propagation delay by exploiting a tradeoff between wire capacitance and resistance, and we propose a new routing algorithm based on this phenomenon. Using SPICE to determine the efficacy of our methods, we obtain dramatic results: for example, the judicious addition of a few extra wires to an existing Steiner routing reduces the signal propagation delay by an average of up to 62%, with relatively modest total wirelength increase, depending on net size and the technology parameters. Finally, we observe that non-tree routing also significantly reduces signal skew.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125379956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326918
M. Straube, W. Wilkes, G. Schlageter
CAD frameworks allow to integrate various CAD tools into an integrated design environment. Such a design environment will give the designer more freedom in organizing his design process and he may follow more than only one predefined design path. This paper introduces a design consulting system which supports the designer in performing this additional task of organizing his design process. The system follows a distributed approach: several expert systems evaluate a given design situation on the basis of their local knowledge, and their results are combined into a common proposal as to how to perform the next design steps. The paper describes the underlying concepts and the implementation design of the design consultant prototype HANDICAP.<>
{"title":"HANDICAP/spl minus/a system for design consulting","authors":"M. Straube, W. Wilkes, G. Schlageter","doi":"10.1109/EDTC.1994.326918","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326918","url":null,"abstract":"CAD frameworks allow to integrate various CAD tools into an integrated design environment. Such a design environment will give the designer more freedom in organizing his design process and he may follow more than only one predefined design path. This paper introduces a design consulting system which supports the designer in performing this additional task of organizing his design process. The system follows a distributed approach: several expert systems evaluate a given design situation on the basis of their local knowledge, and their results are combined into a common proposal as to how to perform the next design steps. The paper describes the underlying concepts and the implementation design of the design consultant prototype HANDICAP.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326860
Sying-Jyan Wang
We present a synthesis procedure for easily testable sequential machines. Testing cost of circuits synthesized from this procedure is reduced, while the added hardware overhead is negligible. The procedure begins with a modification of a state transition graph of a finite state machine (FSM); eventually an easily testable circuit that behaves like the original FSM is synthesized. This result can be combined with previous researches on fully testable sequential circuits to synthesize fully and easily testable sequential machines.<>
{"title":"Synthesis of sequential machines with reduced testing cost","authors":"Sying-Jyan Wang","doi":"10.1109/EDTC.1994.326860","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326860","url":null,"abstract":"We present a synthesis procedure for easily testable sequential machines. Testing cost of circuits synthesized from this procedure is reduced, while the added hardware overhead is negligible. The procedure begins with a modification of a state transition graph of a finite state machine (FSM); eventually an easily testable circuit that behaves like the original FSM is synthesized. This result can be combined with previous researches on fully testable sequential circuits to synthesize fully and easily testable sequential machines.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122528359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326826
D. Dumas, P. Girard, C. Landrault, S. Pravossoudovitch
Delay fault testing has been an active research topic in the last ten years. Recently proposed methods try to move the sampling time of the circuit outputs during testing to produce better fault coverages than that obtained by using a fixed observation time method. In the same way, the authors propose to use such a testing scheme to improve delay fault diagnosis when compared to methods based on fixed output sampling times. The timing analysis which gives the output observation times applied during the test is first described in this paper. Next, the authors present the diagnosis method they implemented with the new testing scheme. Finally, results showing the effectiveness of a variable sampling time strategy for delay fault diagnosis are given.<>
{"title":"Effectiveness of a variable sampling time strategy for delay fault diagnosis","authors":"D. Dumas, P. Girard, C. Landrault, S. Pravossoudovitch","doi":"10.1109/EDTC.1994.326826","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326826","url":null,"abstract":"Delay fault testing has been an active research topic in the last ten years. Recently proposed methods try to move the sampling time of the circuit outputs during testing to produce better fault coverages than that obtained by using a fixed observation time method. In the same way, the authors propose to use such a testing scheme to improve delay fault diagnosis when compared to methods based on fixed output sampling times. The timing analysis which gives the output observation times applied during the test is first described in this paper. Next, the authors present the diagnosis method they implemented with the new testing scheme. Finally, results showing the effectiveness of a variable sampling time strategy for delay fault diagnosis are given.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122712426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326794
S. Banerjee, R. Roy, S. Chakradhar, D. Pradhan
We present a method of transforming a functionally uninitializable signal transition graph (STG) into a functionally initializable STG. The design of a trigger module is described to illustrate the transformations.<>
{"title":"Signal transition graph transformations for initializability","authors":"S. Banerjee, R. Roy, S. Chakradhar, D. Pradhan","doi":"10.1109/EDTC.1994.326794","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326794","url":null,"abstract":"We present a method of transforming a functionally uninitializable signal transition graph (STG) into a functionally initializable STG. The design of a trigger module is described to illustrate the transformations.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121078516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326843
Yu-Liang Wu, M. Marek-Sadowska
In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<>
{"title":"An efficient router for 2-D field programmable gate array","authors":"Yu-Liang Wu, M. Marek-Sadowska","doi":"10.1109/EDTC.1994.326843","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326843","url":null,"abstract":"In this paper, we analyze the traditional 2-step global/detailed routing scheme. We propose a bin-packing heuristic based greedy 2-D router that can effectively and stably produce good results in both minimizing routing length and number of tracks needed to complete routing. On the tested MCNC benchmarks, our router resulted 17% less total tracks compared to the best known results of 2-step routers. Our one-step router is linear in both CPU time and run-time memory which suggests its particular suitability for very large circuits.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115113697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326828
Meng Lin, Jwu-E Chen, Chung-Len Lee
For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<>
{"title":"TRANS: a fast and memory-efficient path delay fault simulator","authors":"Meng Lin, Jwu-E Chen, Chung-Len Lee","doi":"10.1109/EDTC.1994.326828","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326828","url":null,"abstract":"For path fault testing, a simulator may suffer from handling an enormous number of paths for their representation and simulation. This paper proposes a fast and memory-efficient path delay fault simulator TRANS. Applied to the ISCAS benchmark circuits, TRANS runs one million patterns within 2.5 hours and 2.2 mega-bytes for each circuit, except for c6288. Comparing the experimental results with those of DAC'89, TRANS achieves 85 times the gain of memory-speed product.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"82 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326859
N. D. Holmes, D. Gajski
In this paper, we present a new algorithm for analyzing performance/cost tradeoffs in interactive synthesis of DSP algorithms. Our algorithm handles both memories with different access times and pipelined units with different numbers of stages. The output is a shape function illustrating the performance vs. cost tradeoff. We have tested this algorithm on several benchmarks including an FIR filter and a robot kinematics example. Results show that the average difference in cost, as compared to manual designs, is 0.41%, while the average performance difference is 4.90% without memory access times and 0.77% with memory access times.<>
{"title":"An algorithm for generation of behavioral shape functions","authors":"N. D. Holmes, D. Gajski","doi":"10.1109/EDTC.1994.326859","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326859","url":null,"abstract":"In this paper, we present a new algorithm for analyzing performance/cost tradeoffs in interactive synthesis of DSP algorithms. Our algorithm handles both memories with different access times and pipelined units with different numbers of stages. The output is a shape function illustrating the performance vs. cost tradeoff. We have tested this algorithm on several benchmarks including an FIR filter and a robot kinematics example. Results show that the average difference in cost, as compared to manual designs, is 0.41%, while the average performance difference is 4.90% without memory access times and 0.77% with memory access times.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126347574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326858
M. E. Dalkiliç, Vijay Pitchumani
Presents an accurate resource lower bound estimation technique which leads to an efficient, and optimal solution of time-constrained as well as hardware resource-constrained scheduling problems in high-level synthesis. A given time or hardware constrained scheduling problem is transformed into a cost ordered sequence of feasible scheduling problems where a solution to this new problem is guaranteed to be an optimal solution to the original problem. Efficiency of the approach is demonstrated on large high-level synthesis benchmarks like the elliptical wave filter and the discrete cosine transform.<>
{"title":"Optimal operation scheduling using resource lower bound estimations","authors":"M. E. Dalkiliç, Vijay Pitchumani","doi":"10.1109/EDTC.1994.326858","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326858","url":null,"abstract":"Presents an accurate resource lower bound estimation technique which leads to an efficient, and optimal solution of time-constrained as well as hardware resource-constrained scheduling problems in high-level synthesis. A given time or hardware constrained scheduling problem is transformed into a cost ordered sequence of feasible scheduling problems where a solution to this new problem is guaranteed to be an optimal solution to the original problem. Efficiency of the approach is demonstrated on large high-level synthesis benchmarks like the elliptical wave filter and the discrete cosine transform.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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