Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326906
A. Greiner, L. Lucas, F. Wajsbürt, L. Winckel
This paper presents the design flow for a superscalar VLIW microprocessor using the 0.8 /spl mu/ CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A full set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle and to maintain a high level of integration and performance. The final circuit contains about 875000 transistors with a die size of 14.6/spl times/14.6 mm/sup 2/. The chip design and verification have been performed with new advanced CAD tools developed in the IDPS project. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA.<>
{"title":"Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library","authors":"A. Greiner, L. Lucas, F. Wajsbürt, L. Winckel","doi":"10.1109/EDTC.1994.326906","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326906","url":null,"abstract":"This paper presents the design flow for a superscalar VLIW microprocessor using the 0.8 /spl mu/ CMOS portable ASIC library developed in the framework of the ESPRIT2 IDPS project. A full set of cell libraries and macro-block generators have been used, in order to achieve fast design cycle and to maintain a high level of integration and performance. The final circuit contains about 875000 transistors with a die size of 14.6/spl times/14.6 mm/sup 2/. The chip design and verification have been performed with new advanced CAD tools developed in the IDPS project. The layout uses a symbolic approach in order to provide process independence. The package is a 428-pin PGA.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128570693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326916
C. Ramachandran, F. Kurdahi
High level synthesis (HLS) has been mainly concerned with datapath synthesis of a digital system. Consequently, controller effects are often ignored when performing HLS tasks. However, the controller may sometimes have significant contributions to the overall system area and delay. Thus, it is necessary to incorporate the controller effects during HLS. Since control synthesis tools such as MISII are time consuming, it is not feasible to synthesize a controller netlist every time a high level design decision is made. As a result, it is necessary to estimate the controller contribution. As a first step towards a comprehensive prediction scheme, we present a simple yet effective controller estimation model which can be invoked during the register-transfer synthesis phase of HLS, which attempts to reflect the incremental effects of iterative RT level transformations on the controller area and delay. Our model has been bench-marked and found to efficiently account for the controller area and delay.<>
{"title":"Incorporating the controller effects during register transfer level synthesis","authors":"C. Ramachandran, F. Kurdahi","doi":"10.1109/EDTC.1994.326916","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326916","url":null,"abstract":"High level synthesis (HLS) has been mainly concerned with datapath synthesis of a digital system. Consequently, controller effects are often ignored when performing HLS tasks. However, the controller may sometimes have significant contributions to the overall system area and delay. Thus, it is necessary to incorporate the controller effects during HLS. Since control synthesis tools such as MISII are time consuming, it is not feasible to synthesize a controller netlist every time a high level design decision is made. As a result, it is necessary to estimate the controller contribution. As a first step towards a comprehensive prediction scheme, we present a simple yet effective controller estimation model which can be invoked during the register-transfer synthesis phase of HLS, which attempts to reflect the incremental effects of iterative RT level transformations on the controller area and delay. Our model has been bench-marked and found to efficiently account for the controller area and delay.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126091084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326881
Brian Chess, T. Larrabee
We describe a system for generating accurate tests for bridge faults (with or without feedback) in CMOS ICs. We present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridge faults via topological analysis of the feedback-influenced region of the faulted circuit (without the need for any post-test verification or explicit examination of inversion parity). We describe our test pattern generation system's treatment of feedback bridge faults in detail and report on the system's performance.<>
{"title":"Generating test patterns for bridge faults in CMOS ICs","authors":"Brian Chess, T. Larrabee","doi":"10.1109/EDTC.1994.326881","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326881","url":null,"abstract":"We describe a system for generating accurate tests for bridge faults (with or without feedback) in CMOS ICs. We present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridge faults via topological analysis of the feedback-influenced region of the faulted circuit (without the need for any post-test verification or explicit examination of inversion parity). We describe our test pattern generation system's treatment of feedback bridge faults in detail and report on the system's performance.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"58 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326844
E. Huijbregts, J. V. Eijndhoven, J. Jess
This paper addresses the problem of design rule correct routing, i.e. the avoidance of illegal wiring patterns during routing. These illegal wiring patterns are due to the set of design rules accompanying each specific technology. To avoid software tuning for different technologies, the routing space is modelled as a grid graph, and all design rules are described in terms of the grid graph, including rules that describe illegal wiring patterns. The problem of finding valid, (i.e. containing no illegal wiring patterns) minimum cost connections is shown to be NP-complete, even for single nets. Although this restriction occurs in most technologies, literature does not mention any routing algorithm capable of handling these situations correctly. Two heuristics are presented to solve the routing problem, both ensuring all paths found to be valid.<>
{"title":"On design rule correct maze routing","authors":"E. Huijbregts, J. V. Eijndhoven, J. Jess","doi":"10.1109/EDTC.1994.326844","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326844","url":null,"abstract":"This paper addresses the problem of design rule correct routing, i.e. the avoidance of illegal wiring patterns during routing. These illegal wiring patterns are due to the set of design rules accompanying each specific technology. To avoid software tuning for different technologies, the routing space is modelled as a grid graph, and all design rules are described in terms of the grid graph, including rules that describe illegal wiring patterns. The problem of finding valid, (i.e. containing no illegal wiring patterns) minimum cost connections is shown to be NP-complete, even for single nets. Although this restriction occurs in most technologies, literature does not mention any routing algorithm capable of handling these situations correctly. Two heuristics are presented to solve the routing problem, both ensuring all paths found to be valid.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130128703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326842
J. Akita, K. Asada
Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of a 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.<>
{"title":"A method for reducing power consumption of CMOS logic based on signal transition probability","authors":"J. Akita, K. Asada","doi":"10.1109/EDTC.1994.326842","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326842","url":null,"abstract":"Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of a 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131448038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326796
M. Hirech, Olivier Florent, A. Greiner, El Housseine Rejouan
A new symbolic simulation technique for design for testability (DFT) rules checking is discussed. With this method symbolic values and transfer functions of gates are redefinable to allow an adaptability to different sets of rules.<>
{"title":"A redefinable symbolic simulation technique for testability design rules checking","authors":"M. Hirech, Olivier Florent, A. Greiner, El Housseine Rejouan","doi":"10.1109/EDTC.1994.326796","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326796","url":null,"abstract":"A new symbolic simulation technique for design for testability (DFT) rules checking is discussed. With this method symbolic values and transfer functions of gates are redefinable to allow an adaptability to different sets of rules.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130012003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326961
W. Vermeiren, B. Straube, G. Elst
On the assumption that a commercial analog simulation tool is used an accelerated analog fault simulation can be carried out by simultaneous simulations of several faulty networks using external user written programs. If clusters with faults having similar sensitivity and temporal effects to the output can be constructed and when the faults of each cluster are simulated simultaneously a further speed-up can be achieved.<>
{"title":"A suggestion for accelerating the analog fault simulation","authors":"W. Vermeiren, B. Straube, G. Elst","doi":"10.1109/EDTC.1994.326961","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326961","url":null,"abstract":"On the assumption that a commercial analog simulation tool is used an accelerated analog fault simulation can be carried out by simultaneous simulations of several faulty networks using external user written programs. If clusters with faults having similar sensitivity and temporal effects to the output can be constructed and when the faults of each cluster are simulated simultaneously a further speed-up can be achieved.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132240508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326849
R. McGowen, F. Ferguson
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise or delay, or increase test pattern generation costs. This paper describes the undetectable nonfeedback shorts that are likely to occur in standard cell implementations of the ISCAS'85 combinational test circuits. For ten layouts of each circuit, all shorts between adjacent wires were extracted and the undetectable ones analyzed. We found that approximately 0.4% are undetectable and that nearly half of these can be easily predicted before the physical layout of the circuit is generated. Since only a small percentage of the shorts are undetectable, and many of the undetectables are easily identifiable, it appears that it is possible to reduce the likelihood, or completely eliminate, the occurrence of a large portion of these shorts by incorporating design-for-test strategies into routing software.<>
{"title":"A study of undetectable non-feedback shorts for the purpose of physical-DFT","authors":"R. McGowen, F. Ferguson","doi":"10.1109/EDTC.1994.326849","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326849","url":null,"abstract":"Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise or delay, or increase test pattern generation costs. This paper describes the undetectable nonfeedback shorts that are likely to occur in standard cell implementations of the ISCAS'85 combinational test circuits. For ten layouts of each circuit, all shorts between adjacent wires were extracted and the undetectable ones analyzed. We found that approximately 0.4% are undetectable and that nearly half of these can be easily predicted before the physical layout of the circuit is generated. Since only a small percentage of the shorts are undetectable, and many of the undetectables are easily identifiable, it appears that it is possible to reduce the likelihood, or completely eliminate, the occurrence of a large portion of these shorts by incorporating design-for-test strategies into routing software.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326808
N. M. Vitsyn
Electronic Design Automation (EDA) Standards are the key element not only of the present but mainly of the future development of CAE/CAD/CAM systems. The paper presents the state of activities in this field in Russia. This is especially important at the present moment when Russia is reestablishing its parity with Western industry in the field of microelectronics.<>
{"title":"The Russian EDA standards activities","authors":"N. M. Vitsyn","doi":"10.1109/EDTC.1994.326808","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326808","url":null,"abstract":"Electronic Design Automation (EDA) Standards are the key element not only of the present but mainly of the future development of CAE/CAD/CAM systems. The paper presents the state of activities in this field in Russia. This is especially important at the present moment when Russia is reestablishing its parity with Western industry in the field of microelectronics.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127400420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-02-28DOI: 10.1109/EDTC.1994.326794
S. Banerjee, R. Roy, S. Chakradhar, D. Pradhan
We present a method of transforming a functionally uninitializable signal transition graph (STG) into a functionally initializable STG. The design of a trigger module is described to illustrate the transformations.<>
{"title":"Signal transition graph transformations for initializability","authors":"S. Banerjee, R. Roy, S. Chakradhar, D. Pradhan","doi":"10.1109/EDTC.1994.326794","DOIUrl":"https://doi.org/10.1109/EDTC.1994.326794","url":null,"abstract":"We present a method of transforming a functionally uninitializable signal transition graph (STG) into a functionally initializable STG. The design of a trigger module is described to illustrate the transformations.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121078516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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