Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201295
Lucas Alves da Silva, W. Tatinian, G. Jacquemod
In this paper the hierarchical modeling of a 2.4-GHz RF power amplifier with its energy consumption considerations is presented. The models foresee the component's total power consumption as one of its high-level parameters, in addition to gain, input and output impedances and third order nonlinearities. Hence an estimation of the energy consumed by the transmitter can be achieved at the system level of design, due to the inclusion of amplifier's efficiency (ŋ), first within an intermediate model (VHDL-AMS) and later at highest level, using Matlab and Simulink.
{"title":"Hierarchical modeling of a 2.4-GHz power amplifier for energy consumption analysis at system level","authors":"Lucas Alves da Silva, W. Tatinian, G. Jacquemod","doi":"10.1109/RME.2009.5201295","DOIUrl":"https://doi.org/10.1109/RME.2009.5201295","url":null,"abstract":"In this paper the hierarchical modeling of a 2.4-GHz RF power amplifier with its energy consumption considerations is presented. The models foresee the component's total power consumption as one of its high-level parameters, in addition to gain, input and output impedances and third order nonlinearities. Hence an estimation of the energy consumed by the transmitter can be achieved at the system level of design, due to the inclusion of amplifier's efficiency (ŋ), first within an intermediate model (VHDL-AMS) and later at highest level, using Matlab and Simulink.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122929822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201291
Martin Trojer, J. García-González, W. Pribyl
This paper presents the design and implementation of a low-voltage low-power high speed pipeline analog-to-digital converter (ADC) for flat-panel display application fabricated in a standard digital 65nm CMOS technology. The ADC does not use a dedicated sample-and-hold (S&H) stage and is built by means of the cascade of 8 pipeline stages and a 2-bit flash ADC. Operational amplifier sharing technique is applied in order to reduce power consumption. Nested cascoded miller compensation technique is used to optimize speed and power of the first and second stage. Performance of 56.5dB SNDR at 5MHz and 50dB at 85MHz input frequency is obtained at 130MS/s for full-scale. The occupied silicon area is 0.125mm2, and the power consumption of 33mW from a 1.1V supply.
{"title":"A 10bit 1.1V 130MS/s 0.125mm2 pipeline ADC for flat-panel display applications in 65nm CMOS","authors":"Martin Trojer, J. García-González, W. Pribyl","doi":"10.1109/RME.2009.5201291","DOIUrl":"https://doi.org/10.1109/RME.2009.5201291","url":null,"abstract":"This paper presents the design and implementation of a low-voltage low-power high speed pipeline analog-to-digital converter (ADC) for flat-panel display application fabricated in a standard digital 65nm CMOS technology. The ADC does not use a dedicated sample-and-hold (S&H) stage and is built by means of the cascade of 8 pipeline stages and a 2-bit flash ADC. Operational amplifier sharing technique is applied in order to reduce power consumption. Nested cascoded miller compensation technique is used to optimize speed and power of the first and second stage. Performance of 56.5dB SNDR at 5MHz and 50dB at 85MHz input frequency is obtained at 130MS/s for full-scale. The occupied silicon area is 0.125mm2, and the power consumption of 33mW from a 1.1V supply.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201372
F. Garzia, T. Ahonen, J. Nurmi
This paper describes a novel interconnection infrastructure for a general-purpose system composed of a RISC processor core and a coarse grain run-time reconfigurable array. The proposed infrastructure is based on a non-blocking network of switches and provides a point-to-point connection between the two processing blocks and all the system peripherals. Modifications to the switches and adoption of separated clock domains allowed the achievement of a 3x speed-up in comparison with a bus based interconnection.
{"title":"A switched interconnection infrastructure to tightly-couple a RISC processor core with a coarse grain reconfigurable array","authors":"F. Garzia, T. Ahonen, J. Nurmi","doi":"10.1109/RME.2009.5201372","DOIUrl":"https://doi.org/10.1109/RME.2009.5201372","url":null,"abstract":"This paper describes a novel interconnection infrastructure for a general-purpose system composed of a RISC processor core and a coarse grain run-time reconfigurable array. The proposed infrastructure is based on a non-blocking network of switches and provides a point-to-point connection between the two processing blocks and all the system peripherals. Modifications to the switches and adoption of separated clock domains allowed the achievement of a 3x speed-up in comparison with a bus based interconnection.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"68 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127972675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201350
Wenbin Chen, A. Mathewson, K. McCarthy
This paper addresses the issue of thin-film characterization through wafer-probe measurements and electromagnetic simulation (EM simulation). The parameters are optimized to get the best fit between measured and simulated S-parameters. Based on the results obtained an optimization methodology for modeling the test structure is presented. The optimization methodology has been verified by investigating the S-parameters of Coplanar-Waveguide (CPW) transmission lines with a known SiO2 layer using CAD simulations and two-port S-parameter measurements up to 6 GHz. The combination of CAD simulation and S-parameter measurement is shown to be suitable for characterization of dielectric materials.
{"title":"Sensitivity analysis and fine tuning of EM simulation for CPW transmission line characterization","authors":"Wenbin Chen, A. Mathewson, K. McCarthy","doi":"10.1109/RME.2009.5201350","DOIUrl":"https://doi.org/10.1109/RME.2009.5201350","url":null,"abstract":"This paper addresses the issue of thin-film characterization through wafer-probe measurements and electromagnetic simulation (EM simulation). The parameters are optimized to get the best fit between measured and simulated S-parameters. Based on the results obtained an optimization methodology for modeling the test structure is presented. The optimization methodology has been verified by investigating the S-parameters of Coplanar-Waveguide (CPW) transmission lines with a known SiO2 layer using CAD simulations and two-port S-parameter measurements up to 6 GHz. The combination of CAD simulation and S-parameter measurement is shown to be suitable for characterization of dielectric materials.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130280769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201314
M. Bichan, A. C. Carusone
We present an analysis of offset voltage and noise in a dynamic comparator. To limit the offset and noise to acceptable levels, a single comparator must be sized quite large. We show that better use can be made of this die area by dividing it into an array of redundant comparators from which the lowest-offset device is chosen. Monte Carlo simulations with a 45nm CMOS process confirm that the input-offset standard deviation can be reduced arbitrarily in the absence of noise. As the area is divided into a greater number of smaller comparators, random noise overtakes offset as the factor limiting the sensitivity. The competing effects of offset and noise combine to give an optimum number of comparators that maximizes sensitivity for a given total area.
{"title":"The effect of redundancy on mismatch-induced offset and random noise in a dynamic comparator","authors":"M. Bichan, A. C. Carusone","doi":"10.1109/RME.2009.5201314","DOIUrl":"https://doi.org/10.1109/RME.2009.5201314","url":null,"abstract":"We present an analysis of offset voltage and noise in a dynamic comparator. To limit the offset and noise to acceptable levels, a single comparator must be sized quite large. We show that better use can be made of this die area by dividing it into an array of redundant comparators from which the lowest-offset device is chosen. Monte Carlo simulations with a 45nm CMOS process confirm that the input-offset standard deviation can be reduced arbitrarily in the absence of noise. As the area is divided into a greater number of smaller comparators, random noise overtakes offset as the factor limiting the sensitivity. The competing effects of offset and noise combine to give an optimum number of comparators that maximizes sensitivity for a given total area.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114871973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201346
Enrique Sedano, D. Chaver, J. Resano
Branch prediction is an important topic in modern Computer Architecture research. Predictors attempt to improve the performance of a processor with a reasonable HW cost. In the last decade, many prediction schemes have been developed in order to achieve this objective, each of them with different cost/performance trade-offs. Identifying the optimal predictor for a given architecture and set of applications is an important issue that involves carrying out extensive simulations. Normally this exploration is carried out using SW emulation tools. However, this approach provides very slow simulation speeds, making it unfeasible for large design-space explorations. In this context, our work presents an important contribution, since we have developed a HW platform, based on FPGAs, for evaluating branch predictors. This platform allows us to evaluate in parallel representative branch prediction schemes, while executing the benchmarks in a SPARC v8 processor implemented in the FPGA. Our approach is several orders of magnitude faster than traditional SWbased approaches, and it not only provides accurate performance statistics but also reports the area cost and the maximum operating frequency of each predictor. In addition, our platform can be easily extended for other processor architectures as long as its HDL codes are available.
{"title":"Implementation of a hardware branch-predictor evaluation platform based on FPGAs","authors":"Enrique Sedano, D. Chaver, J. Resano","doi":"10.1109/RME.2009.5201346","DOIUrl":"https://doi.org/10.1109/RME.2009.5201346","url":null,"abstract":"Branch prediction is an important topic in modern Computer Architecture research. Predictors attempt to improve the performance of a processor with a reasonable HW cost. In the last decade, many prediction schemes have been developed in order to achieve this objective, each of them with different cost/performance trade-offs. Identifying the optimal predictor for a given architecture and set of applications is an important issue that involves carrying out extensive simulations. Normally this exploration is carried out using SW emulation tools. However, this approach provides very slow simulation speeds, making it unfeasible for large design-space explorations. In this context, our work presents an important contribution, since we have developed a HW platform, based on FPGAs, for evaluating branch predictors. This platform allows us to evaluate in parallel representative branch prediction schemes, while executing the benchmarks in a SPARC v8 processor implemented in the FPGA. Our approach is several orders of magnitude faster than traditional SWbased approaches, and it not only provides accurate performance statistics but also reports the area cost and the maximum operating frequency of each predictor. In addition, our platform can be easily extended for other processor architectures as long as its HDL codes are available.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132787998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201323
F. Brandonisio, Michael Peter Kennedy
In this paper, we compare a 2GHz LC oscillatorbased ILFD with a 2GHz ring oscillator-based ILFD in terms of locking range, phase noise and power consumption. We recall the definitions of open and closed loop quality factor. The open loop quality factor is convenient for relating phase noise to the circuit parameters. The closed loop quality factor is suitable for relating locking range and circuit parameters. By means of simulations, the locking range and phase noise are determined for different values of quality factor and power consumption. We show qualitatively how to tune the circuit parameters to achieve better performance.
{"title":"Comparison of ring and LC oscillator-based ILFDs in terms of phase noise, locking range, power consumption and quality factor","authors":"F. Brandonisio, Michael Peter Kennedy","doi":"10.1109/RME.2009.5201323","DOIUrl":"https://doi.org/10.1109/RME.2009.5201323","url":null,"abstract":"In this paper, we compare a 2GHz LC oscillatorbased ILFD with a 2GHz ring oscillator-based ILFD in terms of locking range, phase noise and power consumption. We recall the definitions of open and closed loop quality factor. The open loop quality factor is convenient for relating phase noise to the circuit parameters. The closed loop quality factor is suitable for relating locking range and circuit parameters. By means of simulations, the locking range and phase noise are determined for different values of quality factor and power consumption. We show qualitatively how to tune the circuit parameters to achieve better performance.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129788946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201306
M. Tonelli, A. Boni, C. Azzolini
A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).
{"title":"Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers","authors":"M. Tonelli, A. Boni, C. Azzolini","doi":"10.1109/RME.2009.5201306","DOIUrl":"https://doi.org/10.1109/RME.2009.5201306","url":null,"abstract":"A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133194052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201298
J. A. Rodríguez-Rodríguez, J. Masuch, M. Delgado-Restituto
Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation- 2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35µm CMOS technology process and occupies 7mm2 including pads. The design also incorporates a 10-b rail-to-rail SAR ADC for sensory applications. Under maximum digital activity conditions, post-layout simulations show that the power consumption of the processor below 2.8µW.
{"title":"An EPC Class-1 Generation-2 baseband processor for passive UHF RFID tag","authors":"J. A. Rodríguez-Rodríguez, J. Masuch, M. Delgado-Restituto","doi":"10.1109/RME.2009.5201298","DOIUrl":"https://doi.org/10.1109/RME.2009.5201298","url":null,"abstract":"Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation- 2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35µm CMOS technology process and occupies 7mm2 including pads. The design also incorporates a 10-b rail-to-rail SAR ADC for sensory applications. Under maximum digital activity conditions, post-layout simulations show that the power consumption of the processor below 2.8µW.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134539462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-12DOI: 10.1109/RME.2009.5201345
J. Hilder, James Alfred Walker, A. Tyrrell
This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.
{"title":"Designing variability tolerant logic using evolutionary algorithms","authors":"J. Hilder, James Alfred Walker, A. Tyrrell","doi":"10.1109/RME.2009.5201345","DOIUrl":"https://doi.org/10.1109/RME.2009.5201345","url":null,"abstract":"This paper describes an approach to create novel, robust logic-circuit topologies, using several evolution-inspired techniques over a number of design stages. A library of 2-input logic gates are evolved and optimised for tolerance to the effects of intrinsic variability. Block-level designs are evolved using evolutionary methods (CGP). A method of selecting the optimal gates from the library to fit into the block-level designs to create variability-tolerant circuits is also proposed.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132215900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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