Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541522
C. V. Vangerow, Daniel Stracke, D. Kissinger, T. Zwick
In this work the design of variable gain amplifiers using the distributed amplifier topology with capacitive division is explored. The effects of the capacitive division technique on gain, line attenuation and bandwidth of the amplifier in different bias states are analyzed by means of circuit simulations and theoretical investigations. The designed 3-stage circuit shows a gain range from −0.1 to 11.9 dB at a bandwidth of at least 1.2-83 GHz over all measured gain states. At maximum gain the upper 3dB frequency exceeds 110 GHz. The circuit fabricated in a 130 nm SiGe BiCMOS technology has a chip area of 0.4 mm2and a power consumption of 72 mW at the maximum gain state.
{"title":"Variable Gain Distributed Amplifier with Capacitive Division","authors":"C. V. Vangerow, Daniel Stracke, D. Kissinger, T. Zwick","doi":"10.23919/eumc.2018.8541522","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541522","url":null,"abstract":"In this work the design of variable gain amplifiers using the distributed amplifier topology with capacitive division is explored. The effects of the capacitive division technique on gain, line attenuation and bandwidth of the amplifier in different bias states are analyzed by means of circuit simulations and theoretical investigations. The designed 3-stage circuit shows a gain range from −0.1 to 11.9 dB at a bandwidth of at least 1.2-83 GHz over all measured gain states. At maximum gain the upper 3dB frequency exceeds 110 GHz. The circuit fabricated in a 130 nm SiGe BiCMOS technology has a chip area of 0.4 mm2and a power consumption of 72 mW at the maximum gain state.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117260159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539879
S. Vehring, G. Boeck
This paper presents a novel push-push frequency doubler concept which can deliver high balanced output power. Two lumped couplers provide balanced quadrature input signaling for two doubler cells. As a result, the output signals of the two doubler cells form an inherently balanced output and a lossy output transformer can be avoided. Hence, higher output power and efficiency can be achieved. Moreover, high fundamental rejection and supply suppression with low LO leakage into other circuit blocks are further advantages. As a proof of concept, a K-band doubler is implemented in a 65 nm CMOS technology. At 0 dBm input power, the circuit delivers 4.3 dBm output power with more than 6 % PAE. The chip draws 24 mA from a 1.2 V supply and the total chip area is 0.85 × 0.55 mm2, The fundamental suppression is around 44 dBc. The concept is applicable to other technologies and frequencies as well.
{"title":"Novel Push-Push Frequency Doubler Concept","authors":"S. Vehring, G. Boeck","doi":"10.23919/EUMIC.2018.8539879","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539879","url":null,"abstract":"This paper presents a novel push-push frequency doubler concept which can deliver high balanced output power. Two lumped couplers provide balanced quadrature input signaling for two doubler cells. As a result, the output signals of the two doubler cells form an inherently balanced output and a lossy output transformer can be avoided. Hence, higher output power and efficiency can be achieved. Moreover, high fundamental rejection and supply suppression with low LO leakage into other circuit blocks are further advantages. As a proof of concept, a K-band doubler is implemented in a 65 nm CMOS technology. At 0 dBm input power, the circuit delivers 4.3 dBm output power with more than 6 % PAE. The chip draws 24 mA from a 1.2 V supply and the total chip area is 0.85 × 0.55 mm2, The fundamental suppression is around 44 dBc. The concept is applicable to other technologies and frequencies as well.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123505554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumic.2018.8539918
Álvaro Díez López, Amparo Herrera Guardado, Juan Carlos Pérez Ambrojo
A wideband frequency multipliers using SiGe bipolar transistors are proposed in this paper. The main circuit of these frequency multipliers consists of an attenuator followed by a bias network and a band pass filter which selects the desired harmonic at the output. The designed doubler can convert a 2–3 GHz input signal to a 4–6 GHz signal, with high suppressions of 59 dB, and 41 dB on the fundamental, and the third harmonic respectively. The tripler can convert a 2.3-2.7 GHz input signal to a 7–8 GHz signal, with suppressions of 68 dB, 52 dB, and 43 dB on the fundamental, the second, and fourth harmonics respectively.
{"title":"Frequency Multipliers Based on Hybrid Technology with High Harmonic Suppression","authors":"Álvaro Díez López, Amparo Herrera Guardado, Juan Carlos Pérez Ambrojo","doi":"10.23919/eumic.2018.8539918","DOIUrl":"https://doi.org/10.23919/eumic.2018.8539918","url":null,"abstract":"A wideband frequency multipliers using SiGe bipolar transistors are proposed in this paper. The main circuit of these frequency multipliers consists of an attenuator followed by a bias network and a band pass filter which selects the desired harmonic at the output. The designed doubler can convert a 2–3 GHz input signal to a 4–6 GHz signal, with high suppressions of 59 dB, and 41 dB on the fundamental, and the third harmonic respectively. The tripler can convert a 2.3-2.7 GHz input signal to a 7–8 GHz signal, with suppressions of 68 dB, 52 dB, and 43 dB on the fundamental, the second, and fourth harmonics respectively.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131741916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539871
R. Pilard, J. Duvernay, M. Wingender, F. Bore, K. Salmi, N. Chantier
Designers of microwave systems are constantly looking for DACs which provide not only large Nyquist zones (>2.5 GHz), but also offer flat frequency response in these large instantaneous bandwidths. Such DACs allow simplifying the architecture of the complete microwave generation system, thus saving costs. This paper covers the performance of a new generation DAC with a working range up to the K-band. A number of applications of this part will be discussed preliminary to a review of the aspects of interfacing to this component in the digital and analogue domains. Typical single tone and broadband measurement results are proposed in the last part.
{"title":"First K-band Capable 12-bit 6 GSps Digital to Analogue Converter","authors":"R. Pilard, J. Duvernay, M. Wingender, F. Bore, K. Salmi, N. Chantier","doi":"10.23919/EUMIC.2018.8539871","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539871","url":null,"abstract":"Designers of microwave systems are constantly looking for DACs which provide not only large Nyquist zones (>2.5 GHz), but also offer flat frequency response in these large instantaneous bandwidths. Such DACs allow simplifying the architecture of the complete microwave generation system, thus saving costs. This paper covers the performance of a new generation DAC with a working range up to the K-band. A number of applications of this part will be discussed preliminary to a review of the aspects of interfacing to this component in the digital and analogue domains. Typical single tone and broadband measurement results are proposed in the last part.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129052717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539943
A. Shrestha, J. Moll, A. Raemer, M. Hrobak, V. Krozer
This paper presents work on a 20 GHz ROM-less direct digital synthesizer (DDS) with 12-bit phase and 6-bit amplitude resolution in a 0.25μm SiGe technology having ft/fmax 180/220GHz. The DDS is applicable for wireless communications and is capable of generating sinusoidal and complex waveforms up to 10 GHz. The 12-bit reduced size pipeline accumulator has been designed with a novel 6-bit phase control word unit to facilitate digital phase modulation schemes. The DDS has been successfully measured and characterized using a dedicated PCB board. Its operation has been confirmed in terms of frequency settings. The output amplitude from the DDS is lower than expected due to losses in the FR4 PCB. To our knowledge this DDS is the first attempt to employ a digital phase control and is among the fastest DDS in SiGe BiCMOS reported so far. The total power consumption is only 1.54 W. The DDS has an output frequency range from 5 MHz to 10 GHz with worst case spurious free dynamic range (SFDR) of 25 dBc with a maximum clock frequency of 20 GHz. The frequency settling time is below 300 ns.
{"title":"20 GHz Clock Frequency ROM-Less Direct Digital Synthesizer Comprising Unique Phase Control Unit in 0.25 μm SiGe Technology","authors":"A. Shrestha, J. Moll, A. Raemer, M. Hrobak, V. Krozer","doi":"10.23919/EUMIC.2018.8539943","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539943","url":null,"abstract":"This paper presents work on a 20 GHz ROM-less direct digital synthesizer (DDS) with 12-bit phase and 6-bit amplitude resolution in a 0.25μm SiGe technology having ft/fmax 180/220GHz. The DDS is applicable for wireless communications and is capable of generating sinusoidal and complex waveforms up to 10 GHz. The 12-bit reduced size pipeline accumulator has been designed with a novel 6-bit phase control word unit to facilitate digital phase modulation schemes. The DDS has been successfully measured and characterized using a dedicated PCB board. Its operation has been confirmed in terms of frequency settings. The output amplitude from the DDS is lower than expected due to losses in the FR4 PCB. To our knowledge this DDS is the first attempt to employ a digital phase control and is among the fastest DDS in SiGe BiCMOS reported so far. The total power consumption is only 1.54 W. The DDS has an output frequency range from 5 MHz to 10 GHz with worst case spurious free dynamic range (SFDR) of 25 dBc with a maximum clock frequency of 20 GHz. The frequency settling time is below 300 ns.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129106163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541625
S. Senega, Jürgen Röber, A. Nassar, R. Weigel, C. Heuer, S. Lindenmeier
A compact antenna diversity system with a new integrated circuit is presented for automotive reception of satellite digital audio radio services (SDARS) at 2.3 GHz. For a scan-phase antenna diversity with switching and phase alignment of up to three antenna paths, the integrated circuit includes RF switches, phase-alignment and signal combining as well as the frequency conversion for level detection. This is the first integrated circuit for SDARS scan-phase antenna diversity, which includes all the diversity functions except for level detection and digital signal processing. With the integrated circuit with a package size of only 9 mm by 9 mm a compact hardware demonstrator is realized. The diversity circuit is independent of the radio and offers the same interface to the radio as a conventional single antenna. In laboratory measurements characteristic values of the RF signal paths like gain and variable phase shift are determined. In addition, the new compact diversity circuit is also evaluated in a real fading scenario on a single side mirror of the test vehicle showing a significant reduction of audio mutes by the diversity system compared to single antenna reception.
{"title":"New Compact Antenna Diversity with a Fully Integrated Microwave Circuit for Automotive Satellite Radio Reception","authors":"S. Senega, Jürgen Röber, A. Nassar, R. Weigel, C. Heuer, S. Lindenmeier","doi":"10.23919/eumc.2018.8541625","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541625","url":null,"abstract":"A compact antenna diversity system with a new integrated circuit is presented for automotive reception of satellite digital audio radio services (SDARS) at 2.3 GHz. For a scan-phase antenna diversity with switching and phase alignment of up to three antenna paths, the integrated circuit includes RF switches, phase-alignment and signal combining as well as the frequency conversion for level detection. This is the first integrated circuit for SDARS scan-phase antenna diversity, which includes all the diversity functions except for level detection and digital signal processing. With the integrated circuit with a package size of only 9 mm by 9 mm a compact hardware demonstrator is realized. The diversity circuit is independent of the radio and offers the same interface to the radio as a conventional single antenna. In laboratory measurements characteristic values of the RF signal paths like gain and variable phase shift are determined. In addition, the new compact diversity circuit is also evaluated in a real fading scenario on a single side mirror of the test vehicle showing a significant reduction of audio mutes by the diversity system compared to single antenna reception.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126269893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539913
A. Cidronali, G. Collodi
We present a novel design approach of high-power broadband Doherty amplifier (DPA) by the X-parameters. It is based on the nonlinear vector network analysis of the 3-port circuit composed of the main and peak power devices, connected to the input network. The technique permits the analysis of the best termination for both the peak and main devices, mutually interacting by the input network, and development of the broadband output networks which optimizes the mutual devices load modulation. The three-port nonlinear vector characterization method was applied to the analysis of a broadband DPA designs based on a pair of Silicon Laterally Diffused MOSFETs (LDMOS) with optimized peak power and efficiency in the 700 MHz to 960 MHz bandwidth. The DPA performance exhibited a peak power of 54.2 dBm at center frequency with a peak drain efficiency up to 71.5%. and a drain efficiency in excess of 68 % within 8-dB back-off at center frequency band.
{"title":"X-Parameter Characterization of LDMOS Devices for Broadband Doherty High-Power Amplifier Design","authors":"A. Cidronali, G. Collodi","doi":"10.23919/EUMIC.2018.8539913","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539913","url":null,"abstract":"We present a novel design approach of high-power broadband Doherty amplifier (DPA) by the X-parameters. It is based on the nonlinear vector network analysis of the 3-port circuit composed of the main and peak power devices, connected to the input network. The technique permits the analysis of the best termination for both the peak and main devices, mutually interacting by the input network, and development of the broadband output networks which optimizes the mutual devices load modulation. The three-port nonlinear vector characterization method was applied to the analysis of a broadband DPA designs based on a pair of Silicon Laterally Diffused MOSFETs (LDMOS) with optimized peak power and efficiency in the 700 MHz to 960 MHz bandwidth. The DPA performance exhibited a peak power of 54.2 dBm at center frequency with a peak drain efficiency up to 71.5%. and a drain efficiency in excess of 68 % within 8-dB back-off at center frequency band.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541779
Çağdaş Yağbasan, Ahmet Aktuğ
In this paper, design and measurement of X-Band monolithic microwave integrated circuit (MMIC) low noise amplifiers (LNA) using a commercial 0.25 um microstrip GaN-on-SiC high electron mobility transistor (HEMT) technology are reported. Using a novel active limiting approach in measurements, lower than 1.75 dB noise figure (NF) and higher than 16 W CW input power survivability is obtained from a single chip. To the best of authors' knowledge, said LNA has the highest input power handling performance for the given noise figure level although transistors are not optimized for low-noise operation and input matching network is realized to compromise between noise figure and input return loss which is better than 10 dB. Results are promising for single chip GaN frontend transceiver architecture realization.
{"title":"Robust X-band GaN LNA with Integrated Active Limiter","authors":"Çağdaş Yağbasan, Ahmet Aktuğ","doi":"10.23919/eumc.2018.8541779","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541779","url":null,"abstract":"In this paper, design and measurement of X-Band monolithic microwave integrated circuit (MMIC) low noise amplifiers (LNA) using a commercial 0.25 um microstrip GaN-on-SiC high electron mobility transistor (HEMT) technology are reported. Using a novel active limiting approach in measurements, lower than 1.75 dB noise figure (NF) and higher than 16 W CW input power survivability is obtained from a single chip. To the best of authors' knowledge, said LNA has the highest input power handling performance for the given noise figure level although transistors are not optimized for low-noise operation and input matching network is realized to compromise between noise figure and input return loss which is better than 10 dB. Results are promising for single chip GaN frontend transceiver architecture realization.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115233764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-08-01DOI: 10.1109/emceurope.2018.8485110
{"title":"This publication has been designed for use with Adobe Reader 8 or later","authors":"","doi":"10.1109/emceurope.2018.8485110","DOIUrl":"https://doi.org/10.1109/emceurope.2018.8485110","url":null,"abstract":"","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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