Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539907
K. Kawasaki, E. Kuwata, Hidenori Ishibashi, T. Yao, Kiyoshi Ishida, Kazuhiro Maeda, H. Shibata, M. Tsuru, K. Mori, M. Shimozawa, H. Fukumoto
This paper demonstrates a S-band 3D surface mount packaged Si and GaN Tx Module using flip-chip bonding and a chip embedded PCB Substrate. In order to integrate heterogeneous SiGe and GaN chips in a single package, 3D-structure is employed. The GaN chip is embedded in the PCB substrate and the SiGe chip is flip-chip bonded on the GaN embedded PCB Substrate. The Tx module includes a 5bit phase shifter, a 5bit VGA, a driver amplifier, and a power amplifier. The package size is occupying 7×7mm2• The developed Tx module achieves phase and amplitude error of less than 1.3 degrees-rms., and 0.36dB rms., and an output power of30dBm, respectively.
{"title":"A S-band 3D Surface Mount Packaged SiGe and GaN Tx Module Using Flip-Chip Bonding and a Device Embedded PCB Substrate","authors":"K. Kawasaki, E. Kuwata, Hidenori Ishibashi, T. Yao, Kiyoshi Ishida, Kazuhiro Maeda, H. Shibata, M. Tsuru, K. Mori, M. Shimozawa, H. Fukumoto","doi":"10.23919/EUMIC.2018.8539907","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539907","url":null,"abstract":"This paper demonstrates a S-band 3D surface mount packaged Si and GaN Tx Module using flip-chip bonding and a chip embedded PCB Substrate. In order to integrate heterogeneous SiGe and GaN chips in a single package, 3D-structure is employed. The GaN chip is embedded in the PCB substrate and the SiGe chip is flip-chip bonded on the GaN embedded PCB Substrate. The Tx module includes a 5bit phase shifter, a 5bit VGA, a driver amplifier, and a power amplifier. The package size is occupying 7×7mm2• The developed Tx module achieves phase and amplitude error of less than 1.3 degrees-rms., and 0.36dB rms., and an output power of30dBm, respectively.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133942525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539963
Paolo Enrico de Falco, K. Mimis, S. B. Smida, Kevin Morris, G. Watkins, A. Yamaoka, K. Yamaguchi
Back-off efficiency is a key requirement for load modulated power amplifier (PA) architectures such as Chireix outphasing. This paper studies the impact of second and third harmonic impedance tuning (Z2fo,Z3fo) on the performance of a 10 Watt GaN HEMT branch PA subject to outphasing-like load modulation, operating at 900 MHz. Performance variation of up to 3 dB output power (POUT) and 50% points drain efficiency (DE) with phase manipulation alone of Z2fo is recorded. Optimal Z2fo is revealed to vary - throughout a fixed and for different - outphasing trajectories. A simple technique is presented, using continuous class F−1closed form equations, which predicts the intrinsic optimal Z2fo for multiple points from five outphasing load trajectories, de-embedded to the current generator (CG) plane of the device.
回退效率是负载调制功率放大器(PA)架构(如Chireix失相)的关键要求。本文研究了二次和三次谐波阻抗调谐(Z2fo,Z3fo)对工作于900 MHz的10w GaN HEMT支路PA在类失相负载调制下性能的影响。记录了高达3db输出功率(POUT)和50%点漏极效率(DE)的性能变化，仅用Z2fo进行相位操作。最优Z2fo在一个固定的和不同的同相轨迹中是变化的。提出了一种简单的技术，使用连续类F−1闭形式方程，预测了从五个失相负载轨迹到器件电流发生器(CG)平面的多个点的内在最优Z2fo。
{"title":"Single-Ended Branch PA Characterisation for Outphasing Amplifiers","authors":"Paolo Enrico de Falco, K. Mimis, S. B. Smida, Kevin Morris, G. Watkins, A. Yamaoka, K. Yamaguchi","doi":"10.23919/EUMIC.2018.8539963","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539963","url":null,"abstract":"Back-off efficiency is a key requirement for load modulated power amplifier (PA) architectures such as Chireix outphasing. This paper studies the impact of second and third harmonic impedance tuning (Z2fo,Z3fo) on the performance of a 10 Watt GaN HEMT branch PA subject to outphasing-like load modulation, operating at 900 MHz. Performance variation of up to 3 dB output power (POUT) and 50% points drain efficiency (DE) with phase manipulation alone of Z2fo is recorded. Optimal Z2fo is revealed to vary - throughout a fixed and for different - outphasing trajectories. A simple technique is presented, using continuous class F−1closed form equations, which predicts the intrinsic optimal Z2fo for multiple points from five outphasing load trajectories, de-embedded to the current generator (CG) plane of the device.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133405418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541803
R. Ishikawa, Y. Takayama, K. Honjo
A fully integrated asymmetric Doherty power amplifier has been developed by using GaN HEMT MMIC technology. To minimize the circuit size, a two-power-level impedance optimization method was applied instead of using a quarter-wavelength transmission line impedance inverter for load modulation in the Doherty amplifier. For this optimization, asymmetric configuration is required to realize optimum impedance conditions. The 4-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 56% and a maximum power-added efficiency (PAE) of 53% at 4.3 GHz, with a saturation output power of 36dBm. In addition, PAE of 44% was achieved at 4.2 GHz on a 6-dB output back-off condition.
{"title":"Fully Integrated Asymmetric Doherty Amplifier Based on Two-Power-Level Impedance Optimization","authors":"R. Ishikawa, Y. Takayama, K. Honjo","doi":"10.23919/eumc.2018.8541803","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541803","url":null,"abstract":"A fully integrated asymmetric Doherty power amplifier has been developed by using GaN HEMT MMIC technology. To minimize the circuit size, a two-power-level impedance optimization method was applied instead of using a quarter-wavelength transmission line impedance inverter for load modulation in the Doherty amplifier. For this optimization, asymmetric configuration is required to realize optimum impedance conditions. The 4-GHz-band GaN HEMT Doherty amplifier MMIC exhibited a maximum drain efficiency of 56% and a maximum power-added efficiency (PAE) of 53% at 4.3 GHz, with a saturation output power of 36dBm. In addition, PAE of 44% was achieved at 4.2 GHz on a 6-dB output back-off condition.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539900
M. De Stefano, S. Grivet-Talocia, T. Bradde, A. Zanco
We present a numerical scheme for the identification of compact surrogate models of analog circuit blocks. The basic assumption is small signal operation, so that a local linearization can be applied around a given bias point, resulting in a bias-dependent linear state-space behavioral macromodel. The main novel contribution of this work is the ability to embed in the identification process a suitable set of constraints, that are able to guarantee the uniform stability of the model for any bias value within a prescribed design range.
{"title":"A Framework for the Generation of Guaranteed Stable Small-Signal Bias-Dependent Behavioral Models","authors":"M. De Stefano, S. Grivet-Talocia, T. Bradde, A. Zanco","doi":"10.23919/EUMIC.2018.8539900","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539900","url":null,"abstract":"We present a numerical scheme for the identification of compact surrogate models of analog circuit blocks. The basic assumption is small signal operation, so that a local linearization can be applied around a given bias point, resulting in a bias-dependent linear state-space behavioral macromodel. The main novel contribution of this work is the ability to embed in the identification process a suitable set of constraints, that are able to guarantee the uniform stability of the model for any bias value within a prescribed design range.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125883390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539964
M. Hashemi, M. Alavi, L. D. de Vreede
The maximum achievable linearity of a digital polar transmitter (DPTX) is mainly constrained by two RF-DAC associated nonidealities; namely, aliasing of sampling spectral replicas (SSR) of the AM and PM signals, and the presence of nonuniform quantization noise. In this work, using DPTX hardware linearization, in combination with PM SSR filtering and iterative learning control (ILC) algorithm improved by look-up tables (LUT), a CMOS DPTX is linearized close to its theoretical ACPR and EVM limits as predicted by its resolution. Using the ILC technique as underlying basis, an effective real-time direct-learning digital predistortion (DPD) technique is proposed. Measurement results show −60/−53 dBc ACPR and −60/−47 dB EVM using the ILC algorithm for 16/64 MHz OFDM signals, and −55/−48 dBc ACPR and −50/−44 dB EVM using the proposed DPD for 16/64 MHz OFDM signals. To the best of author's knowledge, this is the highest linearity reported for a DPTX operating with wideband signals.
{"title":"Pushing the Linearity Limits of a Digital Polar Transmitter","authors":"M. Hashemi, M. Alavi, L. D. de Vreede","doi":"10.23919/EUMIC.2018.8539964","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539964","url":null,"abstract":"The maximum achievable linearity of a digital polar transmitter (DPTX) is mainly constrained by two RF-DAC associated nonidealities; namely, aliasing of sampling spectral replicas (SSR) of the AM and PM signals, and the presence of nonuniform quantization noise. In this work, using DPTX hardware linearization, in combination with PM SSR filtering and iterative learning control (ILC) algorithm improved by look-up tables (LUT), a CMOS DPTX is linearized close to its theoretical ACPR and EVM limits as predicted by its resolution. Using the ILC technique as underlying basis, an effective real-time direct-learning digital predistortion (DPD) technique is proposed. Measurement results show −60/−53 dBc ACPR and −60/−47 dB EVM using the ILC algorithm for 16/64 MHz OFDM signals, and −55/−48 dBc ACPR and −50/−44 dB EVM using the proposed DPD for 16/64 MHz OFDM signals. To the best of author's knowledge, this is the highest linearity reported for a DPTX operating with wideband signals.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124807403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539923
F. Heinz, D. Schwantuschke, A. Leuther, A. Tessmann, M. Ohlrogge, R. Quay, O. Ambacher
The mechanisms causing the RF-noise in InGaAs metamorphic HEMTs and MOSFETs have been investigated and compared. A small signal model for InGaAs- metamorphic HEMTs and InGaAs MOSFETs, including an accurate description of the RF-noise, is presented. The model is based on a distributed multiport-network approach, which is scalable in gate width, the number of gate-fingers and covers usual bias points used in amplifier circuits. The noise model is capable of analyzing the sources of noise in InGaAs HEMTs and MOSFETs and their impact on the overall device noise figure. The new extracted MOSFET model is verified on circuit level in the W-Band (75 to 110GHz).
{"title":"RF-Noise Modeling of InGaAs Metamorphic HEMTs and MOSFETs","authors":"F. Heinz, D. Schwantuschke, A. Leuther, A. Tessmann, M. Ohlrogge, R. Quay, O. Ambacher","doi":"10.23919/EUMIC.2018.8539923","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539923","url":null,"abstract":"The mechanisms causing the RF-noise in InGaAs metamorphic HEMTs and MOSFETs have been investigated and compared. A small signal model for InGaAs- metamorphic HEMTs and InGaAs MOSFETs, including an accurate description of the RF-noise, is presented. The model is based on a distributed multiport-network approach, which is scalable in gate width, the number of gate-fingers and covers usual bias points used in amplifier circuits. The noise model is capable of analyzing the sources of noise in InGaAs HEMTs and MOSFETs and their impact on the overall device noise figure. The new extracted MOSFET model is verified on circuit level in the W-Band (75 to 110GHz).","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127968296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539939
M. Bao, Z. He, Thanh NgocThi Do, H. Zirath
The presented D-band sixtupler consists of a frequency tripler, a frequency doubler, as well as amplifiers. The optimum arrangement for those blocks is investigated. The analysis shows that the tripler should precede the doubler. Furthermore, to extend the bandwidth, an amplifier with an increasing gain versus frequency is applied, to compensate the gain decrease of the tripler. This wideband frequency sixtupler is designed and characterized in a 130 nm SiGe BiCMOS technology. This sixtupler has a bandwidth of 37 GHz (from 110 to 147 GHz), the maximum output power is 4.5 dBm, with a DC power consumption of 310 mW. The maximum power efficiency is 0.9%.
{"title":"A 110-to-147 GHz Frequency Sixtupler in a 130 nm Sige Bicmos Technology","authors":"M. Bao, Z. He, Thanh NgocThi Do, H. Zirath","doi":"10.23919/EUMIC.2018.8539939","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539939","url":null,"abstract":"The presented D-band sixtupler consists of a frequency tripler, a frequency doubler, as well as amplifiers. The optimum arrangement for those blocks is investigated. The analysis shows that the tripler should precede the doubler. Furthermore, to extend the bandwidth, an amplifier with an increasing gain versus frequency is applied, to compensate the gain decrease of the tripler. This wideband frequency sixtupler is designed and characterized in a 130 nm SiGe BiCMOS technology. This sixtupler has a bandwidth of 37 GHz (from 110 to 147 GHz), the maximum output power is 4.5 dBm, with a DC power consumption of 310 mW. The maximum power efficiency is 0.9%.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117221902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541514
Daniel Kramer
Phase shifters are an important part of phased array antennas, which the next generation 5G wireless communication networks will rely on. This paper presents 4-bit and 6-bit digital phase shifters with very low loss and high power handling that function from 27.5 to 29.5 GHz, a frequency band being considered for 5G. This is achieved by using a combination of all shunt P-I-N diodes switches and delay lines on the MACOM A1GaAs P-I-N diode process. The chips have integrated bias networks and work well with MACOM's MADR-009443 quad driver.
{"title":"Ka-Band P-I-N Diode Based Digital Phase Shifter","authors":"Daniel Kramer","doi":"10.23919/eumc.2018.8541514","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541514","url":null,"abstract":"Phase shifters are an important part of phased array antennas, which the next generation 5G wireless communication networks will rely on. This paper presents 4-bit and 6-bit digital phase shifters with very low loss and high power handling that function from 27.5 to 29.5 GHz, a frequency band being considered for 5G. This is achieved by using a combination of all shunt P-I-N diodes switches and delay lines on the MACOM A1GaAs P-I-N diode process. The chips have integrated bias networks and work well with MACOM's MADR-009443 quad driver.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539962
R. Kabouche, J. Derluyn, R. Pusche, S. Degroote, M. Germain, R. Pecheux, E. Okada, M. Zegaoui, F. Medjdoub
We report on a comparison of the ultrathin (sub-10 nm barrier thickness) AIN/GaN heterostructure using two types of buffer layers for millimeter-wave applications: 1) carbon doped GaN high electron mobility transistors (HEMTs) and 2) double heterostructure field effect transistor (DHFET). It is observed that the carbon doped HEMT structure shows superior electrical characteristics, with a maximum drain current density Id of 1.5 A/mm, an extrinsic transconductance Gm of 500 mS/mm and a maximum oscillation frequency fmaxof 242 GHz while using a gate length of 120 nm. The C-doped structure delivering high frequency performance together with an excellent electron confinement under high bias enabled to achieve a state-of-the-art combination at 40 GHz of output power density (POUT = 7 W/mm) and power added efficiency (PAE) above 52% up to VDs = 25V in pulsed mode.
{"title":"Comparison of C-Doped AlN/GaN HEMTs and AlN/GaN/AlGaN Double Heterostructure for mmW Applications","authors":"R. Kabouche, J. Derluyn, R. Pusche, S. Degroote, M. Germain, R. Pecheux, E. Okada, M. Zegaoui, F. Medjdoub","doi":"10.23919/EUMIC.2018.8539962","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539962","url":null,"abstract":"We report on a comparison of the ultrathin (sub-10 nm barrier thickness) AIN/GaN heterostructure using two types of buffer layers for millimeter-wave applications: 1) carbon doped GaN high electron mobility transistors (HEMTs) and 2) double heterostructure field effect transistor (DHFET). It is observed that the carbon doped HEMT structure shows superior electrical characteristics, with a maximum drain current density Id of 1.5 A/mm, an extrinsic transconductance Gm of 500 mS/mm and a maximum oscillation frequency fmaxof 242 GHz while using a gate length of 120 nm. The C-doped structure delivering high frequency performance together with an excellent electron confinement under high bias enabled to achieve a state-of-the-art combination at 40 GHz of output power density (POUT = 7 W/mm) and power added efficiency (PAE) above 52% up to VDs = 25V in pulsed mode.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128341288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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