Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539952
Run Levinger, R. Levi, E. Shumaker, S. Levin, G. Horovitz
This paper presents an LC tank, ultra-low power CMOS digitally controlled oscillator (DCO) with resistive drain delay element designed and fabricated in 28 nm CMOS process. The implemented DCO covers 3.95 to 4.7 GHz (17% tuning range, TR) with a resolution of 300 to 500 KHz and gain variation of less than 3 % within a sub-band. Measured phase noise at 4.6 GHz is − 83, −109.5 and −130 dBc/Hz for 100 KHz, 1 MHz and 10 MHz offsets respectively. The DCO is designed to be temperature robust and allows operation within −40°C to 130°C. The DCO and output buffers consume 0.44 mA from a 0.8 V supply, for a total power of 0.35mW. The DCO active area is 0.04 mm2.
{"title":"A 3.9-4.7 GHz 0.35 mW DCO with −187.4 dBc FoM in 28nm CMOS","authors":"Run Levinger, R. Levi, E. Shumaker, S. Levin, G. Horovitz","doi":"10.23919/EUMIC.2018.8539952","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539952","url":null,"abstract":"This paper presents an LC tank, ultra-low power CMOS digitally controlled oscillator (DCO) with resistive drain delay element designed and fabricated in 28 nm CMOS process. The implemented DCO covers 3.95 to 4.7 GHz (17% tuning range, TR) with a resolution of 300 to 500 KHz and gain variation of less than 3 % within a sub-band. Measured phase noise at 4.6 GHz is − 83, −109.5 and −130 dBc/Hz for 100 KHz, 1 MHz and 10 MHz offsets respectively. The DCO is designed to be temperature robust and allows operation within −40°C to 130°C. The DCO and output buffers consume 0.44 mA from a 0.8 V supply, for a total power of 0.35mW. The DCO active area is 0.04 mm2.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125608712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539904
S. Theeuwen, H. Mollee, R. Heeres, F. van Rijs
We show the capability of LDMOS technology for power amplifiers at frequencies up to 12 GHz. The frequency roll-off of the RF parameters is presented for the several LDMOS nodes (12V, 30V, 50V). Spectacularly high RF performance is measured by using on-wafer load pull for 4mm structures made in LDMOS 30V node. At 12 GHz, we measure a 35% drain efficiency, 10 dB gain and 1.0W/mm power density. Furthermore at 5 GHz, this on wafer LDMOS has about 63% drain efficiency, 19 dB gain and 1.4 W/mm, showing that LDMOS is capable of serving 5–12 GHz applications. As a demonstrator, we show the first packaged C-band LDMOS amplifier with more than 20W output power and an efficiency of 50–51 % over the band in combination with 15–16 dB maximum linear gain.
{"title":"LDMOS Technology for Power Amplifiers Up to 12 GHz","authors":"S. Theeuwen, H. Mollee, R. Heeres, F. van Rijs","doi":"10.23919/EUMIC.2018.8539904","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539904","url":null,"abstract":"We show the capability of LDMOS technology for power amplifiers at frequencies up to 12 GHz. The frequency roll-off of the RF parameters is presented for the several LDMOS nodes (12V, 30V, 50V). Spectacularly high RF performance is measured by using on-wafer load pull for 4mm structures made in LDMOS 30V node. At 12 GHz, we measure a 35% drain efficiency, 10 dB gain and 1.0W/mm power density. Furthermore at 5 GHz, this on wafer LDMOS has about 63% drain efficiency, 19 dB gain and 1.4 W/mm, showing that LDMOS is capable of serving 5–12 GHz applications. As a demonstrator, we show the first packaged C-band LDMOS amplifier with more than 20W output power and an efficiency of 50–51 % over the band in combination with 15–16 dB maximum linear gain.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121410845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539958
M. Ko, Mohamed Hussein Eissa, J. Borngräber, A. Çağrı Ulusoy, D. Kissinger
This paper proposes a compact and efficient frequency quadrupler based on a single Gilbert cell which converts 30 GHz input frequency directly into 120 GHz. It consists of a spiral Marchand edge coupled input balun, a Gilbert cell based quadrupler core and an output buffer. The Gilbert cell core, which is conventionally utilized as a doubler, is utilized here as a quadrupler to generate strong fourth harmonic by maximizing the nonlinearity of the transconductance stage in order to mix the third harmonic with the fundamental component in the switching quad. The usage of single stage multiplication enables to achieve high power efficiency and wide bandwidth. The circuit implemented in 0.13μm SiGe BiCMOS achieves an output power of 2.7 dBm at 120 GHz with a 3-dB bandwidth of 25 GHz and a power efficiency of 4.1 %. Spurious rejection is better than 30 dBc at the output frequency of 120 GHz. The circuit occupies a silicon area of 0.42 mm2.
{"title":"110–135 GHz SiGe BiCMOS Frequency Quadrupler Based on a Single Gilbert Cell","authors":"M. Ko, Mohamed Hussein Eissa, J. Borngräber, A. Çağrı Ulusoy, D. Kissinger","doi":"10.23919/EUMIC.2018.8539958","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539958","url":null,"abstract":"This paper proposes a compact and efficient frequency quadrupler based on a single Gilbert cell which converts 30 GHz input frequency directly into 120 GHz. It consists of a spiral Marchand edge coupled input balun, a Gilbert cell based quadrupler core and an output buffer. The Gilbert cell core, which is conventionally utilized as a doubler, is utilized here as a quadrupler to generate strong fourth harmonic by maximizing the nonlinearity of the transconductance stage in order to mix the third harmonic with the fundamental component in the switching quad. The usage of single stage multiplication enables to achieve high power efficiency and wide bandwidth. The circuit implemented in 0.13μm SiGe BiCMOS achieves an output power of 2.7 dBm at 120 GHz with a 3-dB bandwidth of 25 GHz and a power efficiency of 4.1 %. Spurious rejection is better than 30 dBc at the output frequency of 120 GHz. The circuit occupies a silicon area of 0.42 mm2.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115223879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539965
Jyh-Chyurn Guo, K. Yeh
A new compact model has been developed in this paper for accurate simulation of RF noise and extraction of actual intrinsic noise in sub-40 nm multi-finger nMOSFETs. This model can predict and verify the excess noise sources before and after deembedding, the mechanism responsible for the complicated layout dependence in various noise parameters, and facilitate optimization design for low noise devices and circuits in nanoscale CMOS technology.
{"title":"A New Compact Model for Accurate Simulation of RF Noise in Sub-40nm Multi-Finger nMOSFETs","authors":"Jyh-Chyurn Guo, K. Yeh","doi":"10.23919/EUMIC.2018.8539965","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539965","url":null,"abstract":"A new compact model has been developed in this paper for accurate simulation of RF noise and extraction of actual intrinsic noise in sub-40 nm multi-finger nMOSFETs. This model can predict and verify the excess noise sources before and after deembedding, the mechanism responsible for the complicated layout dependence in various noise parameters, and facilitate optimization design for low noise devices and circuits in nanoscale CMOS technology.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"153 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131746768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539914
Manuel Potércau, N. Deltimple, A. Ghiotto
In this paper, an ultra-compact transformer-based integrated quadrature hybrid coupler is presented. Its design, taking advantage of the transformer distributed parasitic capacitances to minimize lumped capacitors, achieves low insertion loss and high compactness. For demonstration purposes, a prototype, operating at Ku-band and based on the 130 nm BiCMOS technology from STMicroelectronics, has been fabricated. Theoretical, simulated and experimental results are reported. The demonstrated integrated coupler occupies an area as small as 0.0014 mm2. In the 17.3 to 20.2 GHz frequency range (15.5% relative bandwidth) used for SATCOM applications, an insertion loss and a phase imbalance of better than 0.4 dB and 2° are experimentally obtained, respectively, with an amplitude imbalance of less than 1 dB.
{"title":"Ultra-Compact Low-Loss Integrated Transformer-Based Ku-Band Quadrature Hybrid Coupler","authors":"Manuel Potércau, N. Deltimple, A. Ghiotto","doi":"10.23919/EUMIC.2018.8539914","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539914","url":null,"abstract":"In this paper, an ultra-compact transformer-based integrated quadrature hybrid coupler is presented. Its design, taking advantage of the transformer distributed parasitic capacitances to minimize lumped capacitors, achieves low insertion loss and high compactness. For demonstration purposes, a prototype, operating at Ku-band and based on the 130 nm BiCMOS technology from STMicroelectronics, has been fabricated. Theoretical, simulated and experimental results are reported. The demonstrated integrated coupler occupies an area as small as 0.0014 mm2. In the 17.3 to 20.2 GHz frequency range (15.5% relative bandwidth) used for SATCOM applications, an insertion loss and a phase imbalance of better than 0.4 dB and 2° are experimentally obtained, respectively, with an amplitude imbalance of less than 1 dB.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132809416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539908
R. Jain, Robin Zatta, J. Grzyb, D. Harame, U. Pfeiffer
This paper reports on the design and characterization of a CMOS based direct terahertz detector in an advanced 22nm FD-SOI technology. The nFET detector is implemented with an on-chip ring antenna fully compliant with the technology density rules. At 0.855 THz, a maximum optical responsivity and a minimum noise equivalent power (NEP) of 1.51 kV/W and 22.65 pW/HZ1/2respectively were measured in a voltage mode readout at a chopping frequency of 3 kHz. In the current mode readout, a maximum responsivity of 180 mA/W and minimum NEP of 12 pW/HZ1/2were measured at a chopping frequency of 120 kHz. Additionally, the effect of transistor back-gate biasing on the detector responsivity is also characterized. The detector sensitivity is comparable to the best reported room-temperature THz direct detectors in any silicon integrated technology, along with the highest reported RF operational bandwidth with NEP below 40 pW/HZ1/2in the measured frequency band of 0.7–1 THz.
{"title":"A Terahertz Direct Detector in 22nm FD-SOI CMOS","authors":"R. Jain, Robin Zatta, J. Grzyb, D. Harame, U. Pfeiffer","doi":"10.23919/EUMIC.2018.8539908","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539908","url":null,"abstract":"This paper reports on the design and characterization of a CMOS based direct terahertz detector in an advanced 22nm FD-SOI technology. The nFET detector is implemented with an on-chip ring antenna fully compliant with the technology density rules. At 0.855 THz, a maximum optical responsivity and a minimum noise equivalent power (NEP) of 1.51 kV/W and 22.65 pW/HZ1/2respectively were measured in a voltage mode readout at a chopping frequency of 3 kHz. In the current mode readout, a maximum responsivity of 180 mA/W and minimum NEP of 12 pW/HZ1/2were measured at a chopping frequency of 120 kHz. Additionally, the effect of transistor back-gate biasing on the detector responsivity is also characterized. The detector sensitivity is comparable to the best reported room-temperature THz direct detectors in any silicon integrated technology, along with the highest reported RF operational bandwidth with NEP below 40 pW/HZ1/2in the measured frequency band of 0.7–1 THz.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133191544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541584
M. Ayad, A. Couturier, P. Poilvert, L. Marechal, P. Auxemery
This paper presents the realization and characteristics of broadband plastic low cost packaged 5G High Power Frond-End (HPFE) operating in 24-31GHz bandwidth. This demonstrator includes a Transmit and Receive paths realized on mixed technologies: 150nm Gallium Nitride on Silicon Carbide (AlGaN/GaN on SiC) and 150nm Gallium Arsenide (GaAs). Continuous Wave (CW) measured power results of the Transmit path (Tx) demonstrates a maximum output power (POUT, Tx) higher than 2W (33.5dBm) with 24% power added efficiency (PAE), and 36dB of insertion gain (GI, Tx) in the 24-31GHz bandwidth. The receiver path (Rx) presents an maximum output power (POUT, Rx) of 30m W (15.5dBm) and an average Noise Figure (NF) of 3.6dB with an associated Insertion Gain (GI, Rx) of 20dB in the same bandwidth. The HPFE/Tx linearity has been investigated with several M-QAM modulation signals with 25/50 and 100MHz channel spacing and using Digital Pre-Distortion (DPD) leading to 48dBc Adjacent Channel Leakage Ratio (ACLR) and 40dB Mean Squared Error (MSE) for average output powers ranging from 17dBm to 25dBm. The linearity performances have been compared to the ones obtained with two other linear GaAs amplifiers (P A1 and P A2) dedicated to point to point telecommunications application: the HPFE presents similar linearity performances associated to a higher efficiency.
介绍了工作在24-31GHz带宽范围内的宽带塑料低成本封装5G高功率前端(HPFE)的实现及其特点。该演示器包括采用混合技术实现的发射和接收路径:150nm碳化硅上的氮化镓(AlGaN/GaN on SiC)和150nm砷化镓(GaAs)。发射路径(Tx)的连续波(CW)测量功率结果表明，在24-31GHz带宽下，最大输出功率(POUT, Tx)高于2W (33.5dBm)，功率附加效率(PAE)为24%，插入增益(GI, Tx)为36dB。接收器路径(Rx)在相同带宽下的最大输出功率(POUT, Rx)为30m W (15.5dBm)，平均噪声系数(NF)为3.6dB，相关的插入增益(GI, Rx)为20dB。我们研究了几种具有25/50和100MHz信道间隔的M-QAM调制信号的HPFE/Tx线性度，并使用数字预失真(DPD)在17dBm至25dBm的平均输出功率范围内导致48dBc的相邻信道泄漏比(ACLR)和40dB的均方误差(MSE)。将线性性能与专用于点对点电信应用的另外两个线性GaAs放大器(pa1和pa2)的线性性能进行了比较:HPFE具有与更高效率相关的相似线性性能。
{"title":"Mixed Technologies Packaged High Power Frond-End for Broadband 28GHz 5G Solutions","authors":"M. Ayad, A. Couturier, P. Poilvert, L. Marechal, P. Auxemery","doi":"10.23919/eumc.2018.8541584","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541584","url":null,"abstract":"This paper presents the realization and characteristics of broadband plastic low cost packaged 5G High Power Frond-End (HPFE) operating in 24-31GHz bandwidth. This demonstrator includes a Transmit and Receive paths realized on mixed technologies: 150nm Gallium Nitride on Silicon Carbide (AlGaN/GaN on SiC) and 150nm Gallium Arsenide (GaAs). Continuous Wave (CW) measured power results of the Transmit path (Tx) demonstrates a maximum output power (POUT, Tx) higher than 2W (33.5dBm) with 24% power added efficiency (PAE), and 36dB of insertion gain (GI, Tx) in the 24-31GHz bandwidth. The receiver path (Rx) presents an maximum output power (POUT, Rx) of 30m W (15.5dBm) and an average Noise Figure (NF) of 3.6dB with an associated Insertion Gain (GI, Rx) of 20dB in the same bandwidth. The HPFE/Tx linearity has been investigated with several M-QAM modulation signals with 25/50 and 100MHz channel spacing and using Digital Pre-Distortion (DPD) leading to 48dBc Adjacent Channel Leakage Ratio (ACLR) and 40dB Mean Squared Error (MSE) for average output powers ranging from 17dBm to 25dBm. The linearity performances have been compared to the ones obtained with two other linear GaAs amplifiers (P A1 and P A2) dedicated to point to point telecommunications application: the HPFE presents similar linearity performances associated to a higher efficiency.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539911
V. Van Kerckhoven, L. Piraux, I. Huynen
This paper presents an innovative method to synthesize nanowire-based microwave devices integrated inside a nanoporous alumina membrane. A laser treatment is used to destroy locally the template surface porosity, preventing the nanowire growth in the modified regions. We have realized a substrate integrated waveguide (SIW) in which the vertical walls consist of nanowire arrays. The waveguide can then be modified to achieve different types of microwave devices by properly placing nanowire arrays inside the SIW. The so-obtained devices combine the advantages of nanowire arrays (compactness, tunable permittivity and permeability,…) with those of substrate integrated waveguides (low losses). Our fabrication approach enables wide range of devices and we present promising results for integrated waveguide isolators.
{"title":"A Novel Laser-Assisted Fabrication Process for Nanowired Substrate Integrated Devices","authors":"V. Van Kerckhoven, L. Piraux, I. Huynen","doi":"10.23919/EUMIC.2018.8539911","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539911","url":null,"abstract":"This paper presents an innovative method to synthesize nanowire-based microwave devices integrated inside a nanoporous alumina membrane. A laser treatment is used to destroy locally the template surface porosity, preventing the nanowire growth in the modified regions. We have realized a substrate integrated waveguide (SIW) in which the vertical walls consist of nanowire arrays. The waveguide can then be modified to achieve different types of microwave devices by properly placing nanowire arrays inside the SIW. The so-obtained devices combine the advantages of nanowire arrays (compactness, tunable permittivity and permeability,…) with those of substrate integrated waveguides (low losses). Our fabrication approach enables wide range of devices and we present promising results for integrated waveguide isolators.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539884
Ahmed S. H. Ahmed, A. Farid, M. Urteaga, M. Rodwell
We report stacked mm-wave power amplifiers designed by a novel 2-port technique. Two power amplifiers designed into 130-nm InP HBT to verify the technique. The first design (unit cell) biased at 436mW Pdc produces 34.6mW saturated output power with 5.8% PAE at 204GHz. The amplifier has a 13.9dB peak small signal gain at 236GHz and 27 GHz 3–dB bandwidth. The chip size is 0.63mm×0.54mm including the pads. The second design combines two cells in parallel with an additional gain stage. The design consumes 1.18W Pdc and it shows a 63mW saturated output power with 4.8%PAE at 204GHz. The amplifier has a 22.7 dB peak small signal gain at 230GHz and larger than 25GHz 3–dB bandwidth. The chip size is 0.7mm×1.3mm including the pads. The paper reports the first stacked power amplifier designed in a rigorous way at mm-wave frequenices.
{"title":"204GHz Stacked-Power Amplifiers Designed by a Novel Two-Port Technique","authors":"Ahmed S. H. Ahmed, A. Farid, M. Urteaga, M. Rodwell","doi":"10.23919/EUMIC.2018.8539884","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539884","url":null,"abstract":"We report stacked mm-wave power amplifiers designed by a novel 2-port technique. Two power amplifiers designed into 130-nm InP HBT to verify the technique. The first design (unit cell) biased at 436mW Pdc produces 34.6mW saturated output power with 5.8% PAE at 204GHz. The amplifier has a 13.9dB peak small signal gain at 236GHz and 27 GHz 3–dB bandwidth. The chip size is 0.63mm×0.54mm including the pads. The second design combines two cells in parallel with an additional gain stage. The design consumes 1.18W Pdc and it shows a 63mW saturated output power with 4.8%PAE at 204GHz. The amplifier has a 22.7 dB peak small signal gain at 230GHz and larger than 25GHz 3–dB bandwidth. The chip size is 0.7mm×1.3mm including the pads. The paper reports the first stacked power amplifier designed in a rigorous way at mm-wave frequenices.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122475212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541708
S. Gillespie, D. Root, M. Marcu, P. Aaen
For the first time, this paper presents and validates a novel extension of the X-parameter behavioral modeling paradigm to include dynamic electro-thermal phenomena, a key source of long-term memory affecting transistors. The dynamic thermal X-parameter model (DTXM) adds a novel but straightforward method to implement envelope domain sub-circuit in a feedback loop around a conventional static X -parameter model, enabling the simulation of modulated waveform-dependent dynamic self-heating effects. The extended model is identified from conventional CW or pulsed X-parameter measurements, over a range of ambient temperatures. A re-referencing of the extracted X-parameter data to the junction temperature is performed, based on estimated or a calculated thermal resistance and thermal capacitance. The model can also be generated in the simulation environment starting from a dynamic electro-thermal compact time-domain model. The DTXM accounts for thermally-induced asymmetry of intermodulation distortion products and temperature hysteresis depending on the signal bandwidth.
{"title":"Electrothermal X-Parameters for Dynamic Modeling of RF and Microwave Power Transistors","authors":"S. Gillespie, D. Root, M. Marcu, P. Aaen","doi":"10.23919/eumc.2018.8541708","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541708","url":null,"abstract":"For the first time, this paper presents and validates a novel extension of the X-parameter behavioral modeling paradigm to include dynamic electro-thermal phenomena, a key source of long-term memory affecting transistors. The dynamic thermal X-parameter model (DTXM) adds a novel but straightforward method to implement envelope domain sub-circuit in a feedback loop around a conventional static X -parameter model, enabling the simulation of modulated waveform-dependent dynamic self-heating effects. The extended model is identified from conventional CW or pulsed X-parameter measurements, over a range of ambient temperatures. A re-referencing of the extracted X-parameter data to the junction temperature is performed, based on estimated or a calculated thermal resistance and thermal capacitance. The model can also be generated in the simulation environment starting from a dynamic electro-thermal compact time-domain model. The DTXM accounts for thermally-induced asymmetry of intermodulation distortion products and temperature hysteresis depending on the signal bandwidth.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115452076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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